1 /* 2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 11 <http://rt2x00.serialmonkey.com> 12 13 This program is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2 of the License, or 16 (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 /* 28 Module: rt2800 29 Abstract: Data structures and registers for the rt2800 modules. 30 Supported chipsets: RT2800E, RT2800ED & RT2800U. 31 */ 32 33 #ifndef RT2800_H 34 #define RT2800_H 35 36 /* 37 * RF chip defines. 38 * 39 * RF2820 2.4G 2T3R 40 * RF2850 2.4G/5G 2T3R 41 * RF2720 2.4G 1T2R 42 * RF2750 2.4G/5G 1T2R 43 * RF3020 2.4G 1T1R 44 * RF2020 2.4G B/G 45 * RF3021 2.4G 1T2R 46 * RF3022 2.4G 2T2R 47 * RF3052 2.4G/5G 2T2R 48 * RF2853 2.4G/5G 3T3R 49 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) 50 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) 51 * RF3053 2.4G/5G 3T3R(RT3563/RT3573/RT3593) 52 * RF3853 2.4G/5G 3T3R(RT3883/RT3662) 53 * RF5592 2.4G/5G 2T2R 54 * RF3070 2.4G 1T1R 55 * RF5360 2.4G 1T1R 56 * RF5362 2.4G 1T1R 57 * RF5370 2.4G 1T1R 58 * RF5390 2.4G 1T1R 59 */ 60 #define RF2820 0x0001 61 #define RF2850 0x0002 62 #define RF2720 0x0003 63 #define RF2750 0x0004 64 #define RF3020 0x0005 65 #define RF2020 0x0006 66 #define RF3021 0x0007 67 #define RF3022 0x0008 68 #define RF3052 0x0009 69 #define RF2853 0x000a 70 #define RF3320 0x000b 71 #define RF3322 0x000c 72 #define RF3053 0x000d 73 #define RF5592 0x000f 74 #define RF3070 0x3070 75 #define RF3290 0x3290 76 #define RF3853 0x3853 77 #define RF5350 0x5350 78 #define RF5360 0x5360 79 #define RF5362 0x5362 80 #define RF5370 0x5370 81 #define RF5372 0x5372 82 #define RF5390 0x5390 83 #define RF5392 0x5392 84 #define RF7620 0x7620 85 86 /* 87 * Chipset revisions. 88 */ 89 #define REV_RT2860C 0x0100 90 #define REV_RT2860D 0x0101 91 #define REV_RT2872E 0x0200 92 #define REV_RT3070E 0x0200 93 #define REV_RT3070F 0x0201 94 #define REV_RT3071E 0x0211 95 #define REV_RT3090E 0x0211 96 #define REV_RT3390E 0x0211 97 #define REV_RT3593E 0x0211 98 #define REV_RT5390F 0x0502 99 #define REV_RT5370G 0x0503 100 #define REV_RT5390R 0x1502 101 #define REV_RT5592C 0x0221 102 103 #define DEFAULT_RSSI_OFFSET 120 104 105 /* 106 * Register layout information. 107 */ 108 #define CSR_REG_BASE 0x1000 109 #define CSR_REG_SIZE 0x0800 110 #define EEPROM_BASE 0x0000 111 #define EEPROM_SIZE 0x0200 112 #define BBP_BASE 0x0000 113 #define BBP_SIZE 0x00ff 114 #define RF_BASE 0x0004 115 #define RF_SIZE 0x0010 116 #define RFCSR_BASE 0x0000 117 #define RFCSR_SIZE 0x0040 118 119 /* 120 * Number of TX queues. 121 */ 122 #define NUM_TX_QUEUES 4 123 124 /* 125 * Registers. 126 */ 127 128 129 /* 130 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number. 131 */ 132 #define MAC_CSR0_3290 0x0000 133 134 /* 135 * E2PROM_CSR: PCI EEPROM control register. 136 * RELOAD: Write 1 to reload eeprom content. 137 * TYPE: 0: 93c46, 1:93c66. 138 * LOAD_STATUS: 1:loading, 0:done. 139 */ 140 #define E2PROM_CSR 0x0004 141 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) 142 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) 143 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) 144 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) 145 #define E2PROM_CSR_TYPE FIELD32(0x00000030) 146 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) 147 #define E2PROM_CSR_RELOAD FIELD32(0x00000080) 148 149 /* 150 * CMB_CTRL_CFG 151 */ 152 #define CMB_CTRL 0x0020 153 #define AUX_OPT_BIT0 FIELD32(0x00000001) 154 #define AUX_OPT_BIT1 FIELD32(0x00000002) 155 #define AUX_OPT_BIT2 FIELD32(0x00000004) 156 #define AUX_OPT_BIT3 FIELD32(0x00000008) 157 #define AUX_OPT_BIT4 FIELD32(0x00000010) 158 #define AUX_OPT_BIT5 FIELD32(0x00000020) 159 #define AUX_OPT_BIT6 FIELD32(0x00000040) 160 #define AUX_OPT_BIT7 FIELD32(0x00000080) 161 #define AUX_OPT_BIT8 FIELD32(0x00000100) 162 #define AUX_OPT_BIT9 FIELD32(0x00000200) 163 #define AUX_OPT_BIT10 FIELD32(0x00000400) 164 #define AUX_OPT_BIT11 FIELD32(0x00000800) 165 #define AUX_OPT_BIT12 FIELD32(0x00001000) 166 #define AUX_OPT_BIT13 FIELD32(0x00002000) 167 #define AUX_OPT_BIT14 FIELD32(0x00004000) 168 #define AUX_OPT_BIT15 FIELD32(0x00008000) 169 #define LDO25_LEVEL FIELD32(0x00030000) 170 #define LDO25_LARGEA FIELD32(0x00040000) 171 #define LDO25_FRC_ON FIELD32(0x00080000) 172 #define CMB_RSV FIELD32(0x00300000) 173 #define XTAL_RDY FIELD32(0x00400000) 174 #define PLL_LD FIELD32(0x00800000) 175 #define LDO_CORE_LEVEL FIELD32(0x0F000000) 176 #define LDO_BGSEL FIELD32(0x30000000) 177 #define LDO3_EN FIELD32(0x40000000) 178 #define LDO0_EN FIELD32(0x80000000) 179 180 /* 181 * EFUSE_CSR_3290: RT3290 EEPROM 182 */ 183 #define EFUSE_CTRL_3290 0x0024 184 185 /* 186 * EFUSE_DATA3 of 3290 187 */ 188 #define EFUSE_DATA3_3290 0x0028 189 190 /* 191 * EFUSE_DATA2 of 3290 192 */ 193 #define EFUSE_DATA2_3290 0x002c 194 195 /* 196 * EFUSE_DATA1 of 3290 197 */ 198 #define EFUSE_DATA1_3290 0x0030 199 200 /* 201 * EFUSE_DATA0 of 3290 202 */ 203 #define EFUSE_DATA0_3290 0x0034 204 205 /* 206 * OSC_CTRL_CFG 207 * Ring oscillator configuration 208 */ 209 #define OSC_CTRL 0x0038 210 #define OSC_REF_CYCLE FIELD32(0x00001fff) 211 #define OSC_RSV FIELD32(0x0000e000) 212 #define OSC_CAL_CNT FIELD32(0x0fff0000) 213 #define OSC_CAL_ACK FIELD32(0x10000000) 214 #define OSC_CLK_32K_VLD FIELD32(0x20000000) 215 #define OSC_CAL_REQ FIELD32(0x40000000) 216 #define OSC_ROSC_EN FIELD32(0x80000000) 217 218 /* 219 * COEX_CFG_0 220 */ 221 #define COEX_CFG0 0x0040 222 #define COEX_CFG_ANT FIELD32(0xff000000) 223 /* 224 * COEX_CFG_1 225 */ 226 #define COEX_CFG1 0x0044 227 228 /* 229 * COEX_CFG_2 230 */ 231 #define COEX_CFG2 0x0048 232 #define BT_COEX_CFG1 FIELD32(0xff000000) 233 #define BT_COEX_CFG0 FIELD32(0x00ff0000) 234 #define WL_COEX_CFG1 FIELD32(0x0000ff00) 235 #define WL_COEX_CFG0 FIELD32(0x000000ff) 236 /* 237 * PLL_CTRL_CFG 238 * PLL configuration register 239 */ 240 #define PLL_CTRL 0x0050 241 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff) 242 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00) 243 #define PLL_CONTROL FIELD32(0x00070000) 244 #define PLL_LPF_R1 FIELD32(0x00080000) 245 #define PLL_LPF_C1_CTRL FIELD32(0x00300000) 246 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000) 247 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000) 248 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000) 249 #define PLL_LOCK_CTRL FIELD32(0x70000000) 250 #define PLL_VBGBK_EN FIELD32(0x80000000) 251 252 253 /* 254 * WLAN_CTRL_CFG 255 * RT3290 wlan configuration 256 */ 257 #define WLAN_FUN_CTRL 0x0080 258 #define WLAN_EN FIELD32(0x00000001) 259 #define WLAN_CLK_EN FIELD32(0x00000002) 260 #define WLAN_RSV1 FIELD32(0x00000004) 261 #define WLAN_RESET FIELD32(0x00000008) 262 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010) 263 #define FRC_WL_ANT_SET FIELD32(0x00000020) 264 #define INV_TR_SW0 FIELD32(0x00000040) 265 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100) 266 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200) 267 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400) 268 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800) 269 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000) 270 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000) 271 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000) 272 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000) 273 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00) 274 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000) 275 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000) 276 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000) 277 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000) 278 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000) 279 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000) 280 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000) 281 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000) 282 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000) 283 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000) 284 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000) 285 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000) 286 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000) 287 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000) 288 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000) 289 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000) 290 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000) 291 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000) 292 293 /* 294 * AUX_CTRL: Aux/PCI-E related configuration 295 */ 296 #define AUX_CTRL 0x10c 297 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002) 298 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400) 299 300 /* 301 * OPT_14: Unknown register used by rt3xxx devices. 302 */ 303 #define OPT_14_CSR 0x0114 304 #define OPT_14_CSR_BIT0 FIELD32(0x00000001) 305 306 /* 307 * INT_SOURCE_CSR: Interrupt source register. 308 * Write one to clear corresponding bit. 309 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO 310 */ 311 #define INT_SOURCE_CSR 0x0200 312 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) 313 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) 314 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) 315 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) 316 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) 317 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) 318 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) 319 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 320 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 321 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) 322 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) 323 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) 324 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) 325 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 326 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) 327 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) 328 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) 329 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) 330 331 /* 332 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. 333 */ 334 #define INT_MASK_CSR 0x0204 335 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) 336 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) 337 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) 338 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) 339 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) 340 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) 341 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) 342 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) 343 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) 344 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) 345 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) 346 #define INT_MASK_CSR_TBTT FIELD32(0x00000800) 347 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) 348 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) 349 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) 350 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) 351 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) 352 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) 353 354 /* 355 * WPDMA_GLO_CFG 356 */ 357 #define WPDMA_GLO_CFG 0x0208 358 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) 359 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) 360 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) 361 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) 362 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) 363 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) 364 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) 365 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) 366 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) 367 368 /* 369 * WPDMA_RST_IDX 370 */ 371 #define WPDMA_RST_IDX 0x020c 372 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) 373 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) 374 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) 375 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) 376 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) 377 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) 378 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) 379 380 /* 381 * DELAY_INT_CFG 382 */ 383 #define DELAY_INT_CFG 0x0210 384 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) 385 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) 386 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) 387 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) 388 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) 389 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) 390 391 /* 392 * WMM_AIFSN_CFG: Aifsn for each EDCA AC 393 * AIFSN0: AC_VO 394 * AIFSN1: AC_VI 395 * AIFSN2: AC_BE 396 * AIFSN3: AC_BK 397 */ 398 #define WMM_AIFSN_CFG 0x0214 399 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) 400 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) 401 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) 402 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) 403 404 /* 405 * WMM_CWMIN_CSR: CWmin for each EDCA AC 406 * CWMIN0: AC_VO 407 * CWMIN1: AC_VI 408 * CWMIN2: AC_BE 409 * CWMIN3: AC_BK 410 */ 411 #define WMM_CWMIN_CFG 0x0218 412 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) 413 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) 414 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) 415 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) 416 417 /* 418 * WMM_CWMAX_CSR: CWmax for each EDCA AC 419 * CWMAX0: AC_VO 420 * CWMAX1: AC_VI 421 * CWMAX2: AC_BE 422 * CWMAX3: AC_BK 423 */ 424 #define WMM_CWMAX_CFG 0x021c 425 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) 426 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) 427 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) 428 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) 429 430 /* 431 * AC_TXOP0: AC_VO/AC_VI TXOP register 432 * AC0TXOP: AC_VO in unit of 32us 433 * AC1TXOP: AC_VI in unit of 32us 434 */ 435 #define WMM_TXOP0_CFG 0x0220 436 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) 437 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) 438 439 /* 440 * AC_TXOP1: AC_BE/AC_BK TXOP register 441 * AC2TXOP: AC_BE in unit of 32us 442 * AC3TXOP: AC_BK in unit of 32us 443 */ 444 #define WMM_TXOP1_CFG 0x0224 445 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) 446 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) 447 448 /* 449 * GPIO_CTRL: 450 * GPIO_CTRL_VALx: GPIO value 451 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input 452 */ 453 #define GPIO_CTRL 0x0228 454 #define GPIO_CTRL_VAL0 FIELD32(0x00000001) 455 #define GPIO_CTRL_VAL1 FIELD32(0x00000002) 456 #define GPIO_CTRL_VAL2 FIELD32(0x00000004) 457 #define GPIO_CTRL_VAL3 FIELD32(0x00000008) 458 #define GPIO_CTRL_VAL4 FIELD32(0x00000010) 459 #define GPIO_CTRL_VAL5 FIELD32(0x00000020) 460 #define GPIO_CTRL_VAL6 FIELD32(0x00000040) 461 #define GPIO_CTRL_VAL7 FIELD32(0x00000080) 462 #define GPIO_CTRL_DIR0 FIELD32(0x00000100) 463 #define GPIO_CTRL_DIR1 FIELD32(0x00000200) 464 #define GPIO_CTRL_DIR2 FIELD32(0x00000400) 465 #define GPIO_CTRL_DIR3 FIELD32(0x00000800) 466 #define GPIO_CTRL_DIR4 FIELD32(0x00001000) 467 #define GPIO_CTRL_DIR5 FIELD32(0x00002000) 468 #define GPIO_CTRL_DIR6 FIELD32(0x00004000) 469 #define GPIO_CTRL_DIR7 FIELD32(0x00008000) 470 #define GPIO_CTRL_VAL8 FIELD32(0x00010000) 471 #define GPIO_CTRL_VAL9 FIELD32(0x00020000) 472 #define GPIO_CTRL_VAL10 FIELD32(0x00040000) 473 #define GPIO_CTRL_DIR8 FIELD32(0x01000000) 474 #define GPIO_CTRL_DIR9 FIELD32(0x02000000) 475 #define GPIO_CTRL_DIR10 FIELD32(0x04000000) 476 477 /* 478 * MCU_CMD_CFG 479 */ 480 #define MCU_CMD_CFG 0x022c 481 482 /* 483 * AC_VO register offsets 484 */ 485 #define TX_BASE_PTR0 0x0230 486 #define TX_MAX_CNT0 0x0234 487 #define TX_CTX_IDX0 0x0238 488 #define TX_DTX_IDX0 0x023c 489 490 /* 491 * AC_VI register offsets 492 */ 493 #define TX_BASE_PTR1 0x0240 494 #define TX_MAX_CNT1 0x0244 495 #define TX_CTX_IDX1 0x0248 496 #define TX_DTX_IDX1 0x024c 497 498 /* 499 * AC_BE register offsets 500 */ 501 #define TX_BASE_PTR2 0x0250 502 #define TX_MAX_CNT2 0x0254 503 #define TX_CTX_IDX2 0x0258 504 #define TX_DTX_IDX2 0x025c 505 506 /* 507 * AC_BK register offsets 508 */ 509 #define TX_BASE_PTR3 0x0260 510 #define TX_MAX_CNT3 0x0264 511 #define TX_CTX_IDX3 0x0268 512 #define TX_DTX_IDX3 0x026c 513 514 /* 515 * HCCA register offsets 516 */ 517 #define TX_BASE_PTR4 0x0270 518 #define TX_MAX_CNT4 0x0274 519 #define TX_CTX_IDX4 0x0278 520 #define TX_DTX_IDX4 0x027c 521 522 /* 523 * MGMT register offsets 524 */ 525 #define TX_BASE_PTR5 0x0280 526 #define TX_MAX_CNT5 0x0284 527 #define TX_CTX_IDX5 0x0288 528 #define TX_DTX_IDX5 0x028c 529 530 /* 531 * RX register offsets 532 */ 533 #define RX_BASE_PTR 0x0290 534 #define RX_MAX_CNT 0x0294 535 #define RX_CRX_IDX 0x0298 536 #define RX_DRX_IDX 0x029c 537 538 /* 539 * USB_DMA_CFG 540 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 541 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 542 * PHY_CLEAR: phy watch dog enable. 543 * TX_CLEAR: Clear USB DMA TX path. 544 * TXOP_HALT: Halt TXOP count down when TX buffer is full. 545 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. 546 * RX_BULK_EN: Enable USB DMA Rx. 547 * TX_BULK_EN: Enable USB DMA Tx. 548 * EP_OUT_VALID: OUT endpoint data valid. 549 * RX_BUSY: USB DMA RX FSM busy. 550 * TX_BUSY: USB DMA TX FSM busy. 551 */ 552 #define USB_DMA_CFG 0x02a0 553 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) 554 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) 555 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) 556 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) 557 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) 558 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) 559 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) 560 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) 561 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) 562 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) 563 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) 564 565 /* 566 * US_CYC_CNT 567 * BT_MODE_EN: Bluetooth mode enable 568 * CLOCK CYCLE: Clock cycle count in 1us. 569 * PCI:0x21, PCIE:0x7d, USB:0x1e 570 */ 571 #define US_CYC_CNT 0x02a4 572 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100) 573 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) 574 575 /* 576 * PBF_SYS_CTRL 577 * HOST_RAM_WRITE: enable Host program ram write selection 578 */ 579 #define PBF_SYS_CTRL 0x0400 580 #define PBF_SYS_CTRL_READY FIELD32(0x00000080) 581 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) 582 583 /* 584 * HOST-MCU shared memory 585 */ 586 #define HOST_CMD_CSR 0x0404 587 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) 588 589 /* 590 * PBF registers 591 * Most are for debug. Driver doesn't touch PBF register. 592 */ 593 #define PBF_CFG 0x0408 594 #define PBF_MAX_PCNT 0x040c 595 #define PBF_CTRL 0x0410 596 #define PBF_INT_STA 0x0414 597 #define PBF_INT_ENA 0x0418 598 599 /* 600 * BCN_OFFSET0: 601 */ 602 #define BCN_OFFSET0 0x042c 603 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) 604 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) 605 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) 606 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) 607 608 /* 609 * BCN_OFFSET1: 610 */ 611 #define BCN_OFFSET1 0x0430 612 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) 613 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) 614 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) 615 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) 616 617 /* 618 * TXRXQ_PCNT: PBF register 619 * PCNT_TX0Q: Page count for TX hardware queue 0 620 * PCNT_TX1Q: Page count for TX hardware queue 1 621 * PCNT_TX2Q: Page count for TX hardware queue 2 622 * PCNT_RX0Q: Page count for RX hardware queue 623 */ 624 #define TXRXQ_PCNT 0x0438 625 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff) 626 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00) 627 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000) 628 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000) 629 630 /* 631 * PBF register 632 * Debug. Driver doesn't touch PBF register. 633 */ 634 #define PBF_DBG 0x043c 635 636 /* 637 * RF registers 638 */ 639 #define RF_CSR_CFG 0x0500 640 #define RF_CSR_CFG_DATA FIELD32(0x000000ff) 641 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00) 642 #define RF_CSR_CFG_WRITE FIELD32(0x00010000) 643 #define RF_CSR_CFG_BUSY FIELD32(0x00020000) 644 645 /* 646 * MT7620 RF registers (reversed order) 647 */ 648 #define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00) 649 #define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000) 650 #define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010) 651 #define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001) 652 653 /* undocumented registers for calibration of new MAC */ 654 #define RF_CONTROL0 0x0518 655 #define RF_BYPASS0 0x051c 656 #define RF_CONTROL1 0x0520 657 #define RF_BYPASS1 0x0524 658 #define RF_CONTROL2 0x0528 659 #define RF_BYPASS2 0x052c 660 #define RF_CONTROL3 0x0530 661 #define RF_BYPASS3 0x0534 662 663 /* 664 * EFUSE_CSR: RT30x0 EEPROM 665 */ 666 #define EFUSE_CTRL 0x0580 667 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) 668 #define EFUSE_CTRL_MODE FIELD32(0x000000c0) 669 #define EFUSE_CTRL_KICK FIELD32(0x40000000) 670 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000) 671 672 /* 673 * EFUSE_DATA0 674 */ 675 #define EFUSE_DATA0 0x0590 676 677 /* 678 * EFUSE_DATA1 679 */ 680 #define EFUSE_DATA1 0x0594 681 682 /* 683 * EFUSE_DATA2 684 */ 685 #define EFUSE_DATA2 0x0598 686 687 /* 688 * EFUSE_DATA3 689 */ 690 #define EFUSE_DATA3 0x059c 691 692 /* 693 * LDO_CFG0 694 */ 695 #define LDO_CFG0 0x05d4 696 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff) 697 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) 698 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) 699 #define LDO_CFG0_BGSEL FIELD32(0x03000000) 700 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) 701 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) 702 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) 703 704 /* 705 * GPIO_SWITCH 706 */ 707 #define GPIO_SWITCH 0x05dc 708 #define GPIO_SWITCH_0 FIELD32(0x00000001) 709 #define GPIO_SWITCH_1 FIELD32(0x00000002) 710 #define GPIO_SWITCH_2 FIELD32(0x00000004) 711 #define GPIO_SWITCH_3 FIELD32(0x00000008) 712 #define GPIO_SWITCH_4 FIELD32(0x00000010) 713 #define GPIO_SWITCH_5 FIELD32(0x00000020) 714 #define GPIO_SWITCH_6 FIELD32(0x00000040) 715 #define GPIO_SWITCH_7 FIELD32(0x00000080) 716 717 /* 718 * FIXME: where the DEBUG_INDEX name come from? 719 */ 720 #define MAC_DEBUG_INDEX 0x05e8 721 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000) 722 723 /* 724 * MAC Control/Status Registers(CSR). 725 * Some values are set in TU, whereas 1 TU == 1024 us. 726 */ 727 728 /* 729 * MAC_CSR0: ASIC revision number. 730 * ASIC_REV: 0 731 * ASIC_VER: 2860 or 2870 732 */ 733 #define MAC_CSR0 0x1000 734 #define MAC_CSR0_REVISION FIELD32(0x0000ffff) 735 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000) 736 737 /* 738 * MAC_SYS_CTRL: 739 */ 740 #define MAC_SYS_CTRL 0x1004 741 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) 742 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) 743 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) 744 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) 745 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) 746 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) 747 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) 748 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) 749 750 /* 751 * MAC_ADDR_DW0: STA MAC register 0 752 */ 753 #define MAC_ADDR_DW0 0x1008 754 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) 755 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) 756 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) 757 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) 758 759 /* 760 * MAC_ADDR_DW1: STA MAC register 1 761 * UNICAST_TO_ME_MASK: 762 * Used to mask off bits from byte 5 of the MAC address 763 * to determine the UNICAST_TO_ME bit for RX frames. 764 * The full mask is complemented by BSS_ID_MASK: 765 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK 766 */ 767 #define MAC_ADDR_DW1 0x100c 768 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) 769 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) 770 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) 771 772 /* 773 * MAC_BSSID_DW0: BSSID register 0 774 */ 775 #define MAC_BSSID_DW0 0x1010 776 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) 777 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) 778 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) 779 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) 780 781 /* 782 * MAC_BSSID_DW1: BSSID register 1 783 * BSS_ID_MASK: 784 * 0: 1-BSSID mode (BSS index = 0) 785 * 1: 2-BSSID mode (BSS index: Byte5, bit 0) 786 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) 787 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) 788 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the 789 * BSSID. This will make sure that those bits will be ignored 790 * when determining the MY_BSS of RX frames. 791 */ 792 #define MAC_BSSID_DW1 0x1014 793 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) 794 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) 795 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) 796 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) 797 798 /* 799 * MAX_LEN_CFG: Maximum frame length register. 800 * MAX_MPDU: rt2860b max 16k bytes 801 * MAX_PSDU: Maximum PSDU length 802 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 803 */ 804 #define MAX_LEN_CFG 0x1018 805 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) 806 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) 807 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) 808 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) 809 810 /* 811 * BBP_CSR_CFG: BBP serial control register 812 * VALUE: Register value to program into BBP 813 * REG_NUM: Selected BBP register 814 * READ_CONTROL: 0 write BBP, 1 read BBP 815 * BUSY: ASIC is busy executing BBP commands 816 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks 817 * BBP_RW_MODE: 0 serial, 1 parallel 818 */ 819 #define BBP_CSR_CFG 0x101c 820 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) 821 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) 822 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) 823 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) 824 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) 825 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) 826 827 /* 828 * RF_CSR_CFG0: RF control register 829 * REGID_AND_VALUE: Register value to program into RF 830 * BITWIDTH: Selected RF register 831 * STANDBYMODE: 0 high when standby, 1 low when standby 832 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate 833 * BUSY: ASIC is busy executing RF commands 834 */ 835 #define RF_CSR_CFG0 0x1020 836 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) 837 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) 838 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) 839 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) 840 #define RF_CSR_CFG0_SEL FIELD32(0x40000000) 841 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) 842 843 /* 844 * RF_CSR_CFG1: RF control register 845 * REGID_AND_VALUE: Register value to program into RF 846 * RFGAP: Gap between BB_CONTROL_RF and RF_LE 847 * 0: 3 system clock cycle (37.5usec) 848 * 1: 5 system clock cycle (62.5usec) 849 */ 850 #define RF_CSR_CFG1 0x1024 851 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) 852 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) 853 854 /* 855 * RF_CSR_CFG2: RF control register 856 * VALUE: Register value to program into RF 857 */ 858 #define RF_CSR_CFG2 0x1028 859 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) 860 861 /* 862 * LED_CFG: LED control 863 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1) 864 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1) 865 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2) 866 * color LED's: 867 * 0: off 868 * 1: blinking upon TX2 869 * 2: periodic slow blinking 870 * 3: always on 871 * LED polarity: 872 * 0: active low 873 * 1: active high 874 */ 875 #define LED_CFG 0x102c 876 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) 877 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) 878 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) 879 #define LED_CFG_R_LED_MODE FIELD32(0x03000000) 880 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) 881 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) 882 #define LED_CFG_LED_POLAR FIELD32(0x40000000) 883 884 /* 885 * AMPDU_BA_WINSIZE: Force BlockAck window size 886 * FORCE_WINSIZE_ENABLE: 887 * 0: Disable forcing of BlockAck window size 888 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck 889 * window size values in the TXWI 890 * FORCE_WINSIZE: BlockAck window size 891 */ 892 #define AMPDU_BA_WINSIZE 0x1040 893 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020) 894 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f) 895 896 /* 897 * XIFS_TIME_CFG: MAC timing 898 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX 899 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX 900 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX 901 * when MAC doesn't reference BBP signal BBRXEND 902 * EIFS: unit 1us 903 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer 904 * 905 */ 906 #define XIFS_TIME_CFG 0x1100 907 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) 908 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) 909 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) 910 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) 911 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) 912 913 /* 914 * BKOFF_SLOT_CFG: 915 */ 916 #define BKOFF_SLOT_CFG 0x1104 917 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) 918 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) 919 920 /* 921 * NAV_TIME_CFG: 922 */ 923 #define NAV_TIME_CFG 0x1108 924 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) 925 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) 926 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) 927 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) 928 929 /* 930 * CH_TIME_CFG: count as channel busy 931 * EIFS_BUSY: Count EIFS as channel busy 932 * NAV_BUSY: Count NAS as channel busy 933 * RX_BUSY: Count RX as channel busy 934 * TX_BUSY: Count TX as channel busy 935 * TMR_EN: Enable channel statistics timer 936 */ 937 #define CH_TIME_CFG 0x110c 938 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010) 939 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008) 940 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004) 941 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002) 942 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001) 943 944 /* 945 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us 946 */ 947 #define PBF_LIFE_TIMER 0x1110 948 949 /* 950 * BCN_TIME_CFG: 951 * BEACON_INTERVAL: in unit of 1/16 TU 952 * TSF_TICKING: Enable TSF auto counting 953 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode 954 * BEACON_GEN: Enable beacon generator 955 */ 956 #define BCN_TIME_CFG 0x1114 957 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) 958 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) 959 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) 960 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) 961 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) 962 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) 963 964 /* 965 * TBTT_SYNC_CFG: 966 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots 967 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots 968 */ 969 #define TBTT_SYNC_CFG 0x1118 970 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff) 971 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00) 972 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000) 973 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000) 974 975 /* 976 * TSF_TIMER_DW0: Local lsb TSF timer, read-only 977 */ 978 #define TSF_TIMER_DW0 0x111c 979 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) 980 981 /* 982 * TSF_TIMER_DW1: Local msb TSF timer, read-only 983 */ 984 #define TSF_TIMER_DW1 0x1120 985 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) 986 987 /* 988 * TBTT_TIMER: TImer remains till next TBTT, read-only 989 */ 990 #define TBTT_TIMER 0x1124 991 992 /* 993 * INT_TIMER_CFG: timer configuration 994 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU 995 * GP_TIMER: period of general purpose timer in units of 1/16 TU 996 */ 997 #define INT_TIMER_CFG 0x1128 998 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff) 999 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000) 1000 1001 /* 1002 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable 1003 */ 1004 #define INT_TIMER_EN 0x112c 1005 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001) 1006 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) 1007 1008 /* 1009 * CH_IDLE_STA: channel idle time (in us) 1010 */ 1011 #define CH_IDLE_STA 0x1130 1012 1013 /* 1014 * CH_BUSY_STA: channel busy time on primary channel (in us) 1015 */ 1016 #define CH_BUSY_STA 0x1134 1017 1018 /* 1019 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us) 1020 */ 1021 #define CH_BUSY_STA_SEC 0x1138 1022 1023 /* 1024 * MAC_STATUS_CFG: 1025 * BBP_RF_BUSY: When set to 0, BBP and RF are stable. 1026 * if 1 or higher one of the 2 registers is busy. 1027 */ 1028 #define MAC_STATUS_CFG 0x1200 1029 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) 1030 1031 /* 1032 * PWR_PIN_CFG: 1033 */ 1034 #define PWR_PIN_CFG 0x1204 1035 1036 /* 1037 * AUTOWAKEUP_CFG: Manual power control / status register 1038 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set 1039 * AUTOWAKE: 0:sleep, 1:awake 1040 */ 1041 #define AUTOWAKEUP_CFG 0x1208 1042 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) 1043 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) 1044 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) 1045 1046 /* 1047 * MIMO_PS_CFG: MIMO Power-save Configuration 1048 */ 1049 #define MIMO_PS_CFG 0x1210 1050 #define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001) 1051 #define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006) 1052 #define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008) 1053 #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010) 1054 #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020) 1055 1056 /* 1057 * EDCA_AC0_CFG: 1058 */ 1059 #define EDCA_AC0_CFG 0x1300 1060 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) 1061 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) 1062 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) 1063 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) 1064 1065 /* 1066 * EDCA_AC1_CFG: 1067 */ 1068 #define EDCA_AC1_CFG 0x1304 1069 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) 1070 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) 1071 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) 1072 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) 1073 1074 /* 1075 * EDCA_AC2_CFG: 1076 */ 1077 #define EDCA_AC2_CFG 0x1308 1078 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) 1079 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) 1080 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) 1081 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) 1082 1083 /* 1084 * EDCA_AC3_CFG: 1085 */ 1086 #define EDCA_AC3_CFG 0x130c 1087 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) 1088 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) 1089 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) 1090 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) 1091 1092 /* 1093 * EDCA_TID_AC_MAP: 1094 */ 1095 #define EDCA_TID_AC_MAP 0x1310 1096 1097 /* 1098 * TX_PWR_CFG: 1099 */ 1100 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) 1101 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) 1102 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) 1103 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) 1104 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) 1105 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) 1106 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) 1107 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) 1108 1109 /* 1110 * TX_PWR_CFG_0: 1111 */ 1112 #define TX_PWR_CFG_0 0x1314 1113 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) 1114 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) 1115 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) 1116 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) 1117 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) 1118 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) 1119 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) 1120 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) 1121 /* bits for 3T devices */ 1122 #define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f) 1123 #define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0) 1124 #define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00) 1125 #define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000) 1126 #define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000) 1127 #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000) 1128 #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000) 1129 #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000) 1130 /* bits for new 2T devices */ 1131 #define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff) 1132 #define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00) 1133 #define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000) 1134 #define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000) 1135 1136 1137 /* 1138 * TX_PWR_CFG_1: 1139 */ 1140 #define TX_PWR_CFG_1 0x1318 1141 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) 1142 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) 1143 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) 1144 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) 1145 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) 1146 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) 1147 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) 1148 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) 1149 /* bits for 3T devices */ 1150 #define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f) 1151 #define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0) 1152 #define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00) 1153 #define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000) 1154 #define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000) 1155 #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000) 1156 #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000) 1157 #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000) 1158 /* bits for new 2T devices */ 1159 #define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff) 1160 #define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00) 1161 #define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000) 1162 #define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000) 1163 1164 /* 1165 * TX_PWR_CFG_2: 1166 */ 1167 #define TX_PWR_CFG_2 0x131c 1168 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) 1169 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) 1170 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) 1171 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) 1172 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) 1173 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) 1174 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) 1175 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) 1176 /* bits for 3T devices */ 1177 #define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f) 1178 #define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0) 1179 #define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00) 1180 #define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000) 1181 #define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000) 1182 #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000) 1183 #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000) 1184 #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000) 1185 /* bits for new 2T devices */ 1186 #define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff) 1187 #define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00) 1188 #define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000) 1189 #define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000) 1190 1191 /* 1192 * TX_PWR_CFG_3: 1193 */ 1194 #define TX_PWR_CFG_3 0x1320 1195 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) 1196 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) 1197 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) 1198 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) 1199 #define TX_PWR_CFG_3_UNKNOWN1 FIELD32(0x000f0000) 1200 #define TX_PWR_CFG_3_UNKNOWN2 FIELD32(0x00f00000) 1201 #define TX_PWR_CFG_3_UNKNOWN3 FIELD32(0x0f000000) 1202 #define TX_PWR_CFG_3_UNKNOWN4 FIELD32(0xf0000000) 1203 /* bits for 3T devices */ 1204 #define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f) 1205 #define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0) 1206 #define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00) 1207 #define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000) 1208 #define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000) 1209 #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000) 1210 #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000) 1211 #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000) 1212 /* bits for new 2T devices */ 1213 #define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff) 1214 #define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00) 1215 #define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000) 1216 #define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000) 1217 1218 /* 1219 * TX_PWR_CFG_4: 1220 */ 1221 #define TX_PWR_CFG_4 0x1324 1222 #define TX_PWR_CFG_4_UNKNOWN5 FIELD32(0x0000000f) 1223 #define TX_PWR_CFG_4_UNKNOWN6 FIELD32(0x000000f0) 1224 #define TX_PWR_CFG_4_UNKNOWN7 FIELD32(0x00000f00) 1225 #define TX_PWR_CFG_4_UNKNOWN8 FIELD32(0x0000f000) 1226 /* bits for 3T devices */ 1227 #define TX_PWR_CFG_4_STBC4_CH0 FIELD32(0x0000000f) 1228 #define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0) 1229 #define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00) 1230 #define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000) 1231 /* bits for new 2T devices */ 1232 #define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff) 1233 #define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00) 1234 1235 /* 1236 * TX_PIN_CFG: 1237 */ 1238 #define TX_PIN_CFG 0x1328 1239 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0 1240 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) 1241 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) 1242 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) 1243 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) 1244 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) 1245 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) 1246 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) 1247 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) 1248 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) 1249 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) 1250 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) 1251 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) 1252 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) 1253 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) 1254 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) 1255 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) 1256 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) 1257 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) 1258 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) 1259 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) 1260 #define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000) 1261 #define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000) 1262 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000) 1263 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000) 1264 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000) 1265 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000) 1266 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000) 1267 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000) 1268 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000) 1269 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000) 1270 1271 /* 1272 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz 1273 */ 1274 #define TX_BAND_CFG 0x132c 1275 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) 1276 #define TX_BAND_CFG_A FIELD32(0x00000002) 1277 #define TX_BAND_CFG_BG FIELD32(0x00000004) 1278 1279 /* 1280 * TX_SW_CFG0: 1281 */ 1282 #define TX_SW_CFG0 0x1330 1283 1284 /* 1285 * TX_SW_CFG1: 1286 */ 1287 #define TX_SW_CFG1 0x1334 1288 1289 /* 1290 * TX_SW_CFG2: 1291 */ 1292 #define TX_SW_CFG2 0x1338 1293 1294 /* 1295 * TXOP_THRES_CFG: 1296 */ 1297 #define TXOP_THRES_CFG 0x133c 1298 1299 /* 1300 * TXOP_CTRL_CFG: 1301 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation 1302 * AC_TRUN_EN: Enable/Disable truncation for AC change 1303 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change 1304 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode 1305 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS 1306 * RESERVED_TRUN_EN: Reserved 1307 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection 1308 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz 1309 * transmissions if extension CCA is clear). 1310 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us) 1311 * EXT_CWMIN: CwMin for extension channel backoff 1312 * 0: Disabled 1313 * 1314 */ 1315 #define TXOP_CTRL_CFG 0x1340 1316 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001) 1317 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002) 1318 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004) 1319 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008) 1320 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010) 1321 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020) 1322 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040) 1323 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080) 1324 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00) 1325 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000) 1326 1327 /* 1328 * TX_RTS_CFG: 1329 * RTS_THRES: unit:byte 1330 * RTS_FBK_EN: enable rts rate fallback 1331 */ 1332 #define TX_RTS_CFG 0x1344 1333 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) 1334 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) 1335 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) 1336 1337 /* 1338 * TX_TIMEOUT_CFG: 1339 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us 1340 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure 1341 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. 1342 * it is recommended that: 1343 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) 1344 */ 1345 #define TX_TIMEOUT_CFG 0x1348 1346 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) 1347 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) 1348 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) 1349 1350 /* 1351 * TX_RTY_CFG: 1352 * SHORT_RTY_LIMIT: short retry limit 1353 * LONG_RTY_LIMIT: long retry limit 1354 * LONG_RTY_THRE: Long retry threshoold 1355 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode 1356 * 0:expired by retry limit, 1: expired by mpdu life timer 1357 * AGG_RTY_MODE: Aggregate MPDU retry mode 1358 * 0:expired by retry limit, 1: expired by mpdu life timer 1359 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable 1360 */ 1361 #define TX_RTY_CFG 0x134c 1362 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) 1363 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) 1364 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) 1365 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) 1366 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) 1367 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) 1368 1369 /* 1370 * TX_LINK_CFG: 1371 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us 1372 * MFB_ENABLE: TX apply remote MFB 1:enable 1373 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable 1374 * 0: not apply remote remote unsolicit (MFS=7) 1375 * TX_MRQ_EN: MCS request TX enable 1376 * TX_RDG_EN: RDG TX enable 1377 * TX_CF_ACK_EN: Piggyback CF-ACK enable 1378 * REMOTE_MFB: remote MCS feedback 1379 * REMOTE_MFS: remote MCS feedback sequence number 1380 */ 1381 #define TX_LINK_CFG 0x1350 1382 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) 1383 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) 1384 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) 1385 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) 1386 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) 1387 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) 1388 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) 1389 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) 1390 1391 /* 1392 * HT_FBK_CFG0: 1393 */ 1394 #define HT_FBK_CFG0 0x1354 1395 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) 1396 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) 1397 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) 1398 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) 1399 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) 1400 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) 1401 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) 1402 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) 1403 1404 /* 1405 * HT_FBK_CFG1: 1406 */ 1407 #define HT_FBK_CFG1 0x1358 1408 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) 1409 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) 1410 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) 1411 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) 1412 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) 1413 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) 1414 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) 1415 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) 1416 1417 /* 1418 * LG_FBK_CFG0: 1419 */ 1420 #define LG_FBK_CFG0 0x135c 1421 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) 1422 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) 1423 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) 1424 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) 1425 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) 1426 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) 1427 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) 1428 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) 1429 1430 /* 1431 * LG_FBK_CFG1: 1432 */ 1433 #define LG_FBK_CFG1 0x1360 1434 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) 1435 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) 1436 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) 1437 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) 1438 1439 /* 1440 * CCK_PROT_CFG: CCK Protection 1441 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) 1442 * PROTECT_CTRL: Protection control frame type for CCK TX 1443 * 0:none, 1:RTS/CTS, 2:CTS-to-self 1444 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV 1445 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV 1446 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow 1447 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow 1448 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow 1449 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow 1450 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow 1451 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow 1452 * RTS_TH_EN: RTS threshold enable on CCK TX 1453 */ 1454 #define CCK_PROT_CFG 0x1364 1455 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1456 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1457 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1458 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1459 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1460 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1461 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1462 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1463 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1464 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1465 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1466 1467 /* 1468 * OFDM_PROT_CFG: OFDM Protection 1469 */ 1470 #define OFDM_PROT_CFG 0x1368 1471 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1472 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1473 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1474 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1475 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1476 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1477 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1478 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1479 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1480 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1481 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1482 1483 /* 1484 * MM20_PROT_CFG: MM20 Protection 1485 */ 1486 #define MM20_PROT_CFG 0x136c 1487 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1488 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1489 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1490 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1491 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1492 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1493 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1494 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1495 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1496 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1497 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1498 1499 /* 1500 * MM40_PROT_CFG: MM40 Protection 1501 */ 1502 #define MM40_PROT_CFG 0x1370 1503 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1504 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1505 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1506 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1507 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1508 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1509 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1510 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1511 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1512 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1513 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1514 1515 /* 1516 * GF20_PROT_CFG: GF20 Protection 1517 */ 1518 #define GF20_PROT_CFG 0x1374 1519 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1520 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1521 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1522 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1523 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1524 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1525 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1526 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1527 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1528 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1529 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1530 1531 /* 1532 * GF40_PROT_CFG: GF40 Protection 1533 */ 1534 #define GF40_PROT_CFG 0x1378 1535 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1536 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1537 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) 1538 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) 1539 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1540 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1541 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1542 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) 1543 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) 1544 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) 1545 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) 1546 1547 /* 1548 * EXP_CTS_TIME: 1549 */ 1550 #define EXP_CTS_TIME 0x137c 1551 1552 /* 1553 * EXP_ACK_TIME: 1554 */ 1555 #define EXP_ACK_TIME 0x1380 1556 1557 /* TX_PWR_CFG_5 */ 1558 #define TX_PWR_CFG_5 0x1384 1559 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f) 1560 #define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0) 1561 #define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00) 1562 #define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000) 1563 #define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000) 1564 #define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000) 1565 1566 /* TX_PWR_CFG_6 */ 1567 #define TX_PWR_CFG_6 0x1388 1568 #define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f) 1569 #define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0) 1570 #define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00) 1571 #define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000) 1572 #define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000) 1573 #define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000) 1574 1575 /* TX_PWR_CFG_0_EXT */ 1576 #define TX_PWR_CFG_0_EXT 0x1390 1577 #define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f) 1578 #define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00) 1579 #define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000) 1580 #define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000) 1581 1582 /* TX_PWR_CFG_1_EXT */ 1583 #define TX_PWR_CFG_1_EXT 0x1394 1584 #define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f) 1585 #define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00) 1586 #define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000) 1587 #define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000) 1588 1589 /* TX_PWR_CFG_2_EXT */ 1590 #define TX_PWR_CFG_2_EXT 0x1398 1591 #define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f) 1592 #define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00) 1593 #define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000) 1594 #define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000) 1595 1596 /* TX_PWR_CFG_3_EXT */ 1597 #define TX_PWR_CFG_3_EXT 0x139c 1598 #define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f) 1599 #define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00) 1600 #define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000) 1601 #define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000) 1602 1603 /* TX_PWR_CFG_4_EXT */ 1604 #define TX_PWR_CFG_4_EXT 0x13a0 1605 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f) 1606 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00) 1607 1608 /* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2] 1609 * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB 1610 */ 1611 #define TX0_RF_GAIN_CORRECT 0x13a0 1612 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f) 1613 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00) 1614 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000) 1615 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000) 1616 1617 #define TX1_RF_GAIN_CORRECT 0x13a4 1618 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f) 1619 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00) 1620 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000) 1621 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000) 1622 1623 /* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level 1624 * Format: 7-bit, signed value 1625 * Unit: 0.5 dB, Range: -20 dB to -5 dB 1626 */ 1627 #define TX0_RF_GAIN_ATTEN 0x13a8 1628 #define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f) 1629 #define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00) 1630 #define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000) 1631 #define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000) 1632 #define TX1_RF_GAIN_ATTEN 0x13ac 1633 #define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f) 1634 #define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00) 1635 #define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000) 1636 #define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000) 1637 1638 /* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0 1639 * TX_ALC_LIMIT_n: TXn upper limit 1640 * TX_ALC_CH_INIT_n: TXn channel initial transmission gain 1641 * Unit: 0.5 dB, Range: 0 to 23.5 dB 1642 */ 1643 #define TX_ALC_CFG_0 0x13b0 1644 #define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f) 1645 #define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00) 1646 #define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000) 1647 #define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000) 1648 1649 /* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1 1650 * TX_TEMP_COMP: TX Power Temperature Compensation 1651 * Unit: 0.5 dB, Range: -10 dB to 10 dB 1652 * TXn_GAIN_FINE: TXn Gain Fine Adjustment 1653 * Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB 1654 * RF_TOS_DLY: Sets the RF_TOS_EN assertion delay after 1655 * deassertion of PA_PE. 1656 * Unit: 0.25 usec 1657 * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector 1658 * RF_TOS_TIMEOUT: time-out value for RF_TOS_ENABLE 1659 * deassertion if RF_TOS_DONE is missing. 1660 * Unit: 0.25 usec 1661 * RF_TOS_ENABLE: TX offset calibration enable 1662 * ROS_BUSY_EN: RX offset calibration busy enable 1663 */ 1664 #define TX_ALC_CFG_1 0x13b4 1665 #define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f) 1666 #define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00) 1667 #define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000) 1668 #define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000) 1669 #define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000) 1670 #define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000) 1671 #define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000) 1672 #define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000) 1673 #define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000) 1674 1675 /* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level 1676 * Format: 5-bit signed values 1677 * Unit: 0.5 dB, Range: -8 dB to 7 dB 1678 */ 1679 #define TX0_BB_GAIN_ATTEN 0x13c0 1680 #define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f) 1681 #define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00) 1682 #define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000) 1683 #define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000) 1684 #define TX1_BB_GAIN_ATTEN 0x13c4 1685 #define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f) 1686 #define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00) 1687 #define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000) 1688 #define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000) 1689 1690 /* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */ 1691 #define TX_ALC_VGA3 0x13c8 1692 #define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f) 1693 #define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00) 1694 #define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000) 1695 #define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000) 1696 1697 /* TX_PWR_CFG_7 */ 1698 #define TX_PWR_CFG_7 0x13d4 1699 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f) 1700 #define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0) 1701 #define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00) 1702 #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000) 1703 #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000) 1704 #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000) 1705 /* bits for new 2T devices */ 1706 #define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff) 1707 #define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000) 1708 1709 1710 /* TX_PWR_CFG_8 */ 1711 #define TX_PWR_CFG_8 0x13d8 1712 #define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f) 1713 #define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0) 1714 #define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00) 1715 #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000) 1716 #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000) 1717 #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000) 1718 /* bits for new 2T devices */ 1719 #define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff) 1720 1721 1722 /* TX_PWR_CFG_9 */ 1723 #define TX_PWR_CFG_9 0x13dc 1724 #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f) 1725 #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0) 1726 #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00) 1727 /* bits for new 2T devices */ 1728 #define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff) 1729 1730 /* 1731 * TX_TXBF_CFG: 1732 */ 1733 #define TX_TXBF_CFG_0 0x138c 1734 #define TX_TXBF_CFG_1 0x13a4 1735 #define TX_TXBF_CFG_2 0x13a8 1736 #define TX_TXBF_CFG_3 0x13ac 1737 1738 /* 1739 * TX_FBK_CFG_3S: 1740 */ 1741 #define TX_FBK_CFG_3S_0 0x13c4 1742 #define TX_FBK_CFG_3S_1 0x13c8 1743 1744 /* 1745 * RX_FILTER_CFG: RX configuration register. 1746 */ 1747 #define RX_FILTER_CFG 0x1400 1748 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) 1749 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) 1750 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) 1751 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) 1752 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) 1753 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) 1754 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) 1755 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) 1756 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) 1757 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) 1758 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) 1759 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) 1760 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) 1761 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) 1762 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) 1763 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) 1764 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) 1765 1766 /* 1767 * AUTO_RSP_CFG: 1768 * AUTORESPONDER: 0: disable, 1: enable 1769 * BAC_ACK_POLICY: 0:long, 1:short preamble 1770 * CTS_40_MMODE: Response CTS 40MHz duplicate mode 1771 * CTS_40_MREF: Response CTS 40MHz duplicate mode 1772 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble 1773 * DUAL_CTS_EN: Power bit value in control frame 1774 * ACK_CTS_PSM_BIT:Power bit value in control frame 1775 */ 1776 #define AUTO_RSP_CFG 0x1404 1777 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) 1778 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) 1779 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) 1780 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) 1781 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) 1782 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) 1783 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) 1784 1785 /* 1786 * LEGACY_BASIC_RATE: 1787 */ 1788 #define LEGACY_BASIC_RATE 0x1408 1789 1790 /* 1791 * HT_BASIC_RATE: 1792 */ 1793 #define HT_BASIC_RATE 0x140c 1794 1795 /* 1796 * HT_CTRL_CFG: 1797 */ 1798 #define HT_CTRL_CFG 0x1410 1799 1800 /* 1801 * SIFS_COST_CFG: 1802 */ 1803 #define SIFS_COST_CFG 0x1414 1804 1805 /* 1806 * RX_PARSER_CFG: 1807 * Set NAV for all received frames 1808 */ 1809 #define RX_PARSER_CFG 0x1418 1810 1811 /* 1812 * TX_SEC_CNT0: 1813 */ 1814 #define TX_SEC_CNT0 0x1500 1815 1816 /* 1817 * RX_SEC_CNT0: 1818 */ 1819 #define RX_SEC_CNT0 0x1504 1820 1821 /* 1822 * CCMP_FC_MUTE: 1823 */ 1824 #define CCMP_FC_MUTE 0x1508 1825 1826 /* 1827 * TXOP_HLDR_ADDR0: 1828 */ 1829 #define TXOP_HLDR_ADDR0 0x1600 1830 1831 /* 1832 * TXOP_HLDR_ADDR1: 1833 */ 1834 #define TXOP_HLDR_ADDR1 0x1604 1835 1836 /* 1837 * TXOP_HLDR_ET: 1838 */ 1839 #define TXOP_HLDR_ET 0x1608 1840 1841 /* 1842 * QOS_CFPOLL_RA_DW0: 1843 */ 1844 #define QOS_CFPOLL_RA_DW0 0x160c 1845 1846 /* 1847 * QOS_CFPOLL_RA_DW1: 1848 */ 1849 #define QOS_CFPOLL_RA_DW1 0x1610 1850 1851 /* 1852 * QOS_CFPOLL_QC: 1853 */ 1854 #define QOS_CFPOLL_QC 0x1614 1855 1856 /* 1857 * RX_STA_CNT0: RX PLCP error count & RX CRC error count 1858 */ 1859 #define RX_STA_CNT0 0x1700 1860 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) 1861 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) 1862 1863 /* 1864 * RX_STA_CNT1: RX False CCA count & RX LONG frame count 1865 */ 1866 #define RX_STA_CNT1 0x1704 1867 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) 1868 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) 1869 1870 /* 1871 * RX_STA_CNT2: 1872 */ 1873 #define RX_STA_CNT2 0x1708 1874 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) 1875 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) 1876 1877 /* 1878 * TX_STA_CNT0: TX Beacon count 1879 */ 1880 #define TX_STA_CNT0 0x170c 1881 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) 1882 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) 1883 1884 /* 1885 * TX_STA_CNT1: TX tx count 1886 */ 1887 #define TX_STA_CNT1 0x1710 1888 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) 1889 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) 1890 1891 /* 1892 * TX_STA_CNT2: TX tx count 1893 */ 1894 #define TX_STA_CNT2 0x1714 1895 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) 1896 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) 1897 1898 /* 1899 * TX_STA_FIFO: TX Result for specific PID status fifo register. 1900 * 1901 * This register is implemented as FIFO with 16 entries in the HW. Each 1902 * register read fetches the next tx result. If the FIFO is full because 1903 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS) 1904 * triggered, the hw seems to simply drop further tx results. 1905 * 1906 * VALID: 1: this tx result is valid 1907 * 0: no valid tx result -> driver should stop reading 1908 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used 1909 * to match a frame with its tx result (even though the PID is 1910 * only 4 bits wide). 1911 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3) 1912 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3) 1913 * This identification number is calculated by ((idx % 3) + 1). 1914 * TX_SUCCESS: Indicates tx success (1) or failure (0) 1915 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0) 1916 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0) 1917 * WCID: The wireless client ID. 1918 * MCS: The tx rate used during the last transmission of this frame, be it 1919 * successful or not. 1920 * PHYMODE: The phymode used for the transmission. 1921 */ 1922 #define TX_STA_FIFO 0x1718 1923 #define TX_STA_FIFO_VALID FIELD32(0x00000001) 1924 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) 1925 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006) 1926 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018) 1927 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) 1928 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) 1929 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) 1930 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) 1931 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) 1932 #define TX_STA_FIFO_MCS FIELD32(0x007f0000) 1933 #define TX_STA_FIFO_BW FIELD32(0x00800000) 1934 #define TX_STA_FIFO_SGI FIELD32(0x01000000) 1935 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) 1936 1937 /* 1938 * TX_AGG_CNT: Debug counter 1939 */ 1940 #define TX_AGG_CNT 0x171c 1941 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) 1942 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) 1943 1944 /* 1945 * TX_AGG_CNT0: 1946 */ 1947 #define TX_AGG_CNT0 0x1720 1948 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) 1949 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) 1950 1951 /* 1952 * TX_AGG_CNT1: 1953 */ 1954 #define TX_AGG_CNT1 0x1724 1955 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) 1956 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) 1957 1958 /* 1959 * TX_AGG_CNT2: 1960 */ 1961 #define TX_AGG_CNT2 0x1728 1962 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) 1963 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) 1964 1965 /* 1966 * TX_AGG_CNT3: 1967 */ 1968 #define TX_AGG_CNT3 0x172c 1969 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) 1970 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) 1971 1972 /* 1973 * TX_AGG_CNT4: 1974 */ 1975 #define TX_AGG_CNT4 0x1730 1976 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) 1977 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) 1978 1979 /* 1980 * TX_AGG_CNT5: 1981 */ 1982 #define TX_AGG_CNT5 0x1734 1983 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) 1984 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) 1985 1986 /* 1987 * TX_AGG_CNT6: 1988 */ 1989 #define TX_AGG_CNT6 0x1738 1990 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) 1991 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) 1992 1993 /* 1994 * TX_AGG_CNT7: 1995 */ 1996 #define TX_AGG_CNT7 0x173c 1997 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) 1998 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) 1999 2000 /* 2001 * MPDU_DENSITY_CNT: 2002 * TX_ZERO_DEL: TX zero length delimiter count 2003 * RX_ZERO_DEL: RX zero length delimiter count 2004 */ 2005 #define MPDU_DENSITY_CNT 0x1740 2006 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) 2007 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) 2008 2009 /* 2010 * Security key table memory. 2011 * 2012 * The pairwise key table shares some memory with the beacon frame 2013 * buffers 6 and 7. That basically means that when beacon 6 & 7 2014 * are used we should only use the reduced pairwise key table which 2015 * has a maximum of 222 entries. 2016 * 2017 * --------------------------------------------- 2018 * |0x4000 | Pairwise Key | Reduced Pairwise | 2019 * | | Table | Key Table | 2020 * | | Size: 256 * 32 | Size: 222 * 32 | 2021 * |0x5BC0 | |------------------- 2022 * | | | Beacon 6 | 2023 * |0x5DC0 | |------------------- 2024 * | | | Beacon 7 | 2025 * |0x5FC0 | |------------------- 2026 * |0x5FFF | | 2027 * -------------------------- 2028 * 2029 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry 2030 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry 2031 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry 2032 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry 2033 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry 2034 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry 2035 */ 2036 #define MAC_WCID_BASE 0x1800 2037 #define PAIRWISE_KEY_TABLE_BASE 0x4000 2038 #define MAC_IVEIV_TABLE_BASE 0x6000 2039 #define MAC_WCID_ATTRIBUTE_BASE 0x6800 2040 #define SHARED_KEY_TABLE_BASE 0x6c00 2041 #define SHARED_KEY_MODE_BASE 0x7000 2042 2043 #define MAC_WCID_ENTRY(__idx) \ 2044 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry))) 2045 #define PAIRWISE_KEY_ENTRY(__idx) \ 2046 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) 2047 #define MAC_IVEIV_ENTRY(__idx) \ 2048 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry))) 2049 #define MAC_WCID_ATTR_ENTRY(__idx) \ 2050 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32))) 2051 #define SHARED_KEY_ENTRY(__idx) \ 2052 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) 2053 #define SHARED_KEY_MODE_ENTRY(__idx) \ 2054 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32))) 2055 2056 struct mac_wcid_entry { 2057 u8 mac[6]; 2058 u8 reserved[2]; 2059 } __packed; 2060 2061 struct hw_key_entry { 2062 u8 key[16]; 2063 u8 tx_mic[8]; 2064 u8 rx_mic[8]; 2065 } __packed; 2066 2067 struct mac_iveiv_entry { 2068 u8 iv[8]; 2069 } __packed; 2070 2071 /* 2072 * MAC_WCID_ATTRIBUTE: 2073 */ 2074 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) 2075 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) 2076 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) 2077 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) 2078 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) 2079 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) 2080 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) 2081 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) 2082 2083 /* 2084 * SHARED_KEY_MODE: 2085 */ 2086 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) 2087 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) 2088 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) 2089 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) 2090 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) 2091 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) 2092 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) 2093 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) 2094 2095 /* 2096 * HOST-MCU communication 2097 */ 2098 2099 /* 2100 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. 2101 * CMD_TOKEN: Command id, 0xff disable status reporting. 2102 */ 2103 #define H2M_MAILBOX_CSR 0x7010 2104 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) 2105 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) 2106 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) 2107 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) 2108 2109 /* 2110 * H2M_MAILBOX_CID: 2111 * Free slots contain 0xff. MCU will store command's token to lowest free slot. 2112 * If all slots are occupied status will be dropped. 2113 */ 2114 #define H2M_MAILBOX_CID 0x7014 2115 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) 2116 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) 2117 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) 2118 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) 2119 2120 /* 2121 * H2M_MAILBOX_STATUS: 2122 * Command status will be saved to same slot as command id. 2123 */ 2124 #define H2M_MAILBOX_STATUS 0x701c 2125 2126 /* 2127 * H2M_INT_SRC: 2128 */ 2129 #define H2M_INT_SRC 0x7024 2130 2131 /* 2132 * H2M_BBP_AGENT: 2133 */ 2134 #define H2M_BBP_AGENT 0x7028 2135 2136 /* 2137 * MCU_LEDCS: LED control for MCU Mailbox. 2138 */ 2139 #define MCU_LEDCS_LED_MODE FIELD8(0x1f) 2140 #define MCU_LEDCS_POLARITY FIELD8(0x01) 2141 2142 /* 2143 * HW_CS_CTS_BASE: 2144 * Carrier-sense CTS frame base address. 2145 * It's where mac stores carrier-sense frame for carrier-sense function. 2146 */ 2147 #define HW_CS_CTS_BASE 0x7700 2148 2149 /* 2150 * HW_DFS_CTS_BASE: 2151 * DFS CTS frame base address. It's where mac stores CTS frame for DFS. 2152 */ 2153 #define HW_DFS_CTS_BASE 0x7780 2154 2155 /* 2156 * TXRX control registers - base address 0x3000 2157 */ 2158 2159 /* 2160 * TXRX_CSR1: 2161 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. 2162 */ 2163 #define TXRX_CSR1 0x77d0 2164 2165 /* 2166 * HW_DEBUG_SETTING_BASE: 2167 * since NULL frame won't be that long (256 byte) 2168 * We steal 16 tail bytes to save debugging settings 2169 */ 2170 #define HW_DEBUG_SETTING_BASE 0x77f0 2171 #define HW_DEBUG_SETTING_BASE2 0x7770 2172 2173 /* 2174 * HW_BEACON_BASE 2175 * In order to support maximum 8 MBSS and its maximum length 2176 * is 512 bytes for each beacon 2177 * Three section discontinue memory segments will be used. 2178 * 1. The original region for BCN 0~3 2179 * 2. Extract memory from FCE table for BCN 4~5 2180 * 3. Extract memory from Pair-wise key table for BCN 6~7 2181 * It occupied those memory of wcid 238~253 for BCN 6 2182 * and wcid 222~237 for BCN 7 (see Security key table memory 2183 * for more info). 2184 * 2185 * IMPORTANT NOTE: Not sure why legacy driver does this, 2186 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. 2187 */ 2188 #define HW_BEACON_BASE0 0x7800 2189 #define HW_BEACON_BASE1 0x7a00 2190 #define HW_BEACON_BASE2 0x7c00 2191 #define HW_BEACON_BASE3 0x7e00 2192 #define HW_BEACON_BASE4 0x7200 2193 #define HW_BEACON_BASE5 0x7400 2194 #define HW_BEACON_BASE6 0x5dc0 2195 #define HW_BEACON_BASE7 0x5bc0 2196 2197 #define HW_BEACON_BASE(__index) \ 2198 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \ 2199 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \ 2200 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200)))) 2201 2202 #define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64) 2203 2204 /* 2205 * BBP registers. 2206 * The wordsize of the BBP is 8 bits. 2207 */ 2208 2209 /* 2210 * BBP 1: TX Antenna & Power Control 2211 * POWER_CTRL: 2212 * 0 - normal, 2213 * 1 - drop tx power by 6dBm, 2214 * 2 - drop tx power by 12dBm, 2215 * 3 - increase tx power by 6dBm 2216 */ 2217 #define BBP1_TX_POWER_CTRL FIELD8(0x03) 2218 #define BBP1_TX_ANTENNA FIELD8(0x18) 2219 2220 /* 2221 * BBP 3: RX Antenna 2222 */ 2223 #define BBP3_RX_ADC FIELD8(0x03) 2224 #define BBP3_RX_ANTENNA FIELD8(0x18) 2225 #define BBP3_HT40_MINUS FIELD8(0x20) 2226 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40) 2227 #define BBP3_ADC_INIT_MODE FIELD8(0x80) 2228 2229 /* 2230 * BBP 4: Bandwidth 2231 */ 2232 #define BBP4_TX_BF FIELD8(0x01) 2233 #define BBP4_BANDWIDTH FIELD8(0x18) 2234 #define BBP4_MAC_IF_CTRL FIELD8(0x40) 2235 2236 /* BBP27 */ 2237 #define BBP27_RX_CHAIN_SEL FIELD8(0x60) 2238 2239 /* 2240 * BBP 47: Bandwidth 2241 */ 2242 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03) 2243 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04) 2244 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18) 2245 #define BBP47_TSSI_ADC6 FIELD8(0x80) 2246 2247 /* 2248 * BBP 49 2249 */ 2250 #define BBP49_UPDATE_FLAG FIELD8(0x01) 2251 2252 /* 2253 * BBP 105: 2254 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth) 2255 * - bit1: FEQ (Feed Forward Compensation) for independend streams 2256 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single 2257 * stream) 2258 * - bit4: channel estimation updates based on remodulation of 2259 * L-SIG and HT-SIG symbols 2260 */ 2261 #define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01) 2262 #define BBP105_FEQ FIELD8(0x02) 2263 #define BBP105_MLD FIELD8(0x04) 2264 #define BBP105_SIG_REMODULATION FIELD8(0x08) 2265 2266 /* 2267 * BBP 109 2268 */ 2269 #define BBP109_TX0_POWER FIELD8(0x0f) 2270 #define BBP109_TX1_POWER FIELD8(0xf0) 2271 2272 /* BBP 110 */ 2273 #define BBP110_TX2_POWER FIELD8(0x0f) 2274 2275 2276 /* 2277 * BBP 138: Unknown 2278 */ 2279 #define BBP138_RX_ADC1 FIELD8(0x02) 2280 #define BBP138_RX_ADC2 FIELD8(0x04) 2281 #define BBP138_TX_DAC1 FIELD8(0x20) 2282 #define BBP138_TX_DAC2 FIELD8(0x40) 2283 2284 /* 2285 * BBP 152: Rx Ant 2286 */ 2287 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80) 2288 2289 /* 2290 * BBP 254: unknown 2291 */ 2292 #define BBP254_BIT7 FIELD8(0x80) 2293 2294 /* 2295 * RFCSR registers 2296 * The wordsize of the RFCSR is 8 bits. 2297 */ 2298 2299 /* 2300 * RFCSR 1: 2301 */ 2302 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 2303 #define RFCSR1_PLL_PD FIELD8(0x02) 2304 #define RFCSR1_RX0_PD FIELD8(0x04) 2305 #define RFCSR1_TX0_PD FIELD8(0x08) 2306 #define RFCSR1_RX1_PD FIELD8(0x10) 2307 #define RFCSR1_TX1_PD FIELD8(0x20) 2308 #define RFCSR1_RX2_PD FIELD8(0x40) 2309 #define RFCSR1_TX2_PD FIELD8(0x80) 2310 #define RFCSR1_TX2_EN_MT7620 FIELD8(0x02) 2311 2312 /* 2313 * RFCSR 2: 2314 */ 2315 #define RFCSR2_RESCAL_BP FIELD8(0x40) 2316 #define RFCSR2_RESCAL_EN FIELD8(0x80) 2317 #define RFCSR2_RX2_EN_MT7620 FIELD8(0x02) 2318 #define RFCSR2_TX2_EN_MT7620 FIELD8(0x20) 2319 2320 /* 2321 * RFCSR 3: 2322 */ 2323 #define RFCSR3_K FIELD8(0x0f) 2324 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */ 2325 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70) 2326 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80) 2327 /* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */ 2328 #define RFCSR3_VCOCAL_EN FIELD8(0x80) 2329 /* Bits for RF3050 */ 2330 #define RFCSR3_BIT1 FIELD8(0x02) 2331 #define RFCSR3_BIT2 FIELD8(0x04) 2332 #define RFCSR3_BIT3 FIELD8(0x08) 2333 #define RFCSR3_BIT4 FIELD8(0x10) 2334 #define RFCSR3_BIT5 FIELD8(0x20) 2335 2336 /* 2337 * RFCSR 4: 2338 * VCOCAL_EN used by MT7620 2339 */ 2340 #define RFCSR4_VCOCAL_EN FIELD8(0x80) 2341 2342 /* 2343 * FRCSR 5: 2344 */ 2345 #define RFCSR5_R1 FIELD8(0x0c) 2346 2347 /* 2348 * RFCSR 6: 2349 */ 2350 #define RFCSR6_R1 FIELD8(0x03) 2351 #define RFCSR6_R2 FIELD8(0x40) 2352 #define RFCSR6_TXDIV FIELD8(0x0c) 2353 /* bits for RF3053 */ 2354 #define RFCSR6_VCO_IC FIELD8(0xc0) 2355 2356 /* 2357 * RFCSR 7: 2358 */ 2359 #define RFCSR7_RF_TUNING FIELD8(0x01) 2360 #define RFCSR7_BIT1 FIELD8(0x02) 2361 #define RFCSR7_BIT2 FIELD8(0x04) 2362 #define RFCSR7_BIT3 FIELD8(0x08) 2363 #define RFCSR7_BIT4 FIELD8(0x10) 2364 #define RFCSR7_BIT5 FIELD8(0x20) 2365 #define RFCSR7_BITS67 FIELD8(0xc0) 2366 2367 /* 2368 * RFCSR 9: 2369 */ 2370 #define RFCSR9_K FIELD8(0x0f) 2371 #define RFCSR9_N FIELD8(0x10) 2372 #define RFCSR9_UNKNOWN FIELD8(0x60) 2373 #define RFCSR9_MOD FIELD8(0x80) 2374 2375 /* 2376 * RFCSR 11: 2377 */ 2378 #define RFCSR11_R FIELD8(0x03) 2379 #define RFCSR11_PLL_MOD FIELD8(0x0c) 2380 #define RFCSR11_MOD FIELD8(0xc0) 2381 /* bits for RF3053 */ 2382 /* TODO: verify RFCSR11_MOD usage on other chips */ 2383 #define RFCSR11_PLL_IDOH FIELD8(0x40) 2384 2385 2386 /* 2387 * RFCSR 12: 2388 */ 2389 #define RFCSR12_TX_POWER FIELD8(0x1f) 2390 #define RFCSR12_DR0 FIELD8(0xe0) 2391 2392 /* 2393 * RFCSR 13: 2394 */ 2395 #define RFCSR13_TX_POWER FIELD8(0x1f) 2396 #define RFCSR13_DR0 FIELD8(0xe0) 2397 #define RFCSR13_RDIV_MT7620 FIELD8(0x03) 2398 2399 /* 2400 * RFCSR 15: 2401 */ 2402 #define RFCSR15_TX_LO2_EN FIELD8(0x08) 2403 2404 /* 2405 * RFCSR 16: 2406 */ 2407 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07) 2408 #define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F) 2409 #define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0) 2410 2411 /* 2412 * RFCSR 17: 2413 */ 2414 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 2415 #define RFCSR17_TX_LO1_EN FIELD8(0x08) 2416 #define RFCSR17_R FIELD8(0x20) 2417 #define RFCSR17_CODE FIELD8(0x7f) 2418 2419 /* RFCSR 18 */ 2420 #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40) 2421 2422 /* RFCSR 19 */ 2423 #define RFCSR19_K FIELD8(0x03) 2424 2425 /* 2426 * RFCSR 20: 2427 */ 2428 #define RFCSR20_RX_LO1_EN FIELD8(0x08) 2429 2430 /* 2431 * RFCSR 21: 2432 */ 2433 #define RFCSR21_RX_LO2_EN FIELD8(0x08) 2434 #define RFCSR21_BIT1 FIELD8(0x01) 2435 #define RFCSR21_BIT8 FIELD8(0x80) 2436 2437 /* 2438 * RFCSR 22: 2439 */ 2440 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) 2441 #define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07) 2442 2443 /* 2444 * RFCSR 23: 2445 */ 2446 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) 2447 2448 /* 2449 * RFCSR 24: 2450 */ 2451 #define RFCSR24_TX_AGC_FC FIELD8(0x1f) 2452 #define RFCSR24_TX_H20M FIELD8(0x20) 2453 #define RFCSR24_TX_CALIB FIELD8(0x7f) 2454 2455 /* 2456 * RFCSR 27: 2457 */ 2458 #define RFCSR27_R1 FIELD8(0x03) 2459 #define RFCSR27_R2 FIELD8(0x04) 2460 #define RFCSR27_R3 FIELD8(0x30) 2461 #define RFCSR27_R4 FIELD8(0x40) 2462 2463 /* 2464 * RFCSR 28: 2465 */ 2466 #define RFCSR28_CH11_HT40 FIELD8(0x04) 2467 2468 /* 2469 * RFCSR 29: 2470 */ 2471 #define RFCSR29_ADC6_TEST FIELD8(0x01) 2472 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02) 2473 #define RFCSR29_RSSI_RESET FIELD8(0x04) 2474 #define RFCSR29_RSSI_ON FIELD8(0x08) 2475 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30) 2476 #define RFCSR29_RSSI_GAIN FIELD8(0xc0) 2477 2478 /* 2479 * RFCSR 30: 2480 */ 2481 #define RFCSR30_TX_H20M FIELD8(0x02) 2482 #define RFCSR30_RX_H20M FIELD8(0x04) 2483 #define RFCSR30_RX_VCM FIELD8(0x18) 2484 #define RFCSR30_RF_CALIBRATION FIELD8(0x80) 2485 #define RF3322_RFCSR30_TX_H20M FIELD8(0x01) 2486 #define RF3322_RFCSR30_RX_H20M FIELD8(0x02) 2487 2488 /* 2489 * RFCSR 31: 2490 */ 2491 #define RFCSR31_RX_AGC_FC FIELD8(0x1f) 2492 #define RFCSR31_RX_H20M FIELD8(0x20) 2493 #define RFCSR31_RX_CALIB FIELD8(0x7f) 2494 2495 /* RFCSR 32 bits for RF3053 */ 2496 #define RFCSR32_TX_AGC_FC FIELD8(0xf8) 2497 2498 /* RFCSR 36 bits for RF3053 */ 2499 #define RFCSR36_RF_BS FIELD8(0x80) 2500 2501 /* 2502 * RFCSR 34: 2503 */ 2504 #define RFCSR34_TX0_EXT_PA FIELD8(0x04) 2505 #define RFCSR34_TX1_EXT_PA FIELD8(0x08) 2506 2507 /* 2508 * RFCSR 38: 2509 */ 2510 #define RFCSR38_RX_LO1_EN FIELD8(0x20) 2511 2512 /* 2513 * RFCSR 39: 2514 */ 2515 #define RFCSR39_RX_DIV FIELD8(0x40) 2516 #define RFCSR39_RX_LO2_EN FIELD8(0x80) 2517 2518 /* 2519 * RFCSR 41: 2520 */ 2521 #define RFCSR41_BIT1 FIELD8(0x01) 2522 #define RFCSR41_BIT4 FIELD8(0x08) 2523 2524 /* 2525 * RFCSR 42: 2526 */ 2527 #define RFCSR42_BIT1 FIELD8(0x01) 2528 #define RFCSR42_BIT4 FIELD8(0x08) 2529 #define RFCSR42_TX2_EN_MT7620 FIELD8(0x40) 2530 2531 /* 2532 * RFCSR 49: 2533 */ 2534 #define RFCSR49_TX FIELD8(0x3f) 2535 #define RFCSR49_EP FIELD8(0xc0) 2536 /* bits for RT3593 */ 2537 #define RFCSR49_TX_LO1_IC FIELD8(0x1c) 2538 #define RFCSR49_TX_DIV FIELD8(0x20) 2539 2540 /* 2541 * RFCSR 50: 2542 */ 2543 #define RFCSR50_TX FIELD8(0x3f) 2544 #define RFCSR50_TX0_EXT_PA FIELD8(0x02) 2545 #define RFCSR50_TX1_EXT_PA FIELD8(0x10) 2546 #define RFCSR50_EP FIELD8(0xc0) 2547 /* bits for RT3593 */ 2548 #define RFCSR50_TX_LO1_EN FIELD8(0x20) 2549 #define RFCSR50_TX_LO2_EN FIELD8(0x10) 2550 2551 /* RFCSR 51 */ 2552 /* bits for RT3593 */ 2553 #define RFCSR51_BITS01 FIELD8(0x03) 2554 #define RFCSR51_BITS24 FIELD8(0x1c) 2555 #define RFCSR51_BITS57 FIELD8(0xe0) 2556 2557 #define RFCSR53_TX_POWER FIELD8(0x3f) 2558 #define RFCSR53_UNKNOWN FIELD8(0xc0) 2559 2560 #define RFCSR54_TX_POWER FIELD8(0x3f) 2561 #define RFCSR54_UNKNOWN FIELD8(0xc0) 2562 2563 #define RFCSR55_TX_POWER FIELD8(0x3f) 2564 #define RFCSR55_UNKNOWN FIELD8(0xc0) 2565 2566 #define RFCSR57_DRV_CC FIELD8(0xfc) 2567 2568 2569 /* 2570 * RF registers 2571 */ 2572 2573 /* 2574 * RF 2 2575 */ 2576 #define RF2_ANTENNA_RX2 FIELD32(0x00000040) 2577 #define RF2_ANTENNA_TX1 FIELD32(0x00004000) 2578 #define RF2_ANTENNA_RX1 FIELD32(0x00020000) 2579 2580 /* 2581 * RF 3 2582 */ 2583 #define RF3_TXPOWER_G FIELD32(0x00003e00) 2584 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) 2585 #define RF3_TXPOWER_A FIELD32(0x00003c00) 2586 2587 /* 2588 * RF 4 2589 */ 2590 #define RF4_TXPOWER_G FIELD32(0x000007c0) 2591 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) 2592 #define RF4_TXPOWER_A FIELD32(0x00000780) 2593 #define RF4_FREQ_OFFSET FIELD32(0x001f8000) 2594 #define RF4_HT40 FIELD32(0x00200000) 2595 2596 /* 2597 * EEPROM content. 2598 * The wordsize of the EEPROM is 16 bits. 2599 */ 2600 2601 enum rt2800_eeprom_word { 2602 EEPROM_CHIP_ID = 0, 2603 EEPROM_VERSION, 2604 EEPROM_MAC_ADDR_0, 2605 EEPROM_MAC_ADDR_1, 2606 EEPROM_MAC_ADDR_2, 2607 EEPROM_NIC_CONF0, 2608 EEPROM_NIC_CONF1, 2609 EEPROM_FREQ, 2610 EEPROM_LED_AG_CONF, 2611 EEPROM_LED_ACT_CONF, 2612 EEPROM_LED_POLARITY, 2613 EEPROM_NIC_CONF2, 2614 EEPROM_LNA, 2615 EEPROM_RSSI_BG, 2616 EEPROM_RSSI_BG2, 2617 EEPROM_TXMIXER_GAIN_BG, 2618 EEPROM_RSSI_A, 2619 EEPROM_RSSI_A2, 2620 EEPROM_TXMIXER_GAIN_A, 2621 EEPROM_EIRP_MAX_TX_POWER, 2622 EEPROM_TXPOWER_DELTA, 2623 EEPROM_TXPOWER_BG1, 2624 EEPROM_TXPOWER_BG2, 2625 EEPROM_TSSI_BOUND_BG1, 2626 EEPROM_TSSI_BOUND_BG2, 2627 EEPROM_TSSI_BOUND_BG3, 2628 EEPROM_TSSI_BOUND_BG4, 2629 EEPROM_TSSI_BOUND_BG5, 2630 EEPROM_TXPOWER_A1, 2631 EEPROM_TXPOWER_A2, 2632 EEPROM_TXPOWER_INIT, 2633 EEPROM_TSSI_BOUND_A1, 2634 EEPROM_TSSI_BOUND_A2, 2635 EEPROM_TSSI_BOUND_A3, 2636 EEPROM_TSSI_BOUND_A4, 2637 EEPROM_TSSI_BOUND_A5, 2638 EEPROM_TXPOWER_BYRATE, 2639 EEPROM_BBP_START, 2640 2641 /* IDs for extended EEPROM format used by three-chain devices */ 2642 EEPROM_EXT_LNA2, 2643 EEPROM_EXT_TXPOWER_BG3, 2644 EEPROM_EXT_TXPOWER_A3, 2645 2646 /* New values must be added before this */ 2647 EEPROM_WORD_COUNT 2648 }; 2649 2650 /* 2651 * EEPROM Version 2652 */ 2653 #define EEPROM_VERSION_FAE FIELD16(0x00ff) 2654 #define EEPROM_VERSION_VERSION FIELD16(0xff00) 2655 2656 /* 2657 * HW MAC address. 2658 */ 2659 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 2660 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 2661 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 2662 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 2663 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 2664 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 2665 2666 /* 2667 * EEPROM NIC Configuration 0 2668 * RXPATH: 1: 1R, 2: 2R, 3: 3R 2669 * TXPATH: 1: 1T, 2: 2T, 3: 3T 2670 * RF_TYPE: RFIC type 2671 */ 2672 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f) 2673 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0) 2674 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00) 2675 2676 /* 2677 * EEPROM NIC Configuration 1 2678 * HW_RADIO: 0: disable, 1: enable 2679 * EXTERNAL_TX_ALC: 0: disable, 1: enable 2680 * EXTERNAL_LNA_2G: 0: disable, 1: enable 2681 * EXTERNAL_LNA_5G: 0: disable, 1: enable 2682 * CARDBUS_ACCEL: 0: enable, 1: disable 2683 * BW40M_SB_2G: 0: disable, 1: enable 2684 * BW40M_SB_5G: 0: disable, 1: enable 2685 * WPS_PBC: 0: disable, 1: enable 2686 * BW40M_2G: 0: enable, 1: disable 2687 * BW40M_5G: 0: enable, 1: disable 2688 * BROADBAND_EXT_LNA: 0: disable, 1: enable 2689 * ANT_DIVERSITY: 00: Disable, 01: Diversity, 2690 * 10: Main antenna, 11: Aux antenna 2691 * INTERNAL_TX_ALC: 0: disable, 1: enable 2692 * BT_COEXIST: 0: disable, 1: enable 2693 * DAC_TEST: 0: disable, 1: enable 2694 * EXTERNAL_TX0_PA: 0: disable, 1: enable (only on RT3352) 2695 * EXTERNAL_TX1_PA: 0: disable, 1: enable (only on RT3352) 2696 */ 2697 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001) 2698 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002) 2699 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004) 2700 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008) 2701 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010) 2702 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020) 2703 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040) 2704 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080) 2705 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100) 2706 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200) 2707 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400) 2708 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800) 2709 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000) 2710 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000) 2711 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000) 2712 #define EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352 FIELD16(0x4000) 2713 #define EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352 FIELD16(0x8000) 2714 2715 /* 2716 * EEPROM frequency 2717 */ 2718 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) 2719 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) 2720 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) 2721 2722 /* 2723 * EEPROM LED 2724 * POLARITY_RDY_G: Polarity RDY_G setting. 2725 * POLARITY_RDY_A: Polarity RDY_A setting. 2726 * POLARITY_ACT: Polarity ACT setting. 2727 * POLARITY_GPIO_0: Polarity GPIO0 setting. 2728 * POLARITY_GPIO_1: Polarity GPIO1 setting. 2729 * POLARITY_GPIO_2: Polarity GPIO2 setting. 2730 * POLARITY_GPIO_3: Polarity GPIO3 setting. 2731 * POLARITY_GPIO_4: Polarity GPIO4 setting. 2732 * LED_MODE: Led mode. 2733 */ 2734 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) 2735 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) 2736 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) 2737 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) 2738 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) 2739 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) 2740 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) 2741 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) 2742 #define EEPROM_LED_LED_MODE FIELD16(0x1f00) 2743 2744 /* 2745 * EEPROM NIC Configuration 2 2746 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream 2747 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream 2748 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved 2749 */ 2750 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f) 2751 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0) 2752 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600) 2753 2754 /* 2755 * EEPROM LNA 2756 */ 2757 #define EEPROM_LNA_BG FIELD16(0x00ff) 2758 #define EEPROM_LNA_A0 FIELD16(0xff00) 2759 2760 /* 2761 * EEPROM RSSI BG offset 2762 */ 2763 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) 2764 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) 2765 2766 /* 2767 * EEPROM RSSI BG2 offset 2768 */ 2769 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) 2770 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) 2771 2772 /* 2773 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). 2774 */ 2775 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) 2776 2777 /* 2778 * EEPROM RSSI A offset 2779 */ 2780 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) 2781 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) 2782 2783 /* 2784 * EEPROM RSSI A2 offset 2785 */ 2786 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) 2787 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) 2788 2789 /* 2790 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2). 2791 */ 2792 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007) 2793 2794 /* 2795 * EEPROM EIRP Maximum TX power values(unit: dbm) 2796 */ 2797 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff) 2798 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00) 2799 2800 /* 2801 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. 2802 * This is delta in 40MHZ. 2803 * VALUE: Tx Power dalta value, MAX=4(unit: dbm) 2804 * TYPE: 1: Plus the delta value, 0: minus the delta value 2805 * ENABLE: enable tx power compensation for 40BW 2806 */ 2807 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f) 2808 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040) 2809 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080) 2810 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00) 2811 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000) 2812 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000) 2813 2814 /* 2815 * EEPROM TXPOWER 802.11BG 2816 */ 2817 #define EEPROM_TXPOWER_BG_SIZE 7 2818 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) 2819 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) 2820 2821 /* 2822 * EEPROM temperature compensation boundaries 802.11BG 2823 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be 2824 * reduced by (agc_step * -4) 2825 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be 2826 * reduced by (agc_step * -3) 2827 */ 2828 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff) 2829 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00) 2830 2831 /* 2832 * EEPROM temperature compensation boundaries 802.11BG 2833 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be 2834 * reduced by (agc_step * -2) 2835 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be 2836 * reduced by (agc_step * -1) 2837 */ 2838 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff) 2839 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00) 2840 2841 /* 2842 * EEPROM temperature compensation boundaries 802.11BG 2843 * REF: Reference TSSI value, no tx power changes needed 2844 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be 2845 * increased by (agc_step * 1) 2846 */ 2847 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff) 2848 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00) 2849 2850 /* 2851 * EEPROM temperature compensation boundaries 802.11BG 2852 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be 2853 * increased by (agc_step * 2) 2854 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be 2855 * increased by (agc_step * 3) 2856 */ 2857 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff) 2858 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00) 2859 2860 /* 2861 * EEPROM temperature compensation boundaries 802.11BG 2862 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be 2863 * increased by (agc_step * 4) 2864 * AGC_STEP: Temperature compensation step. 2865 */ 2866 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff) 2867 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00) 2868 2869 /* 2870 * EEPROM TXPOWER 802.11A 2871 */ 2872 #define EEPROM_TXPOWER_A_SIZE 6 2873 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) 2874 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 2875 2876 /* EEPROM_TXPOWER_{A,G} fields for RT3593 */ 2877 #define EEPROM_TXPOWER_ALC FIELD8(0x1f) 2878 #define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0) 2879 2880 /* 2881 * EEPROM temperature compensation boundaries 802.11A 2882 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be 2883 * reduced by (agc_step * -4) 2884 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be 2885 * reduced by (agc_step * -3) 2886 */ 2887 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff) 2888 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00) 2889 2890 /* 2891 * EEPROM temperature compensation boundaries 802.11A 2892 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be 2893 * reduced by (agc_step * -2) 2894 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be 2895 * reduced by (agc_step * -1) 2896 */ 2897 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff) 2898 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00) 2899 2900 /* 2901 * EEPROM temperature compensation boundaries 802.11A 2902 * REF: Reference TSSI value, no tx power changes needed 2903 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be 2904 * increased by (agc_step * 1) 2905 */ 2906 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff) 2907 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00) 2908 2909 /* 2910 * EEPROM temperature compensation boundaries 802.11A 2911 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be 2912 * increased by (agc_step * 2) 2913 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be 2914 * increased by (agc_step * 3) 2915 */ 2916 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff) 2917 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00) 2918 2919 /* 2920 * EEPROM temperature compensation boundaries 802.11A 2921 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be 2922 * increased by (agc_step * 4) 2923 * AGC_STEP: Temperature compensation step. 2924 */ 2925 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff) 2926 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00) 2927 2928 /* 2929 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode 2930 */ 2931 #define EEPROM_TXPOWER_BYRATE_SIZE 9 2932 2933 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) 2934 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) 2935 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) 2936 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) 2937 2938 /* 2939 * EEPROM BBP. 2940 */ 2941 #define EEPROM_BBP_SIZE 16 2942 #define EEPROM_BBP_VALUE FIELD16(0x00ff) 2943 #define EEPROM_BBP_REG_ID FIELD16(0xff00) 2944 2945 /* EEPROM_EXT_LNA2 */ 2946 #define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff) 2947 #define EEPROM_EXT_LNA2_A2 FIELD16(0xff00) 2948 2949 /* 2950 * EEPROM IQ Calibration, unlike other entries those are byte addresses. 2951 */ 2952 2953 #define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130 2954 #define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131 2955 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132 2956 #define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133 2957 #define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134 2958 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135 2959 #define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136 2960 #define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137 2961 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138 2962 #define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139 2963 #define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A 2964 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B 2965 #define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C 2966 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D 2967 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144 2968 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145 2969 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146 2970 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147 2971 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148 2972 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149 2973 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A 2974 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B 2975 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C 2976 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D 2977 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E 2978 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F 2979 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150 2980 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151 2981 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152 2982 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153 2983 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154 2984 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155 2985 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156 2986 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157 2987 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158 2988 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159 2989 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A 2990 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B 2991 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C 2992 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D 2993 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E 2994 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F 2995 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160 2996 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161 2997 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162 2998 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163 2999 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164 3000 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165 3001 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166 3002 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167 3003 3004 /* 3005 * MCU mailbox commands. 3006 * MCU_SLEEP - go to power-save mode. 3007 * arg1: 1: save as much power as possible, 0: save less power. 3008 * status: 1: success, 2: already asleep, 3009 * 3: maybe MAC is busy so can't finish this task. 3010 * MCU_RADIO_OFF 3011 * arg0: 0: do power-saving, NOT turn off radio. 3012 */ 3013 #define MCU_SLEEP 0x30 3014 #define MCU_WAKEUP 0x31 3015 #define MCU_RADIO_OFF 0x35 3016 #define MCU_CURRENT 0x36 3017 #define MCU_LED 0x50 3018 #define MCU_LED_STRENGTH 0x51 3019 #define MCU_LED_AG_CONF 0x52 3020 #define MCU_LED_ACT_CONF 0x53 3021 #define MCU_LED_LED_POLARITY 0x54 3022 #define MCU_RADAR 0x60 3023 #define MCU_BOOT_SIGNAL 0x72 3024 #define MCU_ANT_SELECT 0X73 3025 #define MCU_FREQ_OFFSET 0x74 3026 #define MCU_BBP_SIGNAL 0x80 3027 #define MCU_POWER_SAVE 0x83 3028 #define MCU_BAND_SELECT 0x91 3029 3030 /* 3031 * MCU mailbox tokens 3032 */ 3033 #define TOKEN_SLEEP 1 3034 #define TOKEN_RADIO_OFF 2 3035 #define TOKEN_WAKEUP 3 3036 3037 3038 /* 3039 * DMA descriptor defines. 3040 */ 3041 3042 #define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32)) 3043 #define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32)) 3044 3045 #define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32)) 3046 #define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32)) 3047 #define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32)) 3048 3049 /* 3050 * TX WI structure 3051 */ 3052 3053 /* 3054 * Word0 3055 * FRAG: 1 To inform TKIP engine this is a fragment. 3056 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode 3057 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs 3058 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will 3059 * duplicate the frame to both channels). 3060 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED 3061 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will 3062 * aggregate consecutive frames with the same RA and QoS TID. If 3063 * a frame A with the same RA and QoS TID but AMPDU=0 is queued 3064 * directly after a frame B with AMPDU=1, frame A might still 3065 * get aggregated into the AMPDU started by frame B. So, setting 3066 * AMPDU to 0 does _not_ necessarily mean the frame is sent as 3067 * MPDU, it can still end up in an AMPDU if the previous frame 3068 * was tagged as AMPDU. 3069 */ 3070 #define TXWI_W0_FRAG FIELD32(0x00000001) 3071 #define TXWI_W0_MIMO_PS FIELD32(0x00000002) 3072 #define TXWI_W0_CF_ACK FIELD32(0x00000004) 3073 #define TXWI_W0_TS FIELD32(0x00000008) 3074 #define TXWI_W0_AMPDU FIELD32(0x00000010) 3075 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) 3076 #define TXWI_W0_TX_OP FIELD32(0x00000300) 3077 #define TXWI_W0_MCS FIELD32(0x007f0000) 3078 #define TXWI_W0_BW FIELD32(0x00800000) 3079 #define TXWI_W0_SHORT_GI FIELD32(0x01000000) 3080 #define TXWI_W0_STBC FIELD32(0x06000000) 3081 #define TXWI_W0_IFS FIELD32(0x08000000) 3082 #define TXWI_W0_PHYMODE FIELD32(0xc0000000) 3083 3084 /* 3085 * Word1 3086 * ACK: 0: No Ack needed, 1: Ack needed 3087 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number 3088 * BW_WIN_SIZE: BA windows size of the recipient 3089 * WIRELESS_CLI_ID: Client ID for WCID table access 3090 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame 3091 * PACKETID: Will be latched into the TX_STA_FIFO register once the according 3092 * frame was processed. If multiple frames are aggregated together 3093 * (AMPDU==1) the reported tx status will always contain the packet 3094 * id of the first frame. 0: Don't report tx status for this frame. 3095 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3) 3096 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3) 3097 * This identification number is calculated by ((idx % 3) + 1). 3098 * The (+1) is required to prevent PACKETID to become 0. 3099 */ 3100 #define TXWI_W1_ACK FIELD32(0x00000001) 3101 #define TXWI_W1_NSEQ FIELD32(0x00000002) 3102 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) 3103 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) 3104 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 3105 #define TXWI_W1_PACKETID FIELD32(0xf0000000) 3106 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000) 3107 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000) 3108 3109 /* 3110 * Word2 3111 */ 3112 #define TXWI_W2_IV FIELD32(0xffffffff) 3113 3114 /* 3115 * Word3 3116 */ 3117 #define TXWI_W3_EIV FIELD32(0xffffffff) 3118 3119 /* 3120 * RX WI structure 3121 */ 3122 3123 /* 3124 * Word0 3125 */ 3126 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) 3127 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) 3128 #define RXWI_W0_BSSID FIELD32(0x00001c00) 3129 #define RXWI_W0_UDF FIELD32(0x0000e000) 3130 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) 3131 #define RXWI_W0_TID FIELD32(0xf0000000) 3132 3133 /* 3134 * Word1 3135 */ 3136 #define RXWI_W1_FRAG FIELD32(0x0000000f) 3137 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) 3138 #define RXWI_W1_MCS FIELD32(0x007f0000) 3139 #define RXWI_W1_BW FIELD32(0x00800000) 3140 #define RXWI_W1_SHORT_GI FIELD32(0x01000000) 3141 #define RXWI_W1_STBC FIELD32(0x06000000) 3142 #define RXWI_W1_PHYMODE FIELD32(0xc0000000) 3143 3144 /* 3145 * Word2 3146 */ 3147 #define RXWI_W2_RSSI0 FIELD32(0x000000ff) 3148 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) 3149 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) 3150 3151 /* 3152 * Word3 3153 */ 3154 #define RXWI_W3_SNR0 FIELD32(0x000000ff) 3155 #define RXWI_W3_SNR1 FIELD32(0x0000ff00) 3156 3157 /* 3158 * Macros for converting txpower from EEPROM to mac80211 value 3159 * and from mac80211 value to register value. 3160 */ 3161 #define MIN_G_TXPOWER 0 3162 #define MIN_A_TXPOWER -7 3163 #define MAX_G_TXPOWER 31 3164 #define MAX_A_TXPOWER 15 3165 #define DEFAULT_TXPOWER 5 3166 3167 #define MIN_A_TXPOWER_3593 0 3168 #define MAX_A_TXPOWER_3593 31 3169 3170 #define TXPOWER_G_FROM_DEV(__txpower) \ 3171 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 3172 3173 #define TXPOWER_A_FROM_DEV(__txpower) \ 3174 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 3175 3176 /* 3177 * Board's maximun TX power limitation 3178 */ 3179 #define EIRP_MAX_TX_POWER_LIMIT 0x50 3180 3181 /* 3182 * Number of TBTT intervals after which we have to adjust 3183 * the hw beacon timer. 3184 */ 3185 #define BCN_TBTT_OFFSET 64 3186 3187 #endif /* RT2800_H */ 3188