1 /*
2 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 	<http://rt2x00.serialmonkey.com>
4 
5 	This program is free software; you can redistribute it and/or modify
6 	it under the terms of the GNU General Public License as published by
7 	the Free Software Foundation; either version 2 of the License, or
8 	(at your option) any later version.
9 
10 	This program is distributed in the hope that it will be useful,
11 	but WITHOUT ANY WARRANTY; without even the implied warranty of
12 	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 	GNU General Public License for more details.
14 
15 	You should have received a copy of the GNU General Public License
16 	along with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 /*
20 	Module: rt2500usb
21 	Abstract: Data structures and registers for the rt2500usb module.
22 	Supported chipsets: RT2570.
23  */
24 
25 #ifndef RT2500USB_H
26 #define RT2500USB_H
27 
28 /*
29  * RF chip defines.
30  */
31 #define RF2522				0x0000
32 #define RF2523				0x0001
33 #define RF2524				0x0002
34 #define RF2525				0x0003
35 #define RF2525E				0x0005
36 #define RF5222				0x0010
37 
38 /*
39  * RT2570 version
40  */
41 #define RT2570_VERSION_B		2
42 #define RT2570_VERSION_C		3
43 #define RT2570_VERSION_D		4
44 
45 /*
46  * Signal information.
47  * Default offset is required for RSSI <-> dBm conversion.
48  */
49 #define DEFAULT_RSSI_OFFSET		120
50 
51 /*
52  * Register layout information.
53  */
54 #define CSR_REG_BASE			0x0400
55 #define CSR_REG_SIZE			0x0100
56 #define EEPROM_BASE			0x0000
57 #define EEPROM_SIZE			0x006e
58 #define BBP_BASE			0x0000
59 #define BBP_SIZE			0x0060
60 #define RF_BASE				0x0004
61 #define RF_SIZE				0x0010
62 
63 /*
64  * Number of TX queues.
65  */
66 #define NUM_TX_QUEUES			2
67 
68 /*
69  * Control/Status Registers(CSR).
70  * Some values are set in TU, whereas 1 TU == 1024 us.
71  */
72 
73 /*
74  * MAC_CSR0: ASIC revision number.
75  */
76 #define MAC_CSR0			0x0400
77 
78 /*
79  * MAC_CSR1: System control.
80  * SOFT_RESET: Software reset, 1: reset, 0: normal.
81  * BBP_RESET: Hardware reset, 1: reset, 0, release.
82  * HOST_READY: Host ready after initialization.
83  */
84 #define MAC_CSR1			0x0402
85 #define MAC_CSR1_SOFT_RESET		FIELD16(0x00000001)
86 #define MAC_CSR1_BBP_RESET		FIELD16(0x00000002)
87 #define MAC_CSR1_HOST_READY		FIELD16(0x00000004)
88 
89 /*
90  * MAC_CSR2: STA MAC register 0.
91  */
92 #define MAC_CSR2			0x0404
93 #define MAC_CSR2_BYTE0			FIELD16(0x00ff)
94 #define MAC_CSR2_BYTE1			FIELD16(0xff00)
95 
96 /*
97  * MAC_CSR3: STA MAC register 1.
98  */
99 #define MAC_CSR3			0x0406
100 #define MAC_CSR3_BYTE2			FIELD16(0x00ff)
101 #define MAC_CSR3_BYTE3			FIELD16(0xff00)
102 
103 /*
104  * MAC_CSR4: STA MAC register 2.
105  */
106 #define MAC_CSR4			0X0408
107 #define MAC_CSR4_BYTE4			FIELD16(0x00ff)
108 #define MAC_CSR4_BYTE5			FIELD16(0xff00)
109 
110 /*
111  * MAC_CSR5: BSSID register 0.
112  */
113 #define MAC_CSR5			0x040a
114 #define MAC_CSR5_BYTE0			FIELD16(0x00ff)
115 #define MAC_CSR5_BYTE1			FIELD16(0xff00)
116 
117 /*
118  * MAC_CSR6: BSSID register 1.
119  */
120 #define MAC_CSR6			0x040c
121 #define MAC_CSR6_BYTE2			FIELD16(0x00ff)
122 #define MAC_CSR6_BYTE3			FIELD16(0xff00)
123 
124 /*
125  * MAC_CSR7: BSSID register 2.
126  */
127 #define MAC_CSR7			0x040e
128 #define MAC_CSR7_BYTE4			FIELD16(0x00ff)
129 #define MAC_CSR7_BYTE5			FIELD16(0xff00)
130 
131 /*
132  * MAC_CSR8: Max frame length.
133  */
134 #define MAC_CSR8			0x0410
135 #define MAC_CSR8_MAX_FRAME_UNIT		FIELD16(0x0fff)
136 
137 /*
138  * Misc MAC_CSR registers.
139  * MAC_CSR9: Timer control.
140  * MAC_CSR10: Slot time.
141  * MAC_CSR11: SIFS.
142  * MAC_CSR12: EIFS.
143  * MAC_CSR13: Power mode0.
144  * MAC_CSR14: Power mode1.
145  * MAC_CSR15: Power saving transition0
146  * MAC_CSR16: Power saving transition1
147  */
148 #define MAC_CSR9			0x0412
149 #define MAC_CSR10			0x0414
150 #define MAC_CSR11			0x0416
151 #define MAC_CSR12			0x0418
152 #define MAC_CSR13			0x041a
153 #define MAC_CSR14			0x041c
154 #define MAC_CSR15			0x041e
155 #define MAC_CSR16			0x0420
156 
157 /*
158  * MAC_CSR17: Manual power control / status register.
159  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
160  * SET_STATE: Set state. Write 1 to trigger, self cleared.
161  * BBP_DESIRE_STATE: BBP desired state.
162  * RF_DESIRE_STATE: RF desired state.
163  * BBP_CURRENT_STATE: BBP current state.
164  * RF_CURRENT_STATE: RF current state.
165  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
166  */
167 #define MAC_CSR17			0x0422
168 #define MAC_CSR17_SET_STATE		FIELD16(0x0001)
169 #define MAC_CSR17_BBP_DESIRE_STATE	FIELD16(0x0006)
170 #define MAC_CSR17_RF_DESIRE_STATE	FIELD16(0x0018)
171 #define MAC_CSR17_BBP_CURR_STATE	FIELD16(0x0060)
172 #define MAC_CSR17_RF_CURR_STATE		FIELD16(0x0180)
173 #define MAC_CSR17_PUT_TO_SLEEP		FIELD16(0x0200)
174 
175 /*
176  * MAC_CSR18: Wakeup timer register.
177  * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
178  * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
179  * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
180  */
181 #define MAC_CSR18			0x0424
182 #define MAC_CSR18_DELAY_AFTER_BEACON	FIELD16(0x00ff)
183 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP	FIELD16(0x7f00)
184 #define MAC_CSR18_AUTO_WAKE		FIELD16(0x8000)
185 
186 /*
187  * MAC_CSR19: GPIO control register.
188  *	MAC_CSR19_VALx: GPIO value
189  *	MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output
190  */
191 #define MAC_CSR19			0x0426
192 #define MAC_CSR19_VAL0			FIELD16(0x0001)
193 #define MAC_CSR19_VAL1			FIELD16(0x0002)
194 #define MAC_CSR19_VAL2			FIELD16(0x0004)
195 #define MAC_CSR19_VAL3			FIELD16(0x0008)
196 #define MAC_CSR19_VAL4			FIELD16(0x0010)
197 #define MAC_CSR19_VAL5			FIELD16(0x0020)
198 #define MAC_CSR19_VAL6			FIELD16(0x0040)
199 #define MAC_CSR19_VAL7			FIELD16(0x0080)
200 #define MAC_CSR19_DIR0			FIELD16(0x0100)
201 #define MAC_CSR19_DIR1			FIELD16(0x0200)
202 #define MAC_CSR19_DIR2			FIELD16(0x0400)
203 #define MAC_CSR19_DIR3			FIELD16(0x0800)
204 #define MAC_CSR19_DIR4			FIELD16(0x1000)
205 #define MAC_CSR19_DIR5			FIELD16(0x2000)
206 #define MAC_CSR19_DIR6			FIELD16(0x4000)
207 #define MAC_CSR19_DIR7			FIELD16(0x8000)
208 
209 /*
210  * MAC_CSR20: LED control register.
211  * ACTIVITY: 0: idle, 1: active.
212  * LINK: 0: linkoff, 1: linkup.
213  * ACTIVITY_POLARITY: 0: active low, 1: active high.
214  */
215 #define MAC_CSR20			0x0428
216 #define MAC_CSR20_ACTIVITY		FIELD16(0x0001)
217 #define MAC_CSR20_LINK			FIELD16(0x0002)
218 #define MAC_CSR20_ACTIVITY_POLARITY	FIELD16(0x0004)
219 
220 /*
221  * MAC_CSR21: LED control register.
222  * ON_PERIOD: On period, default 70ms.
223  * OFF_PERIOD: Off period, default 30ms.
224  */
225 #define MAC_CSR21			0x042a
226 #define MAC_CSR21_ON_PERIOD		FIELD16(0x00ff)
227 #define MAC_CSR21_OFF_PERIOD		FIELD16(0xff00)
228 
229 /*
230  * MAC_CSR22: Collision window control register.
231  */
232 #define MAC_CSR22			0x042c
233 
234 /*
235  * Transmit related CSRs.
236  * Some values are set in TU, whereas 1 TU == 1024 us.
237  */
238 
239 /*
240  * TXRX_CSR0: Security control register.
241  */
242 #define TXRX_CSR0			0x0440
243 #define TXRX_CSR0_ALGORITHM		FIELD16(0x0007)
244 #define TXRX_CSR0_IV_OFFSET		FIELD16(0x01f8)
245 #define TXRX_CSR0_KEY_ID		FIELD16(0x1e00)
246 
247 /*
248  * TXRX_CSR1: TX configuration.
249  * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
250  * TSF_OFFSET: TSF offset in MAC header.
251  * AUTO_SEQUENCE: Let ASIC control frame sequence number.
252  */
253 #define TXRX_CSR1			0x0442
254 #define TXRX_CSR1_ACK_TIMEOUT		FIELD16(0x00ff)
255 #define TXRX_CSR1_TSF_OFFSET		FIELD16(0x7f00)
256 #define TXRX_CSR1_AUTO_SEQUENCE		FIELD16(0x8000)
257 
258 /*
259  * TXRX_CSR2: RX control.
260  * DISABLE_RX: Disable rx engine.
261  * DROP_CRC: Drop crc error.
262  * DROP_PHYSICAL: Drop physical error.
263  * DROP_CONTROL: Drop control frame.
264  * DROP_NOT_TO_ME: Drop not to me unicast frame.
265  * DROP_TODS: Drop frame tods bit is true.
266  * DROP_VERSION_ERROR: Drop version error frame.
267  * DROP_MCAST: Drop multicast frames.
268  * DROP_BCAST: Drop broadcast frames.
269  */
270 #define TXRX_CSR2			0x0444
271 #define	TXRX_CSR2_DISABLE_RX		FIELD16(0x0001)
272 #define TXRX_CSR2_DROP_CRC		FIELD16(0x0002)
273 #define TXRX_CSR2_DROP_PHYSICAL		FIELD16(0x0004)
274 #define TXRX_CSR2_DROP_CONTROL		FIELD16(0x0008)
275 #define TXRX_CSR2_DROP_NOT_TO_ME	FIELD16(0x0010)
276 #define TXRX_CSR2_DROP_TODS		FIELD16(0x0020)
277 #define TXRX_CSR2_DROP_VERSION_ERROR	FIELD16(0x0040)
278 #define TXRX_CSR2_DROP_MULTICAST	FIELD16(0x0200)
279 #define TXRX_CSR2_DROP_BROADCAST	FIELD16(0x0400)
280 
281 /*
282  * RX BBP ID registers
283  * TXRX_CSR3: CCK RX BBP ID.
284  * TXRX_CSR4: OFDM RX BBP ID.
285  */
286 #define TXRX_CSR3			0x0446
287 #define TXRX_CSR4			0x0448
288 
289 /*
290  * TXRX_CSR5: CCK TX BBP ID0.
291  */
292 #define TXRX_CSR5			0x044a
293 #define TXRX_CSR5_BBP_ID0		FIELD16(0x007f)
294 #define TXRX_CSR5_BBP_ID0_VALID		FIELD16(0x0080)
295 #define TXRX_CSR5_BBP_ID1		FIELD16(0x7f00)
296 #define TXRX_CSR5_BBP_ID1_VALID		FIELD16(0x8000)
297 
298 /*
299  * TXRX_CSR6: CCK TX BBP ID1.
300  */
301 #define TXRX_CSR6			0x044c
302 #define TXRX_CSR6_BBP_ID0		FIELD16(0x007f)
303 #define TXRX_CSR6_BBP_ID0_VALID		FIELD16(0x0080)
304 #define TXRX_CSR6_BBP_ID1		FIELD16(0x7f00)
305 #define TXRX_CSR6_BBP_ID1_VALID		FIELD16(0x8000)
306 
307 /*
308  * TXRX_CSR7: OFDM TX BBP ID0.
309  */
310 #define TXRX_CSR7			0x044e
311 #define TXRX_CSR7_BBP_ID0		FIELD16(0x007f)
312 #define TXRX_CSR7_BBP_ID0_VALID		FIELD16(0x0080)
313 #define TXRX_CSR7_BBP_ID1		FIELD16(0x7f00)
314 #define TXRX_CSR7_BBP_ID1_VALID		FIELD16(0x8000)
315 
316 /*
317  * TXRX_CSR8: OFDM TX BBP ID1.
318  */
319 #define TXRX_CSR8			0x0450
320 #define TXRX_CSR8_BBP_ID0		FIELD16(0x007f)
321 #define TXRX_CSR8_BBP_ID0_VALID		FIELD16(0x0080)
322 #define TXRX_CSR8_BBP_ID1		FIELD16(0x7f00)
323 #define TXRX_CSR8_BBP_ID1_VALID		FIELD16(0x8000)
324 
325 /*
326  * TXRX_CSR9: TX ACK time-out.
327  */
328 #define TXRX_CSR9			0x0452
329 
330 /*
331  * TXRX_CSR10: Auto responder control.
332  */
333 #define TXRX_CSR10			0x0454
334 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
335 
336 /*
337  * TXRX_CSR11: Auto responder basic rate.
338  */
339 #define TXRX_CSR11			0x0456
340 
341 /*
342  * ACK/CTS time registers.
343  */
344 #define TXRX_CSR12			0x0458
345 #define TXRX_CSR13			0x045a
346 #define TXRX_CSR14			0x045c
347 #define TXRX_CSR15			0x045e
348 #define TXRX_CSR16			0x0460
349 #define TXRX_CSR17			0x0462
350 
351 /*
352  * TXRX_CSR18: Synchronization control register.
353  */
354 #define TXRX_CSR18			0x0464
355 #define TXRX_CSR18_OFFSET		FIELD16(0x000f)
356 #define TXRX_CSR18_INTERVAL		FIELD16(0xfff0)
357 
358 /*
359  * TXRX_CSR19: Synchronization control register.
360  * TSF_COUNT: Enable TSF auto counting.
361  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
362  * TBCN: Enable Tbcn with reload value.
363  * BEACON_GEN: Enable beacon generator.
364  */
365 #define TXRX_CSR19			0x0466
366 #define TXRX_CSR19_TSF_COUNT		FIELD16(0x0001)
367 #define TXRX_CSR19_TSF_SYNC		FIELD16(0x0006)
368 #define TXRX_CSR19_TBCN			FIELD16(0x0008)
369 #define TXRX_CSR19_BEACON_GEN		FIELD16(0x0010)
370 
371 /*
372  * TXRX_CSR20: Tx BEACON offset time control register.
373  * OFFSET: In units of usec.
374  * BCN_EXPECT_WINDOW: Default: 2^CWmin
375  */
376 #define TXRX_CSR20			0x0468
377 #define TXRX_CSR20_OFFSET		FIELD16(0x1fff)
378 #define TXRX_CSR20_BCN_EXPECT_WINDOW	FIELD16(0xe000)
379 
380 /*
381  * TXRX_CSR21
382  */
383 #define TXRX_CSR21			0x046a
384 
385 /*
386  * Encryption related CSRs.
387  *
388  */
389 
390 /*
391  * SEC_CSR0: Shared key 0, word 0
392  * SEC_CSR1: Shared key 0, word 1
393  * SEC_CSR2: Shared key 0, word 2
394  * SEC_CSR3: Shared key 0, word 3
395  * SEC_CSR4: Shared key 0, word 4
396  * SEC_CSR5: Shared key 0, word 5
397  * SEC_CSR6: Shared key 0, word 6
398  * SEC_CSR7: Shared key 0, word 7
399  */
400 #define SEC_CSR0			0x0480
401 #define SEC_CSR1			0x0482
402 #define SEC_CSR2			0x0484
403 #define SEC_CSR3			0x0486
404 #define SEC_CSR4			0x0488
405 #define SEC_CSR5			0x048a
406 #define SEC_CSR6			0x048c
407 #define SEC_CSR7			0x048e
408 
409 /*
410  * SEC_CSR8: Shared key 1, word 0
411  * SEC_CSR9: Shared key 1, word 1
412  * SEC_CSR10: Shared key 1, word 2
413  * SEC_CSR11: Shared key 1, word 3
414  * SEC_CSR12: Shared key 1, word 4
415  * SEC_CSR13: Shared key 1, word 5
416  * SEC_CSR14: Shared key 1, word 6
417  * SEC_CSR15: Shared key 1, word 7
418  */
419 #define SEC_CSR8			0x0490
420 #define SEC_CSR9			0x0492
421 #define SEC_CSR10			0x0494
422 #define SEC_CSR11			0x0496
423 #define SEC_CSR12			0x0498
424 #define SEC_CSR13			0x049a
425 #define SEC_CSR14			0x049c
426 #define SEC_CSR15			0x049e
427 
428 /*
429  * SEC_CSR16: Shared key 2, word 0
430  * SEC_CSR17: Shared key 2, word 1
431  * SEC_CSR18: Shared key 2, word 2
432  * SEC_CSR19: Shared key 2, word 3
433  * SEC_CSR20: Shared key 2, word 4
434  * SEC_CSR21: Shared key 2, word 5
435  * SEC_CSR22: Shared key 2, word 6
436  * SEC_CSR23: Shared key 2, word 7
437  */
438 #define SEC_CSR16			0x04a0
439 #define SEC_CSR17			0x04a2
440 #define SEC_CSR18			0X04A4
441 #define SEC_CSR19			0x04a6
442 #define SEC_CSR20			0x04a8
443 #define SEC_CSR21			0x04aa
444 #define SEC_CSR22			0x04ac
445 #define SEC_CSR23			0x04ae
446 
447 /*
448  * SEC_CSR24: Shared key 3, word 0
449  * SEC_CSR25: Shared key 3, word 1
450  * SEC_CSR26: Shared key 3, word 2
451  * SEC_CSR27: Shared key 3, word 3
452  * SEC_CSR28: Shared key 3, word 4
453  * SEC_CSR29: Shared key 3, word 5
454  * SEC_CSR30: Shared key 3, word 6
455  * SEC_CSR31: Shared key 3, word 7
456  */
457 #define SEC_CSR24			0x04b0
458 #define SEC_CSR25			0x04b2
459 #define SEC_CSR26			0x04b4
460 #define SEC_CSR27			0x04b6
461 #define SEC_CSR28			0x04b8
462 #define SEC_CSR29			0x04ba
463 #define SEC_CSR30			0x04bc
464 #define SEC_CSR31			0x04be
465 
466 #define KEY_ENTRY(__idx) \
467 	( SEC_CSR0 + ((__idx) * 16) )
468 
469 /*
470  * PHY control registers.
471  */
472 
473 /*
474  * PHY_CSR0: RF switching timing control.
475  */
476 #define PHY_CSR0			0x04c0
477 
478 /*
479  * PHY_CSR1: TX PA configuration.
480  */
481 #define PHY_CSR1			0x04c2
482 
483 /*
484  * MAC configuration registers.
485  */
486 
487 /*
488  * PHY_CSR2: TX MAC configuration.
489  * NOTE: Both register fields are complete dummy,
490  * documentation and legacy drivers are unclear un
491  * what this register means or what fields exists.
492  */
493 #define PHY_CSR2			0x04c4
494 #define PHY_CSR2_LNA			FIELD16(0x0002)
495 #define PHY_CSR2_LNA_MODE		FIELD16(0x3000)
496 
497 /*
498  * PHY_CSR3: RX MAC configuration.
499  */
500 #define PHY_CSR3			0x04c6
501 
502 /*
503  * PHY_CSR4: Interface configuration.
504  */
505 #define PHY_CSR4			0x04c8
506 #define PHY_CSR4_LOW_RF_LE		FIELD16(0x0001)
507 
508 /*
509  * BBP pre-TX registers.
510  * PHY_CSR5: BBP pre-TX CCK.
511  */
512 #define PHY_CSR5			0x04ca
513 #define PHY_CSR5_CCK			FIELD16(0x0003)
514 #define PHY_CSR5_CCK_FLIP		FIELD16(0x0004)
515 
516 /*
517  * BBP pre-TX registers.
518  * PHY_CSR6: BBP pre-TX OFDM.
519  */
520 #define PHY_CSR6			0x04cc
521 #define PHY_CSR6_OFDM			FIELD16(0x0003)
522 #define PHY_CSR6_OFDM_FLIP		FIELD16(0x0004)
523 
524 /*
525  * PHY_CSR7: BBP access register 0.
526  * BBP_DATA: BBP data.
527  * BBP_REG_ID: BBP register ID.
528  * BBP_READ_CONTROL: 0: write, 1: read.
529  */
530 #define PHY_CSR7			0x04ce
531 #define PHY_CSR7_DATA			FIELD16(0x00ff)
532 #define PHY_CSR7_REG_ID			FIELD16(0x7f00)
533 #define PHY_CSR7_READ_CONTROL		FIELD16(0x8000)
534 
535 /*
536  * PHY_CSR8: BBP access register 1.
537  * BBP_BUSY: ASIC is busy execute BBP programming.
538  */
539 #define PHY_CSR8			0x04d0
540 #define PHY_CSR8_BUSY			FIELD16(0x0001)
541 
542 /*
543  * PHY_CSR9: RF access register.
544  * RF_VALUE: Register value + id to program into rf/if.
545  */
546 #define PHY_CSR9			0x04d2
547 #define PHY_CSR9_RF_VALUE		FIELD16(0xffff)
548 
549 /*
550  * PHY_CSR10: RF access register.
551  * RF_VALUE: Register value + id to program into rf/if.
552  * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
553  * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
554  * RF_PLL_LD: Rf pll_ld status.
555  * RF_BUSY: 1: asic is busy execute rf programming.
556  */
557 #define PHY_CSR10			0x04d4
558 #define PHY_CSR10_RF_VALUE		FIELD16(0x00ff)
559 #define PHY_CSR10_RF_NUMBER_OF_BITS	FIELD16(0x1f00)
560 #define PHY_CSR10_RF_IF_SELECT		FIELD16(0x2000)
561 #define PHY_CSR10_RF_PLL_LD		FIELD16(0x4000)
562 #define PHY_CSR10_RF_BUSY		FIELD16(0x8000)
563 
564 /*
565  * STA_CSR0: FCS error count.
566  * FCS_ERROR: FCS error count, cleared when read.
567  */
568 #define STA_CSR0			0x04e0
569 #define STA_CSR0_FCS_ERROR		FIELD16(0xffff)
570 
571 /*
572  * STA_CSR1: PLCP error count.
573  */
574 #define STA_CSR1			0x04e2
575 
576 /*
577  * STA_CSR2: LONG error count.
578  */
579 #define STA_CSR2			0x04e4
580 
581 /*
582  * STA_CSR3: CCA false alarm.
583  * FALSE_CCA_ERROR: False CCA error count, cleared when read.
584  */
585 #define STA_CSR3			0x04e6
586 #define STA_CSR3_FALSE_CCA_ERROR	FIELD16(0xffff)
587 
588 /*
589  * STA_CSR4: RX FIFO overflow.
590  */
591 #define STA_CSR4			0x04e8
592 
593 /*
594  * STA_CSR5: Beacon sent counter.
595  */
596 #define STA_CSR5			0x04ea
597 
598 /*
599  *  Statistics registers
600  */
601 #define STA_CSR6			0x04ec
602 #define STA_CSR7			0x04ee
603 #define STA_CSR8			0x04f0
604 #define STA_CSR9			0x04f2
605 #define STA_CSR10			0x04f4
606 
607 /*
608  * BBP registers.
609  * The wordsize of the BBP is 8 bits.
610  */
611 
612 /*
613  * R2: TX antenna control
614  */
615 #define BBP_R2_TX_ANTENNA		FIELD8(0x03)
616 #define BBP_R2_TX_IQ_FLIP		FIELD8(0x04)
617 
618 /*
619  * R14: RX antenna control
620  */
621 #define BBP_R14_RX_ANTENNA		FIELD8(0x03)
622 #define BBP_R14_RX_IQ_FLIP		FIELD8(0x04)
623 
624 /*
625  * RF registers.
626  */
627 
628 /*
629  * RF 1
630  */
631 #define RF1_TUNER			FIELD32(0x00020000)
632 
633 /*
634  * RF 3
635  */
636 #define RF3_TUNER			FIELD32(0x00000100)
637 #define RF3_TXPOWER			FIELD32(0x00003e00)
638 
639 /*
640  * EEPROM contents.
641  */
642 
643 /*
644  * HW MAC address.
645  */
646 #define EEPROM_MAC_ADDR_0		0x0002
647 #define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
648 #define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
649 #define EEPROM_MAC_ADDR1		0x0003
650 #define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
651 #define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
652 #define EEPROM_MAC_ADDR_2		0x0004
653 #define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
654 #define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)
655 
656 /*
657  * EEPROM antenna.
658  * ANTENNA_NUM: Number of antenna's.
659  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
660  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
661  * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
662  * DYN_TXAGC: Dynamic TX AGC control.
663  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
664  * RF_TYPE: Rf_type of this adapter.
665  */
666 #define EEPROM_ANTENNA			0x000b
667 #define EEPROM_ANTENNA_NUM		FIELD16(0x0003)
668 #define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)
669 #define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)
670 #define EEPROM_ANTENNA_LED_MODE		FIELD16(0x01c0)
671 #define EEPROM_ANTENNA_DYN_TXAGC	FIELD16(0x0200)
672 #define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)
673 #define EEPROM_ANTENNA_RF_TYPE		FIELD16(0xf800)
674 
675 /*
676  * EEPROM NIC config.
677  * CARDBUS_ACCEL: 0: enable, 1: disable.
678  * DYN_BBP_TUNE: 0: enable, 1: disable.
679  * CCK_TX_POWER: CCK TX power compensation.
680  */
681 #define EEPROM_NIC			0x000c
682 #define EEPROM_NIC_CARDBUS_ACCEL	FIELD16(0x0001)
683 #define EEPROM_NIC_DYN_BBP_TUNE		FIELD16(0x0002)
684 #define EEPROM_NIC_CCK_TX_POWER		FIELD16(0x000c)
685 
686 /*
687  * EEPROM geography.
688  * GEO: Default geography setting for device.
689  */
690 #define EEPROM_GEOGRAPHY		0x000d
691 #define EEPROM_GEOGRAPHY_GEO		FIELD16(0x0f00)
692 
693 /*
694  * EEPROM BBP.
695  */
696 #define EEPROM_BBP_START		0x000e
697 #define EEPROM_BBP_SIZE			16
698 #define EEPROM_BBP_VALUE		FIELD16(0x00ff)
699 #define EEPROM_BBP_REG_ID		FIELD16(0xff00)
700 
701 /*
702  * EEPROM TXPOWER
703  */
704 #define EEPROM_TXPOWER_START		0x001e
705 #define EEPROM_TXPOWER_SIZE		7
706 #define EEPROM_TXPOWER_1		FIELD16(0x00ff)
707 #define EEPROM_TXPOWER_2		FIELD16(0xff00)
708 
709 /*
710  * EEPROM Tuning threshold
711  */
712 #define EEPROM_BBPTUNE			0x0030
713 #define EEPROM_BBPTUNE_THRESHOLD	FIELD16(0x00ff)
714 
715 /*
716  * EEPROM BBP R24 Tuning.
717  */
718 #define EEPROM_BBPTUNE_R24		0x0031
719 #define EEPROM_BBPTUNE_R24_LOW		FIELD16(0x00ff)
720 #define EEPROM_BBPTUNE_R24_HIGH		FIELD16(0xff00)
721 
722 /*
723  * EEPROM BBP R25 Tuning.
724  */
725 #define EEPROM_BBPTUNE_R25		0x0032
726 #define EEPROM_BBPTUNE_R25_LOW		FIELD16(0x00ff)
727 #define EEPROM_BBPTUNE_R25_HIGH		FIELD16(0xff00)
728 
729 /*
730  * EEPROM BBP R24 Tuning.
731  */
732 #define EEPROM_BBPTUNE_R61		0x0033
733 #define EEPROM_BBPTUNE_R61_LOW		FIELD16(0x00ff)
734 #define EEPROM_BBPTUNE_R61_HIGH		FIELD16(0xff00)
735 
736 /*
737  * EEPROM BBP VGC Tuning.
738  */
739 #define EEPROM_BBPTUNE_VGC		0x0034
740 #define EEPROM_BBPTUNE_VGCUPPER		FIELD16(0x00ff)
741 #define EEPROM_BBPTUNE_VGCLOWER		FIELD16(0xff00)
742 
743 /*
744  * EEPROM BBP R17 Tuning.
745  */
746 #define EEPROM_BBPTUNE_R17		0x0035
747 #define EEPROM_BBPTUNE_R17_LOW		FIELD16(0x00ff)
748 #define EEPROM_BBPTUNE_R17_HIGH		FIELD16(0xff00)
749 
750 /*
751  * RSSI <-> dBm offset calibration
752  */
753 #define EEPROM_CALIBRATE_OFFSET		0x0036
754 #define EEPROM_CALIBRATE_OFFSET_RSSI	FIELD16(0x00ff)
755 
756 /*
757  * DMA descriptor defines.
758  */
759 #define TXD_DESC_SIZE			( 5 * sizeof(__le32) )
760 #define RXD_DESC_SIZE			( 4 * sizeof(__le32) )
761 
762 /*
763  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
764  */
765 
766 /*
767  * Word0
768  */
769 #define TXD_W0_PACKET_ID		FIELD32(0x0000000f)
770 #define TXD_W0_RETRY_LIMIT		FIELD32(0x000000f0)
771 #define TXD_W0_MORE_FRAG		FIELD32(0x00000100)
772 #define TXD_W0_ACK			FIELD32(0x00000200)
773 #define TXD_W0_TIMESTAMP		FIELD32(0x00000400)
774 #define TXD_W0_OFDM			FIELD32(0x00000800)
775 #define TXD_W0_NEW_SEQ			FIELD32(0x00001000)
776 #define TXD_W0_IFS			FIELD32(0x00006000)
777 #define TXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
778 #define TXD_W0_CIPHER			FIELD32(0x20000000)
779 #define TXD_W0_KEY_ID			FIELD32(0xc0000000)
780 
781 /*
782  * Word1
783  */
784 #define TXD_W1_IV_OFFSET		FIELD32(0x0000003f)
785 #define TXD_W1_AIFS			FIELD32(0x000000c0)
786 #define TXD_W1_CWMIN			FIELD32(0x00000f00)
787 #define TXD_W1_CWMAX			FIELD32(0x0000f000)
788 
789 /*
790  * Word2: PLCP information
791  */
792 #define TXD_W2_PLCP_SIGNAL		FIELD32(0x000000ff)
793 #define TXD_W2_PLCP_SERVICE		FIELD32(0x0000ff00)
794 #define TXD_W2_PLCP_LENGTH_LOW		FIELD32(0x00ff0000)
795 #define TXD_W2_PLCP_LENGTH_HIGH		FIELD32(0xff000000)
796 
797 /*
798  * Word3
799  */
800 #define TXD_W3_IV			FIELD32(0xffffffff)
801 
802 /*
803  * Word4
804  */
805 #define TXD_W4_EIV			FIELD32(0xffffffff)
806 
807 /*
808  * RX descriptor format for RX Ring.
809  */
810 
811 /*
812  * Word0
813  */
814 #define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000002)
815 #define RXD_W0_MULTICAST		FIELD32(0x00000004)
816 #define RXD_W0_BROADCAST		FIELD32(0x00000008)
817 #define RXD_W0_MY_BSS			FIELD32(0x00000010)
818 #define RXD_W0_CRC_ERROR		FIELD32(0x00000020)
819 #define RXD_W0_OFDM			FIELD32(0x00000040)
820 #define RXD_W0_PHYSICAL_ERROR		FIELD32(0x00000080)
821 #define RXD_W0_CIPHER			FIELD32(0x00000100)
822 #define RXD_W0_CIPHER_ERROR		FIELD32(0x00000200)
823 #define RXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
824 
825 /*
826  * Word1
827  */
828 #define RXD_W1_RSSI			FIELD32(0x000000ff)
829 #define RXD_W1_SIGNAL			FIELD32(0x0000ff00)
830 
831 /*
832  * Word2
833  */
834 #define RXD_W2_IV			FIELD32(0xffffffff)
835 
836 /*
837  * Word3
838  */
839 #define RXD_W3_EIV			FIELD32(0xffffffff)
840 
841 /*
842  * Macros for converting txpower from EEPROM to mac80211 value
843  * and from mac80211 value to register value.
844  */
845 #define MIN_TXPOWER	0
846 #define MAX_TXPOWER	31
847 #define DEFAULT_TXPOWER	24
848 
849 #define TXPOWER_FROM_DEV(__txpower) \
850 	(((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
851 
852 #define TXPOWER_TO_DEV(__txpower) \
853 	clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
854 
855 #endif /* RT2500USB_H */
856