1 /* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 /* 20 Module: rt2500pci 21 Abstract: rt2500pci device specific routines. 22 Supported chipsets: RT2560. 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/etherdevice.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/eeprom_93cx6.h> 31 #include <linux/slab.h> 32 33 #include "rt2x00.h" 34 #include "rt2x00mmio.h" 35 #include "rt2x00pci.h" 36 #include "rt2500pci.h" 37 38 /* 39 * Register access. 40 * All access to the CSR registers will go through the methods 41 * rt2x00mmio_register_read and rt2x00mmio_register_write. 42 * BBP and RF register require indirect register access, 43 * and use the CSR registers BBPCSR and RFCSR to achieve this. 44 * These indirect registers work with busy bits, 45 * and we will try maximal REGISTER_BUSY_COUNT times to access 46 * the register while taking a REGISTER_BUSY_DELAY us delay 47 * between each attampt. When the busy bit is still set at that time, 48 * the access attempt is considered to have failed, 49 * and we will print an error. 50 */ 51 #define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) 53 #define WAIT_FOR_RF(__dev, __reg) \ 54 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) 55 56 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, 57 const unsigned int word, const u8 value) 58 { 59 u32 reg; 60 61 mutex_lock(&rt2x00dev->csr_mutex); 62 63 /* 64 * Wait until the BBP becomes available, afterwards we 65 * can safely write the new data into the register. 66 */ 67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 68 reg = 0; 69 rt2x00_set_field32(®, BBPCSR_VALUE, value); 70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); 71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); 72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); 73 74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); 75 } 76 77 mutex_unlock(&rt2x00dev->csr_mutex); 78 } 79 80 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, 81 const unsigned int word, u8 *value) 82 { 83 u32 reg; 84 85 mutex_lock(&rt2x00dev->csr_mutex); 86 87 /* 88 * Wait until the BBP becomes available, afterwards we 89 * can safely write the read request into the register. 90 * After the data has been written, we wait until hardware 91 * returns the correct value, if at any time the register 92 * doesn't become available in time, reg will be 0xffffffff 93 * which means we return 0xff to the caller. 94 */ 95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 96 reg = 0; 97 rt2x00_set_field32(®, BBPCSR_REGNUM, word); 98 rt2x00_set_field32(®, BBPCSR_BUSY, 1); 99 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); 100 101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); 102 103 WAIT_FOR_BBP(rt2x00dev, ®); 104 } 105 106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); 107 108 mutex_unlock(&rt2x00dev->csr_mutex); 109 } 110 111 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, 112 const unsigned int word, const u32 value) 113 { 114 u32 reg; 115 116 mutex_lock(&rt2x00dev->csr_mutex); 117 118 /* 119 * Wait until the RF becomes available, afterwards we 120 * can safely write the new data into the register. 121 */ 122 if (WAIT_FOR_RF(rt2x00dev, ®)) { 123 reg = 0; 124 rt2x00_set_field32(®, RFCSR_VALUE, value); 125 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); 126 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); 127 rt2x00_set_field32(®, RFCSR_BUSY, 1); 128 129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); 130 rt2x00_rf_write(rt2x00dev, word, value); 131 } 132 133 mutex_unlock(&rt2x00dev->csr_mutex); 134 } 135 136 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 137 { 138 struct rt2x00_dev *rt2x00dev = eeprom->data; 139 u32 reg; 140 141 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); 142 143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); 144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); 145 eeprom->reg_data_clock = 146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); 147 eeprom->reg_chip_select = 148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); 149 } 150 151 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom) 152 { 153 struct rt2x00_dev *rt2x00dev = eeprom->data; 154 u32 reg = 0; 155 156 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); 157 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); 158 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, 159 !!eeprom->reg_data_clock); 160 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, 161 !!eeprom->reg_chip_select); 162 163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); 164 } 165 166 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 167 static u8 _rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, 168 const unsigned int word) 169 { 170 u8 value; 171 172 rt2500pci_bbp_read(rt2x00dev, word, &value); 173 174 return value; 175 } 176 177 static const struct rt2x00debug rt2500pci_rt2x00debug = { 178 .owner = THIS_MODULE, 179 .csr = { 180 .read = _rt2x00mmio_register_read, 181 .write = rt2x00mmio_register_write, 182 .flags = RT2X00DEBUGFS_OFFSET, 183 .word_base = CSR_REG_BASE, 184 .word_size = sizeof(u32), 185 .word_count = CSR_REG_SIZE / sizeof(u32), 186 }, 187 .eeprom = { 188 .read = _rt2x00_eeprom_read, 189 .write = rt2x00_eeprom_write, 190 .word_base = EEPROM_BASE, 191 .word_size = sizeof(u16), 192 .word_count = EEPROM_SIZE / sizeof(u16), 193 }, 194 .bbp = { 195 .read = _rt2500pci_bbp_read, 196 .write = rt2500pci_bbp_write, 197 .word_base = BBP_BASE, 198 .word_size = sizeof(u8), 199 .word_count = BBP_SIZE / sizeof(u8), 200 }, 201 .rf = { 202 .read = _rt2x00_rf_read, 203 .write = rt2500pci_rf_write, 204 .word_base = RF_BASE, 205 .word_size = sizeof(u32), 206 .word_count = RF_SIZE / sizeof(u32), 207 }, 208 }; 209 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 210 211 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) 212 { 213 u32 reg; 214 215 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); 216 return rt2x00_get_field32(reg, GPIOCSR_VAL0); 217 } 218 219 #ifdef CONFIG_RT2X00_LIB_LEDS 220 static void rt2500pci_brightness_set(struct led_classdev *led_cdev, 221 enum led_brightness brightness) 222 { 223 struct rt2x00_led *led = 224 container_of(led_cdev, struct rt2x00_led, led_dev); 225 unsigned int enabled = brightness != LED_OFF; 226 u32 reg; 227 228 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); 229 230 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) 231 rt2x00_set_field32(®, LEDCSR_LINK, enabled); 232 else if (led->type == LED_TYPE_ACTIVITY) 233 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); 234 235 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); 236 } 237 238 static int rt2500pci_blink_set(struct led_classdev *led_cdev, 239 unsigned long *delay_on, 240 unsigned long *delay_off) 241 { 242 struct rt2x00_led *led = 243 container_of(led_cdev, struct rt2x00_led, led_dev); 244 u32 reg; 245 246 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, ®); 247 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); 248 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); 249 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); 250 251 return 0; 252 } 253 254 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev, 255 struct rt2x00_led *led, 256 enum led_type type) 257 { 258 led->rt2x00dev = rt2x00dev; 259 led->type = type; 260 led->led_dev.brightness_set = rt2500pci_brightness_set; 261 led->led_dev.blink_set = rt2500pci_blink_set; 262 led->flags = LED_INITIALIZED; 263 } 264 #endif /* CONFIG_RT2X00_LIB_LEDS */ 265 266 /* 267 * Configuration handlers. 268 */ 269 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev, 270 const unsigned int filter_flags) 271 { 272 u32 reg; 273 274 /* 275 * Start configuration steps. 276 * Note that the version error will always be dropped 277 * and broadcast frames will always be accepted since 278 * there is no filter for it at this time. 279 */ 280 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); 281 rt2x00_set_field32(®, RXCSR0_DROP_CRC, 282 !(filter_flags & FIF_FCSFAIL)); 283 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, 284 !(filter_flags & FIF_PLCPFAIL)); 285 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, 286 !(filter_flags & FIF_CONTROL)); 287 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, 288 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 289 rt2x00_set_field32(®, RXCSR0_DROP_TODS, 290 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && 291 !rt2x00dev->intf_ap_count); 292 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); 293 rt2x00_set_field32(®, RXCSR0_DROP_MCAST, 294 !(filter_flags & FIF_ALLMULTI)); 295 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); 296 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); 297 } 298 299 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, 300 struct rt2x00_intf *intf, 301 struct rt2x00intf_conf *conf, 302 const unsigned int flags) 303 { 304 struct data_queue *queue = rt2x00dev->bcn; 305 unsigned int bcn_preload; 306 u32 reg; 307 308 if (flags & CONFIG_UPDATE_TYPE) { 309 /* 310 * Enable beacon config 311 */ 312 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); 313 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, ®); 314 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); 315 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); 316 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); 317 318 /* 319 * Enable synchronisation. 320 */ 321 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); 322 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); 323 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 324 } 325 326 if (flags & CONFIG_UPDATE_MAC) 327 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, 328 conf->mac, sizeof(conf->mac)); 329 330 if (flags & CONFIG_UPDATE_BSSID) 331 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, 332 conf->bssid, sizeof(conf->bssid)); 333 } 334 335 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 336 struct rt2x00lib_erp *erp, 337 u32 changed) 338 { 339 int preamble_mask; 340 u32 reg; 341 342 /* 343 * When short preamble is enabled, we should set bit 0x08 344 */ 345 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 346 preamble_mask = erp->short_preamble << 3; 347 348 rt2x00mmio_register_read(rt2x00dev, TXCSR1, ®); 349 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); 350 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); 351 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 352 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); 353 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); 354 355 rt2x00mmio_register_read(rt2x00dev, ARCSR2, ®); 356 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); 357 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); 358 rt2x00_set_field32(®, ARCSR2_LENGTH, 359 GET_DURATION(ACK_SIZE, 10)); 360 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); 361 362 rt2x00mmio_register_read(rt2x00dev, ARCSR3, ®); 363 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); 364 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); 365 rt2x00_set_field32(®, ARCSR2_LENGTH, 366 GET_DURATION(ACK_SIZE, 20)); 367 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); 368 369 rt2x00mmio_register_read(rt2x00dev, ARCSR4, ®); 370 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); 371 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); 372 rt2x00_set_field32(®, ARCSR2_LENGTH, 373 GET_DURATION(ACK_SIZE, 55)); 374 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); 375 376 rt2x00mmio_register_read(rt2x00dev, ARCSR5, ®); 377 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); 378 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); 379 rt2x00_set_field32(®, ARCSR2_LENGTH, 380 GET_DURATION(ACK_SIZE, 110)); 381 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); 382 } 383 384 if (changed & BSS_CHANGED_BASIC_RATES) 385 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 386 387 if (changed & BSS_CHANGED_ERP_SLOT) { 388 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); 389 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); 390 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); 391 392 rt2x00mmio_register_read(rt2x00dev, CSR18, ®); 393 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); 394 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); 395 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); 396 397 rt2x00mmio_register_read(rt2x00dev, CSR19, ®); 398 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); 399 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); 400 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); 401 } 402 403 if (changed & BSS_CHANGED_BEACON_INT) { 404 rt2x00mmio_register_read(rt2x00dev, CSR12, ®); 405 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, 406 erp->beacon_int * 16); 407 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, 408 erp->beacon_int * 16); 409 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); 410 } 411 412 } 413 414 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, 415 struct antenna_setup *ant) 416 { 417 u32 reg; 418 u8 r14; 419 u8 r2; 420 421 /* 422 * We should never come here because rt2x00lib is supposed 423 * to catch this and send us the correct antenna explicitely. 424 */ 425 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || 426 ant->tx == ANTENNA_SW_DIVERSITY); 427 428 rt2x00mmio_register_read(rt2x00dev, BBPCSR1, ®); 429 rt2500pci_bbp_read(rt2x00dev, 14, &r14); 430 rt2500pci_bbp_read(rt2x00dev, 2, &r2); 431 432 /* 433 * Configure the TX antenna. 434 */ 435 switch (ant->tx) { 436 case ANTENNA_A: 437 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0); 438 rt2x00_set_field32(®, BBPCSR1_CCK, 0); 439 rt2x00_set_field32(®, BBPCSR1_OFDM, 0); 440 break; 441 case ANTENNA_B: 442 default: 443 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2); 444 rt2x00_set_field32(®, BBPCSR1_CCK, 2); 445 rt2x00_set_field32(®, BBPCSR1_OFDM, 2); 446 break; 447 } 448 449 /* 450 * Configure the RX antenna. 451 */ 452 switch (ant->rx) { 453 case ANTENNA_A: 454 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0); 455 break; 456 case ANTENNA_B: 457 default: 458 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2); 459 break; 460 } 461 462 /* 463 * RT2525E and RT5222 need to flip TX I/Q 464 */ 465 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) { 466 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); 467 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); 468 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); 469 470 /* 471 * RT2525E does not need RX I/Q Flip. 472 */ 473 if (rt2x00_rf(rt2x00dev, RF2525E)) 474 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); 475 } else { 476 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); 477 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); 478 } 479 480 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); 481 rt2500pci_bbp_write(rt2x00dev, 14, r14); 482 rt2500pci_bbp_write(rt2x00dev, 2, r2); 483 } 484 485 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev, 486 struct rf_channel *rf, const int txpower) 487 { 488 u8 r70; 489 490 /* 491 * Set TXpower. 492 */ 493 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 494 495 /* 496 * Switch on tuning bits. 497 * For RT2523 devices we do not need to update the R1 register. 498 */ 499 if (!rt2x00_rf(rt2x00dev, RF2523)) 500 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); 501 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); 502 503 /* 504 * For RT2525 we should first set the channel to half band higher. 505 */ 506 if (rt2x00_rf(rt2x00dev, RF2525)) { 507 static const u32 vals[] = { 508 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, 509 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, 510 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a, 511 0x00080d2e, 0x00080d3a 512 }; 513 514 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 515 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]); 516 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); 517 if (rf->rf4) 518 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); 519 } 520 521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 522 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2); 523 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); 524 if (rf->rf4) 525 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); 526 527 /* 528 * Channel 14 requires the Japan filter bit to be set. 529 */ 530 r70 = 0x46; 531 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14); 532 rt2500pci_bbp_write(rt2x00dev, 70, r70); 533 534 msleep(1); 535 536 /* 537 * Switch off tuning bits. 538 * For RT2523 devices we do not need to update the R1 register. 539 */ 540 if (!rt2x00_rf(rt2x00dev, RF2523)) { 541 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); 542 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); 543 } 544 545 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); 546 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); 547 548 /* 549 * Clear false CRC during channel switch. 550 */ 551 rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1); 552 } 553 554 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, 555 const int txpower) 556 { 557 u32 rf3; 558 559 rt2x00_rf_read(rt2x00dev, 3, &rf3); 560 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); 561 rt2500pci_rf_write(rt2x00dev, 3, rf3); 562 } 563 564 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, 565 struct rt2x00lib_conf *libconf) 566 { 567 u32 reg; 568 569 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); 570 rt2x00_set_field32(®, CSR11_LONG_RETRY, 571 libconf->conf->long_frame_max_tx_count); 572 rt2x00_set_field32(®, CSR11_SHORT_RETRY, 573 libconf->conf->short_frame_max_tx_count); 574 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); 575 } 576 577 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, 578 struct rt2x00lib_conf *libconf) 579 { 580 enum dev_state state = 581 (libconf->conf->flags & IEEE80211_CONF_PS) ? 582 STATE_SLEEP : STATE_AWAKE; 583 u32 reg; 584 585 if (state == STATE_SLEEP) { 586 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); 587 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, 588 (rt2x00dev->beacon_int - 20) * 16); 589 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, 590 libconf->conf->listen_interval - 1); 591 592 /* We must first disable autowake before it can be enabled */ 593 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); 594 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); 595 596 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); 597 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); 598 } else { 599 rt2x00mmio_register_read(rt2x00dev, CSR20, ®); 600 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); 601 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); 602 } 603 604 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 605 } 606 607 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev, 608 struct rt2x00lib_conf *libconf, 609 const unsigned int flags) 610 { 611 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 612 rt2500pci_config_channel(rt2x00dev, &libconf->rf, 613 libconf->conf->power_level); 614 if ((flags & IEEE80211_CONF_CHANGE_POWER) && 615 !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) 616 rt2500pci_config_txpower(rt2x00dev, 617 libconf->conf->power_level); 618 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 619 rt2500pci_config_retry_limit(rt2x00dev, libconf); 620 if (flags & IEEE80211_CONF_CHANGE_PS) 621 rt2500pci_config_ps(rt2x00dev, libconf); 622 } 623 624 /* 625 * Link tuning 626 */ 627 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev, 628 struct link_qual *qual) 629 { 630 u32 reg; 631 632 /* 633 * Update FCS error count from register. 634 */ 635 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); 636 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); 637 638 /* 639 * Update False CCA count from register. 640 */ 641 rt2x00mmio_register_read(rt2x00dev, CNT3, ®); 642 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); 643 } 644 645 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev, 646 struct link_qual *qual, u8 vgc_level) 647 { 648 if (qual->vgc_level_reg != vgc_level) { 649 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level); 650 qual->vgc_level = vgc_level; 651 qual->vgc_level_reg = vgc_level; 652 } 653 } 654 655 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev, 656 struct link_qual *qual) 657 { 658 rt2500pci_set_vgc(rt2x00dev, qual, 0x48); 659 } 660 661 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, 662 struct link_qual *qual, const u32 count) 663 { 664 /* 665 * To prevent collisions with MAC ASIC on chipsets 666 * up to version C the link tuning should halt after 20 667 * seconds while being associated. 668 */ 669 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D && 670 rt2x00dev->intf_associated && count > 20) 671 return; 672 673 /* 674 * Chipset versions C and lower should directly continue 675 * to the dynamic CCA tuning. Chipset version D and higher 676 * should go straight to dynamic CCA tuning when they 677 * are not associated. 678 */ 679 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D || 680 !rt2x00dev->intf_associated) 681 goto dynamic_cca_tune; 682 683 /* 684 * A too low RSSI will cause too much false CCA which will 685 * then corrupt the R17 tuning. To remidy this the tuning should 686 * be stopped (While making sure the R17 value will not exceed limits) 687 */ 688 if (qual->rssi < -80 && count > 20) { 689 if (qual->vgc_level_reg >= 0x41) 690 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); 691 return; 692 } 693 694 /* 695 * Special big-R17 for short distance 696 */ 697 if (qual->rssi >= -58) { 698 rt2500pci_set_vgc(rt2x00dev, qual, 0x50); 699 return; 700 } 701 702 /* 703 * Special mid-R17 for middle distance 704 */ 705 if (qual->rssi >= -74) { 706 rt2500pci_set_vgc(rt2x00dev, qual, 0x41); 707 return; 708 } 709 710 /* 711 * Leave short or middle distance condition, restore r17 712 * to the dynamic tuning range. 713 */ 714 if (qual->vgc_level_reg >= 0x41) { 715 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); 716 return; 717 } 718 719 dynamic_cca_tune: 720 721 /* 722 * R17 is inside the dynamic tuning range, 723 * start tuning the link based on the false cca counter. 724 */ 725 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) 726 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg); 727 else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) 728 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg); 729 } 730 731 /* 732 * Queue handlers. 733 */ 734 static void rt2500pci_start_queue(struct data_queue *queue) 735 { 736 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 737 u32 reg; 738 739 switch (queue->qid) { 740 case QID_RX: 741 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); 742 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); 743 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); 744 break; 745 case QID_BEACON: 746 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); 747 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); 748 rt2x00_set_field32(®, CSR14_TBCN, 1); 749 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); 750 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 751 break; 752 default: 753 break; 754 } 755 } 756 757 static void rt2500pci_kick_queue(struct data_queue *queue) 758 { 759 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 760 u32 reg; 761 762 switch (queue->qid) { 763 case QID_AC_VO: 764 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); 765 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); 766 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 767 break; 768 case QID_AC_VI: 769 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); 770 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); 771 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 772 break; 773 case QID_ATIM: 774 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); 775 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); 776 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 777 break; 778 default: 779 break; 780 } 781 } 782 783 static void rt2500pci_stop_queue(struct data_queue *queue) 784 { 785 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 786 u32 reg; 787 788 switch (queue->qid) { 789 case QID_AC_VO: 790 case QID_AC_VI: 791 case QID_ATIM: 792 rt2x00mmio_register_read(rt2x00dev, TXCSR0, ®); 793 rt2x00_set_field32(®, TXCSR0_ABORT, 1); 794 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); 795 break; 796 case QID_RX: 797 rt2x00mmio_register_read(rt2x00dev, RXCSR0, ®); 798 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); 799 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); 800 break; 801 case QID_BEACON: 802 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); 803 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); 804 rt2x00_set_field32(®, CSR14_TBCN, 0); 805 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); 806 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 807 808 /* 809 * Wait for possibly running tbtt tasklets. 810 */ 811 tasklet_kill(&rt2x00dev->tbtt_tasklet); 812 break; 813 default: 814 break; 815 } 816 } 817 818 /* 819 * Initialization functions. 820 */ 821 static bool rt2500pci_get_entry_state(struct queue_entry *entry) 822 { 823 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 824 u32 word; 825 826 if (entry->queue->qid == QID_RX) { 827 rt2x00_desc_read(entry_priv->desc, 0, &word); 828 829 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); 830 } else { 831 rt2x00_desc_read(entry_priv->desc, 0, &word); 832 833 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 834 rt2x00_get_field32(word, TXD_W0_VALID)); 835 } 836 } 837 838 static void rt2500pci_clear_entry(struct queue_entry *entry) 839 { 840 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 841 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 842 u32 word; 843 844 if (entry->queue->qid == QID_RX) { 845 rt2x00_desc_read(entry_priv->desc, 1, &word); 846 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 847 rt2x00_desc_write(entry_priv->desc, 1, word); 848 849 rt2x00_desc_read(entry_priv->desc, 0, &word); 850 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 851 rt2x00_desc_write(entry_priv->desc, 0, word); 852 } else { 853 rt2x00_desc_read(entry_priv->desc, 0, &word); 854 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 855 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 856 rt2x00_desc_write(entry_priv->desc, 0, word); 857 } 858 } 859 860 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) 861 { 862 struct queue_entry_priv_mmio *entry_priv; 863 u32 reg; 864 865 /* 866 * Initialize registers. 867 */ 868 rt2x00mmio_register_read(rt2x00dev, TXCSR2, ®); 869 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 870 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 871 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); 872 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 873 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); 874 875 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 876 rt2x00mmio_register_read(rt2x00dev, TXCSR3, ®); 877 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, 878 entry_priv->desc_dma); 879 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); 880 881 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 882 rt2x00mmio_register_read(rt2x00dev, TXCSR5, ®); 883 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, 884 entry_priv->desc_dma); 885 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); 886 887 entry_priv = rt2x00dev->atim->entries[0].priv_data; 888 rt2x00mmio_register_read(rt2x00dev, TXCSR4, ®); 889 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, 890 entry_priv->desc_dma); 891 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); 892 893 entry_priv = rt2x00dev->bcn->entries[0].priv_data; 894 rt2x00mmio_register_read(rt2x00dev, TXCSR6, ®); 895 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, 896 entry_priv->desc_dma); 897 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); 898 899 rt2x00mmio_register_read(rt2x00dev, RXCSR1, ®); 900 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); 901 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 902 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); 903 904 entry_priv = rt2x00dev->rx->entries[0].priv_data; 905 rt2x00mmio_register_read(rt2x00dev, RXCSR2, ®); 906 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, 907 entry_priv->desc_dma); 908 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); 909 910 return 0; 911 } 912 913 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev) 914 { 915 u32 reg; 916 917 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); 918 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); 919 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002); 920 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); 921 922 rt2x00mmio_register_read(rt2x00dev, TIMECSR, ®); 923 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); 924 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); 925 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); 926 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); 927 928 rt2x00mmio_register_read(rt2x00dev, CSR9, ®); 929 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, 930 rt2x00dev->rx->data_size / 128); 931 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); 932 933 /* 934 * Always use CWmin and CWmax set in descriptor. 935 */ 936 rt2x00mmio_register_read(rt2x00dev, CSR11, ®); 937 rt2x00_set_field32(®, CSR11_CW_SELECT, 0); 938 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); 939 940 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); 941 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); 942 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); 943 rt2x00_set_field32(®, CSR14_TBCN, 0); 944 rt2x00_set_field32(®, CSR14_TCFP, 0); 945 rt2x00_set_field32(®, CSR14_TATIMW, 0); 946 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); 947 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); 948 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); 949 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 950 951 rt2x00mmio_register_write(rt2x00dev, CNT3, 0); 952 953 rt2x00mmio_register_read(rt2x00dev, TXCSR8, ®); 954 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); 955 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); 956 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); 957 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); 958 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); 959 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); 960 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); 961 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); 962 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); 963 964 rt2x00mmio_register_read(rt2x00dev, ARTCSR0, ®); 965 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); 966 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); 967 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); 968 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); 969 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); 970 971 rt2x00mmio_register_read(rt2x00dev, ARTCSR1, ®); 972 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); 973 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); 974 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); 975 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); 976 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); 977 978 rt2x00mmio_register_read(rt2x00dev, ARTCSR2, ®); 979 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); 980 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); 981 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); 982 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); 983 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); 984 985 rt2x00mmio_register_read(rt2x00dev, RXCSR3, ®); 986 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ 987 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); 988 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ 989 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); 990 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ 991 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); 992 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ 993 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); 994 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); 995 996 rt2x00mmio_register_read(rt2x00dev, PCICSR, ®); 997 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); 998 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); 999 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); 1000 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); 1001 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); 1002 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); 1003 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); 1004 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); 1005 1006 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); 1007 1008 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); 1009 rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0); 1010 1011 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1012 return -EBUSY; 1013 1014 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223); 1015 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); 1016 1017 rt2x00mmio_register_read(rt2x00dev, MACCSR2, ®); 1018 rt2x00_set_field32(®, MACCSR2_DELAY, 64); 1019 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); 1020 1021 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, ®); 1022 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); 1023 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); 1024 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); 1025 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); 1026 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); 1027 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); 1028 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); 1029 1030 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200); 1031 1032 rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020); 1033 1034 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); 1035 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); 1036 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); 1037 rt2x00_set_field32(®, CSR1_HOST_READY, 0); 1038 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); 1039 1040 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); 1041 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); 1042 rt2x00_set_field32(®, CSR1_HOST_READY, 1); 1043 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); 1044 1045 /* 1046 * We must clear the FCS and FIFO error count. 1047 * These registers are cleared on read, 1048 * so we may pass a useless variable to store the value. 1049 */ 1050 rt2x00mmio_register_read(rt2x00dev, CNT0, ®); 1051 rt2x00mmio_register_read(rt2x00dev, CNT4, ®); 1052 1053 return 0; 1054 } 1055 1056 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 1057 { 1058 unsigned int i; 1059 u8 value; 1060 1061 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1062 rt2500pci_bbp_read(rt2x00dev, 0, &value); 1063 if ((value != 0xff) && (value != 0x00)) 1064 return 0; 1065 udelay(REGISTER_BUSY_DELAY); 1066 } 1067 1068 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 1069 return -EACCES; 1070 } 1071 1072 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) 1073 { 1074 unsigned int i; 1075 u16 eeprom; 1076 u8 reg_id; 1077 u8 value; 1078 1079 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev))) 1080 return -EACCES; 1081 1082 rt2500pci_bbp_write(rt2x00dev, 3, 0x02); 1083 rt2500pci_bbp_write(rt2x00dev, 4, 0x19); 1084 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); 1085 rt2500pci_bbp_write(rt2x00dev, 15, 0x30); 1086 rt2500pci_bbp_write(rt2x00dev, 16, 0xac); 1087 rt2500pci_bbp_write(rt2x00dev, 18, 0x18); 1088 rt2500pci_bbp_write(rt2x00dev, 19, 0xff); 1089 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); 1090 rt2500pci_bbp_write(rt2x00dev, 21, 0x08); 1091 rt2500pci_bbp_write(rt2x00dev, 22, 0x08); 1092 rt2500pci_bbp_write(rt2x00dev, 23, 0x08); 1093 rt2500pci_bbp_write(rt2x00dev, 24, 0x70); 1094 rt2500pci_bbp_write(rt2x00dev, 25, 0x40); 1095 rt2500pci_bbp_write(rt2x00dev, 26, 0x08); 1096 rt2500pci_bbp_write(rt2x00dev, 27, 0x23); 1097 rt2500pci_bbp_write(rt2x00dev, 30, 0x10); 1098 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); 1099 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); 1100 rt2500pci_bbp_write(rt2x00dev, 34, 0x12); 1101 rt2500pci_bbp_write(rt2x00dev, 35, 0x50); 1102 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); 1103 rt2500pci_bbp_write(rt2x00dev, 40, 0x02); 1104 rt2500pci_bbp_write(rt2x00dev, 41, 0x60); 1105 rt2500pci_bbp_write(rt2x00dev, 53, 0x10); 1106 rt2500pci_bbp_write(rt2x00dev, 54, 0x18); 1107 rt2500pci_bbp_write(rt2x00dev, 56, 0x08); 1108 rt2500pci_bbp_write(rt2x00dev, 57, 0x10); 1109 rt2500pci_bbp_write(rt2x00dev, 58, 0x08); 1110 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); 1111 rt2500pci_bbp_write(rt2x00dev, 62, 0x10); 1112 1113 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1114 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1115 1116 if (eeprom != 0xffff && eeprom != 0x0000) { 1117 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 1118 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 1119 rt2500pci_bbp_write(rt2x00dev, reg_id, value); 1120 } 1121 } 1122 1123 return 0; 1124 } 1125 1126 /* 1127 * Device state switch handlers. 1128 */ 1129 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1130 enum dev_state state) 1131 { 1132 int mask = (state == STATE_RADIO_IRQ_OFF); 1133 u32 reg; 1134 unsigned long flags; 1135 1136 /* 1137 * When interrupts are being enabled, the interrupt registers 1138 * should clear the register to assure a clean state. 1139 */ 1140 if (state == STATE_RADIO_IRQ_ON) { 1141 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); 1142 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); 1143 } 1144 1145 /* 1146 * Only toggle the interrupts bits we are going to use. 1147 * Non-checked interrupt bits are disabled by default. 1148 */ 1149 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); 1150 1151 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); 1152 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); 1153 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); 1154 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); 1155 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); 1156 rt2x00_set_field32(®, CSR8_RXDONE, mask); 1157 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1158 1159 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); 1160 1161 if (state == STATE_RADIO_IRQ_OFF) { 1162 /* 1163 * Ensure that all tasklets are finished. 1164 */ 1165 tasklet_kill(&rt2x00dev->txstatus_tasklet); 1166 tasklet_kill(&rt2x00dev->rxdone_tasklet); 1167 tasklet_kill(&rt2x00dev->tbtt_tasklet); 1168 } 1169 } 1170 1171 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1172 { 1173 /* 1174 * Initialize all registers. 1175 */ 1176 if (unlikely(rt2500pci_init_queues(rt2x00dev) || 1177 rt2500pci_init_registers(rt2x00dev) || 1178 rt2500pci_init_bbp(rt2x00dev))) 1179 return -EIO; 1180 1181 return 0; 1182 } 1183 1184 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev) 1185 { 1186 /* 1187 * Disable power 1188 */ 1189 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); 1190 } 1191 1192 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, 1193 enum dev_state state) 1194 { 1195 u32 reg, reg2; 1196 unsigned int i; 1197 char put_to_sleep; 1198 char bbp_state; 1199 char rf_state; 1200 1201 put_to_sleep = (state != STATE_AWAKE); 1202 1203 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®); 1204 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); 1205 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); 1206 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); 1207 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); 1208 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); 1209 1210 /* 1211 * Device is not guaranteed to be in the requested state yet. 1212 * We must wait until the register indicates that the 1213 * device has entered the correct state. 1214 */ 1215 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1216 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, ®2); 1217 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); 1218 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); 1219 if (bbp_state == state && rf_state == state) 1220 return 0; 1221 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); 1222 msleep(10); 1223 } 1224 1225 return -EBUSY; 1226 } 1227 1228 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, 1229 enum dev_state state) 1230 { 1231 int retval = 0; 1232 1233 switch (state) { 1234 case STATE_RADIO_ON: 1235 retval = rt2500pci_enable_radio(rt2x00dev); 1236 break; 1237 case STATE_RADIO_OFF: 1238 rt2500pci_disable_radio(rt2x00dev); 1239 break; 1240 case STATE_RADIO_IRQ_ON: 1241 case STATE_RADIO_IRQ_OFF: 1242 rt2500pci_toggle_irq(rt2x00dev, state); 1243 break; 1244 case STATE_DEEP_SLEEP: 1245 case STATE_SLEEP: 1246 case STATE_STANDBY: 1247 case STATE_AWAKE: 1248 retval = rt2500pci_set_state(rt2x00dev, state); 1249 break; 1250 default: 1251 retval = -ENOTSUPP; 1252 break; 1253 } 1254 1255 if (unlikely(retval)) 1256 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", 1257 state, retval); 1258 1259 return retval; 1260 } 1261 1262 /* 1263 * TX descriptor initialization 1264 */ 1265 static void rt2500pci_write_tx_desc(struct queue_entry *entry, 1266 struct txentry_desc *txdesc) 1267 { 1268 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1269 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1270 __le32 *txd = entry_priv->desc; 1271 u32 word; 1272 1273 /* 1274 * Start writing the descriptor words. 1275 */ 1276 rt2x00_desc_read(txd, 1, &word); 1277 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1278 rt2x00_desc_write(txd, 1, word); 1279 1280 rt2x00_desc_read(txd, 2, &word); 1281 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1282 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs); 1283 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min); 1284 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max); 1285 rt2x00_desc_write(txd, 2, word); 1286 1287 rt2x00_desc_read(txd, 3, &word); 1288 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); 1289 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); 1290 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, 1291 txdesc->u.plcp.length_low); 1292 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, 1293 txdesc->u.plcp.length_high); 1294 rt2x00_desc_write(txd, 3, word); 1295 1296 rt2x00_desc_read(txd, 10, &word); 1297 rt2x00_set_field32(&word, TXD_W10_RTS, 1298 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1299 rt2x00_desc_write(txd, 10, word); 1300 1301 /* 1302 * Writing TXD word 0 must the last to prevent a race condition with 1303 * the device, whereby the device may take hold of the TXD before we 1304 * finished updating it. 1305 */ 1306 rt2x00_desc_read(txd, 0, &word); 1307 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1308 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1309 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1310 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1311 rt2x00_set_field32(&word, TXD_W0_ACK, 1312 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 1313 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1314 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1315 rt2x00_set_field32(&word, TXD_W0_OFDM, 1316 (txdesc->rate_mode == RATE_MODE_OFDM)); 1317 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1318 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); 1319 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1320 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1321 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1322 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1323 rt2x00_desc_write(txd, 0, word); 1324 1325 /* 1326 * Register descriptor details in skb frame descriptor. 1327 */ 1328 skbdesc->desc = txd; 1329 skbdesc->desc_len = TXD_DESC_SIZE; 1330 } 1331 1332 /* 1333 * TX data initialization 1334 */ 1335 static void rt2500pci_write_beacon(struct queue_entry *entry, 1336 struct txentry_desc *txdesc) 1337 { 1338 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1339 u32 reg; 1340 1341 /* 1342 * Disable beaconing while we are reloading the beacon data, 1343 * otherwise we might be sending out invalid data. 1344 */ 1345 rt2x00mmio_register_read(rt2x00dev, CSR14, ®); 1346 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); 1347 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 1348 1349 if (rt2x00queue_map_txskb(entry)) { 1350 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); 1351 goto out; 1352 } 1353 1354 /* 1355 * Write the TX descriptor for the beacon. 1356 */ 1357 rt2500pci_write_tx_desc(entry, txdesc); 1358 1359 /* 1360 * Dump beacon to userspace through debugfs. 1361 */ 1362 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1363 out: 1364 /* 1365 * Enable beaconing again. 1366 */ 1367 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); 1368 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); 1369 } 1370 1371 /* 1372 * RX control handlers 1373 */ 1374 static void rt2500pci_fill_rxdone(struct queue_entry *entry, 1375 struct rxdone_entry_desc *rxdesc) 1376 { 1377 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; 1378 u32 word0; 1379 u32 word2; 1380 1381 rt2x00_desc_read(entry_priv->desc, 0, &word0); 1382 rt2x00_desc_read(entry_priv->desc, 2, &word2); 1383 1384 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1385 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1386 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1387 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; 1388 1389 /* 1390 * Obtain the status about this packet. 1391 * When frame was received with an OFDM bitrate, 1392 * the signal is the PLCP value. If it was received with 1393 * a CCK bitrate the signal is the rate in 100kbit/s. 1394 */ 1395 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); 1396 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - 1397 entry->queue->rt2x00dev->rssi_offset; 1398 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1399 1400 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1401 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1402 else 1403 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; 1404 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1405 rxdesc->dev_flags |= RXDONE_MY_BSS; 1406 } 1407 1408 /* 1409 * Interrupt functions. 1410 */ 1411 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1412 const enum data_queue_qid queue_idx) 1413 { 1414 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 1415 struct queue_entry_priv_mmio *entry_priv; 1416 struct queue_entry *entry; 1417 struct txdone_entry_desc txdesc; 1418 u32 word; 1419 1420 while (!rt2x00queue_empty(queue)) { 1421 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1422 entry_priv = entry->priv_data; 1423 rt2x00_desc_read(entry_priv->desc, 0, &word); 1424 1425 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1426 !rt2x00_get_field32(word, TXD_W0_VALID)) 1427 break; 1428 1429 /* 1430 * Obtain the status about this packet. 1431 */ 1432 txdesc.flags = 0; 1433 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { 1434 case 0: /* Success */ 1435 case 1: /* Success with retry */ 1436 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1437 break; 1438 case 2: /* Failure, excessive retries */ 1439 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); 1440 /* Don't break, this is a failed frame! */ 1441 default: /* Failure */ 1442 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1443 } 1444 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1445 1446 rt2x00lib_txdone(entry, &txdesc); 1447 } 1448 } 1449 1450 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, 1451 struct rt2x00_field32 irq_field) 1452 { 1453 u32 reg; 1454 1455 /* 1456 * Enable a single interrupt. The interrupt mask register 1457 * access needs locking. 1458 */ 1459 spin_lock_irq(&rt2x00dev->irqmask_lock); 1460 1461 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); 1462 rt2x00_set_field32(®, irq_field, 0); 1463 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1464 1465 spin_unlock_irq(&rt2x00dev->irqmask_lock); 1466 } 1467 1468 static void rt2500pci_txstatus_tasklet(unsigned long data) 1469 { 1470 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 1471 u32 reg; 1472 1473 /* 1474 * Handle all tx queues. 1475 */ 1476 rt2500pci_txdone(rt2x00dev, QID_ATIM); 1477 rt2500pci_txdone(rt2x00dev, QID_AC_VO); 1478 rt2500pci_txdone(rt2x00dev, QID_AC_VI); 1479 1480 /* 1481 * Enable all TXDONE interrupts again. 1482 */ 1483 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { 1484 spin_lock_irq(&rt2x00dev->irqmask_lock); 1485 1486 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); 1487 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); 1488 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); 1489 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); 1490 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1491 1492 spin_unlock_irq(&rt2x00dev->irqmask_lock); 1493 } 1494 } 1495 1496 static void rt2500pci_tbtt_tasklet(unsigned long data) 1497 { 1498 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 1499 rt2x00lib_beacondone(rt2x00dev); 1500 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1501 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); 1502 } 1503 1504 static void rt2500pci_rxdone_tasklet(unsigned long data) 1505 { 1506 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 1507 if (rt2x00mmio_rxdone(rt2x00dev)) 1508 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 1509 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1510 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); 1511 } 1512 1513 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) 1514 { 1515 struct rt2x00_dev *rt2x00dev = dev_instance; 1516 u32 reg, mask; 1517 1518 /* 1519 * Get the interrupt sources & saved to local variable. 1520 * Write register value back to clear pending interrupts. 1521 */ 1522 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); 1523 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); 1524 1525 if (!reg) 1526 return IRQ_NONE; 1527 1528 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1529 return IRQ_HANDLED; 1530 1531 mask = reg; 1532 1533 /* 1534 * Schedule tasklets for interrupt handling. 1535 */ 1536 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) 1537 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); 1538 1539 if (rt2x00_get_field32(reg, CSR7_RXDONE)) 1540 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 1541 1542 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || 1543 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || 1544 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { 1545 tasklet_schedule(&rt2x00dev->txstatus_tasklet); 1546 /* 1547 * Mask out all txdone interrupts. 1548 */ 1549 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); 1550 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); 1551 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); 1552 } 1553 1554 /* 1555 * Disable all interrupts for which a tasklet was scheduled right now, 1556 * the tasklet will reenable the appropriate interrupts. 1557 */ 1558 spin_lock(&rt2x00dev->irqmask_lock); 1559 1560 rt2x00mmio_register_read(rt2x00dev, CSR8, ®); 1561 reg |= mask; 1562 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); 1563 1564 spin_unlock(&rt2x00dev->irqmask_lock); 1565 1566 return IRQ_HANDLED; 1567 } 1568 1569 /* 1570 * Device probe functions. 1571 */ 1572 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) 1573 { 1574 struct eeprom_93cx6 eeprom; 1575 u32 reg; 1576 u16 word; 1577 u8 *mac; 1578 1579 rt2x00mmio_register_read(rt2x00dev, CSR21, ®); 1580 1581 eeprom.data = rt2x00dev; 1582 eeprom.register_read = rt2500pci_eepromregister_read; 1583 eeprom.register_write = rt2500pci_eepromregister_write; 1584 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? 1585 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; 1586 eeprom.reg_data_in = 0; 1587 eeprom.reg_data_out = 0; 1588 eeprom.reg_data_clock = 0; 1589 eeprom.reg_chip_select = 0; 1590 1591 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, 1592 EEPROM_SIZE / sizeof(u16)); 1593 1594 /* 1595 * Start validation of the data that has been read. 1596 */ 1597 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 1598 rt2x00lib_set_mac_address(rt2x00dev, mac); 1599 1600 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 1601 if (word == 0xffff) { 1602 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); 1603 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 1604 ANTENNA_SW_DIVERSITY); 1605 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 1606 ANTENNA_SW_DIVERSITY); 1607 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 1608 LED_MODE_DEFAULT); 1609 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); 1610 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); 1611 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522); 1612 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); 1613 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 1614 } 1615 1616 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); 1617 if (word == 0xffff) { 1618 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); 1619 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0); 1620 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0); 1621 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); 1622 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 1623 } 1624 1625 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word); 1626 if (word == 0xffff) { 1627 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI, 1628 DEFAULT_RSSI_OFFSET); 1629 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word); 1630 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n", 1631 word); 1632 } 1633 1634 return 0; 1635 } 1636 1637 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev) 1638 { 1639 u32 reg; 1640 u16 value; 1641 u16 eeprom; 1642 1643 /* 1644 * Read EEPROM word for configuration. 1645 */ 1646 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); 1647 1648 /* 1649 * Identify RF chipset. 1650 */ 1651 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1652 rt2x00mmio_register_read(rt2x00dev, CSR0, ®); 1653 rt2x00_set_chip(rt2x00dev, RT2560, value, 1654 rt2x00_get_field32(reg, CSR0_REVISION)); 1655 1656 if (!rt2x00_rf(rt2x00dev, RF2522) && 1657 !rt2x00_rf(rt2x00dev, RF2523) && 1658 !rt2x00_rf(rt2x00dev, RF2524) && 1659 !rt2x00_rf(rt2x00dev, RF2525) && 1660 !rt2x00_rf(rt2x00dev, RF2525E) && 1661 !rt2x00_rf(rt2x00dev, RF5222)) { 1662 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); 1663 return -ENODEV; 1664 } 1665 1666 /* 1667 * Identify default antenna configuration. 1668 */ 1669 rt2x00dev->default_ant.tx = 1670 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); 1671 rt2x00dev->default_ant.rx = 1672 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); 1673 1674 /* 1675 * Store led mode, for correct led behaviour. 1676 */ 1677 #ifdef CONFIG_RT2X00_LIB_LEDS 1678 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1679 1680 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 1681 if (value == LED_MODE_TXRX_ACTIVITY || 1682 value == LED_MODE_DEFAULT || 1683 value == LED_MODE_ASUS) 1684 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual, 1685 LED_TYPE_ACTIVITY); 1686 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1687 1688 /* 1689 * Detect if this device has an hardware controlled radio. 1690 */ 1691 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) { 1692 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 1693 /* 1694 * On this device RFKILL initialized during probe does not work. 1695 */ 1696 __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags); 1697 } 1698 1699 /* 1700 * Check if the BBP tuning should be enabled. 1701 */ 1702 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); 1703 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) 1704 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 1705 1706 /* 1707 * Read the RSSI <-> dBm offset information. 1708 */ 1709 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom); 1710 rt2x00dev->rssi_offset = 1711 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI); 1712 1713 return 0; 1714 } 1715 1716 /* 1717 * RF value list for RF2522 1718 * Supports: 2.4 GHz 1719 */ 1720 static const struct rf_channel rf_vals_bg_2522[] = { 1721 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 }, 1722 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 }, 1723 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 }, 1724 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 }, 1725 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 }, 1726 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 }, 1727 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 }, 1728 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 }, 1729 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 }, 1730 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 }, 1731 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 }, 1732 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 }, 1733 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 }, 1734 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 }, 1735 }; 1736 1737 /* 1738 * RF value list for RF2523 1739 * Supports: 2.4 GHz 1740 */ 1741 static const struct rf_channel rf_vals_bg_2523[] = { 1742 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b }, 1743 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b }, 1744 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b }, 1745 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b }, 1746 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b }, 1747 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b }, 1748 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b }, 1749 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b }, 1750 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b }, 1751 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b }, 1752 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b }, 1753 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b }, 1754 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b }, 1755 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 }, 1756 }; 1757 1758 /* 1759 * RF value list for RF2524 1760 * Supports: 2.4 GHz 1761 */ 1762 static const struct rf_channel rf_vals_bg_2524[] = { 1763 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b }, 1764 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b }, 1765 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b }, 1766 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b }, 1767 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b }, 1768 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b }, 1769 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b }, 1770 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b }, 1771 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b }, 1772 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b }, 1773 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b }, 1774 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b }, 1775 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b }, 1776 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 }, 1777 }; 1778 1779 /* 1780 * RF value list for RF2525 1781 * Supports: 2.4 GHz 1782 */ 1783 static const struct rf_channel rf_vals_bg_2525[] = { 1784 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b }, 1785 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b }, 1786 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b }, 1787 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b }, 1788 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b }, 1789 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b }, 1790 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b }, 1791 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b }, 1792 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b }, 1793 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b }, 1794 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b }, 1795 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b }, 1796 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b }, 1797 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 }, 1798 }; 1799 1800 /* 1801 * RF value list for RF2525e 1802 * Supports: 2.4 GHz 1803 */ 1804 static const struct rf_channel rf_vals_bg_2525e[] = { 1805 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b }, 1806 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b }, 1807 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b }, 1808 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b }, 1809 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b }, 1810 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b }, 1811 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b }, 1812 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b }, 1813 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b }, 1814 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b }, 1815 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b }, 1816 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b }, 1817 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b }, 1818 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b }, 1819 }; 1820 1821 /* 1822 * RF value list for RF5222 1823 * Supports: 2.4 GHz & 5.2 GHz 1824 */ 1825 static const struct rf_channel rf_vals_5222[] = { 1826 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b }, 1827 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b }, 1828 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b }, 1829 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b }, 1830 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b }, 1831 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b }, 1832 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b }, 1833 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b }, 1834 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b }, 1835 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b }, 1836 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b }, 1837 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b }, 1838 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b }, 1839 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b }, 1840 1841 /* 802.11 UNI / HyperLan 2 */ 1842 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f }, 1843 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f }, 1844 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f }, 1845 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f }, 1846 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f }, 1847 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f }, 1848 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f }, 1849 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f }, 1850 1851 /* 802.11 HyperLan 2 */ 1852 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f }, 1853 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f }, 1854 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f }, 1855 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f }, 1856 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f }, 1857 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f }, 1858 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f }, 1859 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f }, 1860 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f }, 1861 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f }, 1862 1863 /* 802.11 UNII */ 1864 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f }, 1865 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 }, 1866 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 }, 1867 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 }, 1868 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 }, 1869 }; 1870 1871 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 1872 { 1873 struct hw_mode_spec *spec = &rt2x00dev->spec; 1874 struct channel_info *info; 1875 char *tx_power; 1876 unsigned int i; 1877 1878 /* 1879 * Initialize all hw fields. 1880 */ 1881 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 1882 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 1883 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 1884 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 1885 1886 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 1887 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1888 rt2x00_eeprom_addr(rt2x00dev, 1889 EEPROM_MAC_ADDR_0)); 1890 1891 /* 1892 * Disable powersaving as default. 1893 */ 1894 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 1895 1896 /* 1897 * Initialize hw_mode information. 1898 */ 1899 spec->supported_bands = SUPPORT_BAND_2GHZ; 1900 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 1901 1902 if (rt2x00_rf(rt2x00dev, RF2522)) { 1903 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); 1904 spec->channels = rf_vals_bg_2522; 1905 } else if (rt2x00_rf(rt2x00dev, RF2523)) { 1906 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); 1907 spec->channels = rf_vals_bg_2523; 1908 } else if (rt2x00_rf(rt2x00dev, RF2524)) { 1909 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); 1910 spec->channels = rf_vals_bg_2524; 1911 } else if (rt2x00_rf(rt2x00dev, RF2525)) { 1912 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); 1913 spec->channels = rf_vals_bg_2525; 1914 } else if (rt2x00_rf(rt2x00dev, RF2525E)) { 1915 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); 1916 spec->channels = rf_vals_bg_2525e; 1917 } else if (rt2x00_rf(rt2x00dev, RF5222)) { 1918 spec->supported_bands |= SUPPORT_BAND_5GHZ; 1919 spec->num_channels = ARRAY_SIZE(rf_vals_5222); 1920 spec->channels = rf_vals_5222; 1921 } 1922 1923 /* 1924 * Create channel information array 1925 */ 1926 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 1927 if (!info) 1928 return -ENOMEM; 1929 1930 spec->channels_info = info; 1931 1932 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); 1933 for (i = 0; i < 14; i++) { 1934 info[i].max_power = MAX_TXPOWER; 1935 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); 1936 } 1937 1938 if (spec->num_channels > 14) { 1939 for (i = 14; i < spec->num_channels; i++) { 1940 info[i].max_power = MAX_TXPOWER; 1941 info[i].default_power1 = DEFAULT_TXPOWER; 1942 } 1943 } 1944 1945 return 0; 1946 } 1947 1948 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1949 { 1950 int retval; 1951 u32 reg; 1952 1953 /* 1954 * Allocate eeprom data. 1955 */ 1956 retval = rt2500pci_validate_eeprom(rt2x00dev); 1957 if (retval) 1958 return retval; 1959 1960 retval = rt2500pci_init_eeprom(rt2x00dev); 1961 if (retval) 1962 return retval; 1963 1964 /* 1965 * Enable rfkill polling by setting GPIO direction of the 1966 * rfkill switch GPIO pin correctly. 1967 */ 1968 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, ®); 1969 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); 1970 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); 1971 1972 /* 1973 * Initialize hw specifications. 1974 */ 1975 retval = rt2500pci_probe_hw_mode(rt2x00dev); 1976 if (retval) 1977 return retval; 1978 1979 /* 1980 * This device requires the atim queue and DMA-mapped skbs. 1981 */ 1982 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); 1983 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 1984 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); 1985 1986 /* 1987 * Set the rssi offset. 1988 */ 1989 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 1990 1991 return 0; 1992 } 1993 1994 /* 1995 * IEEE80211 stack callback functions. 1996 */ 1997 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw, 1998 struct ieee80211_vif *vif) 1999 { 2000 struct rt2x00_dev *rt2x00dev = hw->priv; 2001 u64 tsf; 2002 u32 reg; 2003 2004 rt2x00mmio_register_read(rt2x00dev, CSR17, ®); 2005 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; 2006 rt2x00mmio_register_read(rt2x00dev, CSR16, ®); 2007 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); 2008 2009 return tsf; 2010 } 2011 2012 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) 2013 { 2014 struct rt2x00_dev *rt2x00dev = hw->priv; 2015 u32 reg; 2016 2017 rt2x00mmio_register_read(rt2x00dev, CSR15, ®); 2018 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); 2019 } 2020 2021 static const struct ieee80211_ops rt2500pci_mac80211_ops = { 2022 .tx = rt2x00mac_tx, 2023 .start = rt2x00mac_start, 2024 .stop = rt2x00mac_stop, 2025 .add_interface = rt2x00mac_add_interface, 2026 .remove_interface = rt2x00mac_remove_interface, 2027 .config = rt2x00mac_config, 2028 .configure_filter = rt2x00mac_configure_filter, 2029 .sw_scan_start = rt2x00mac_sw_scan_start, 2030 .sw_scan_complete = rt2x00mac_sw_scan_complete, 2031 .get_stats = rt2x00mac_get_stats, 2032 .bss_info_changed = rt2x00mac_bss_info_changed, 2033 .conf_tx = rt2x00mac_conf_tx, 2034 .get_tsf = rt2500pci_get_tsf, 2035 .tx_last_beacon = rt2500pci_tx_last_beacon, 2036 .rfkill_poll = rt2x00mac_rfkill_poll, 2037 .flush = rt2x00mac_flush, 2038 .set_antenna = rt2x00mac_set_antenna, 2039 .get_antenna = rt2x00mac_get_antenna, 2040 .get_ringparam = rt2x00mac_get_ringparam, 2041 .tx_frames_pending = rt2x00mac_tx_frames_pending, 2042 }; 2043 2044 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { 2045 .irq_handler = rt2500pci_interrupt, 2046 .txstatus_tasklet = rt2500pci_txstatus_tasklet, 2047 .tbtt_tasklet = rt2500pci_tbtt_tasklet, 2048 .rxdone_tasklet = rt2500pci_rxdone_tasklet, 2049 .probe_hw = rt2500pci_probe_hw, 2050 .initialize = rt2x00mmio_initialize, 2051 .uninitialize = rt2x00mmio_uninitialize, 2052 .get_entry_state = rt2500pci_get_entry_state, 2053 .clear_entry = rt2500pci_clear_entry, 2054 .set_device_state = rt2500pci_set_device_state, 2055 .rfkill_poll = rt2500pci_rfkill_poll, 2056 .link_stats = rt2500pci_link_stats, 2057 .reset_tuner = rt2500pci_reset_tuner, 2058 .link_tuner = rt2500pci_link_tuner, 2059 .start_queue = rt2500pci_start_queue, 2060 .kick_queue = rt2500pci_kick_queue, 2061 .stop_queue = rt2500pci_stop_queue, 2062 .flush_queue = rt2x00mmio_flush_queue, 2063 .write_tx_desc = rt2500pci_write_tx_desc, 2064 .write_beacon = rt2500pci_write_beacon, 2065 .fill_rxdone = rt2500pci_fill_rxdone, 2066 .config_filter = rt2500pci_config_filter, 2067 .config_intf = rt2500pci_config_intf, 2068 .config_erp = rt2500pci_config_erp, 2069 .config_ant = rt2500pci_config_ant, 2070 .config = rt2500pci_config, 2071 }; 2072 2073 static void rt2500pci_queue_init(struct data_queue *queue) 2074 { 2075 switch (queue->qid) { 2076 case QID_RX: 2077 queue->limit = 32; 2078 queue->data_size = DATA_FRAME_SIZE; 2079 queue->desc_size = RXD_DESC_SIZE; 2080 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2081 break; 2082 2083 case QID_AC_VO: 2084 case QID_AC_VI: 2085 case QID_AC_BE: 2086 case QID_AC_BK: 2087 queue->limit = 32; 2088 queue->data_size = DATA_FRAME_SIZE; 2089 queue->desc_size = TXD_DESC_SIZE; 2090 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2091 break; 2092 2093 case QID_BEACON: 2094 queue->limit = 1; 2095 queue->data_size = MGMT_FRAME_SIZE; 2096 queue->desc_size = TXD_DESC_SIZE; 2097 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2098 break; 2099 2100 case QID_ATIM: 2101 queue->limit = 8; 2102 queue->data_size = DATA_FRAME_SIZE; 2103 queue->desc_size = TXD_DESC_SIZE; 2104 queue->priv_size = sizeof(struct queue_entry_priv_mmio); 2105 break; 2106 2107 default: 2108 BUG(); 2109 break; 2110 } 2111 } 2112 2113 static const struct rt2x00_ops rt2500pci_ops = { 2114 .name = KBUILD_MODNAME, 2115 .max_ap_intf = 1, 2116 .eeprom_size = EEPROM_SIZE, 2117 .rf_size = RF_SIZE, 2118 .tx_queues = NUM_TX_QUEUES, 2119 .queue_init = rt2500pci_queue_init, 2120 .lib = &rt2500pci_rt2x00_ops, 2121 .hw = &rt2500pci_mac80211_ops, 2122 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 2123 .debugfs = &rt2500pci_rt2x00debug, 2124 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 2125 }; 2126 2127 /* 2128 * RT2500pci module information. 2129 */ 2130 static const struct pci_device_id rt2500pci_device_table[] = { 2131 { PCI_DEVICE(0x1814, 0x0201) }, 2132 { 0, } 2133 }; 2134 2135 MODULE_AUTHOR(DRV_PROJECT); 2136 MODULE_VERSION(DRV_VERSION); 2137 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver."); 2138 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards"); 2139 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); 2140 MODULE_LICENSE("GPL"); 2141 2142 static int rt2500pci_probe(struct pci_dev *pci_dev, 2143 const struct pci_device_id *id) 2144 { 2145 return rt2x00pci_probe(pci_dev, &rt2500pci_ops); 2146 } 2147 2148 static struct pci_driver rt2500pci_driver = { 2149 .name = KBUILD_MODNAME, 2150 .id_table = rt2500pci_device_table, 2151 .probe = rt2500pci_probe, 2152 .remove = rt2x00pci_remove, 2153 .suspend = rt2x00pci_suspend, 2154 .resume = rt2x00pci_resume, 2155 }; 2156 2157 module_pci_driver(rt2500pci_driver); 2158