12ef0ecd7SIgor Mitsyanko /* 22ef0ecd7SIgor Mitsyanko * Copyright (c) 2015-2016 Quantenna Communications, Inc. 32ef0ecd7SIgor Mitsyanko * All rights reserved. 42ef0ecd7SIgor Mitsyanko * 52ef0ecd7SIgor Mitsyanko * This program is free software; you can redistribute it and/or 62ef0ecd7SIgor Mitsyanko * modify it under the terms of the GNU General Public License 72ef0ecd7SIgor Mitsyanko * as published by the Free Software Foundation; either version 2 82ef0ecd7SIgor Mitsyanko * of the License, or (at your option) any later version. 92ef0ecd7SIgor Mitsyanko * 102ef0ecd7SIgor Mitsyanko * This program is distributed in the hope that it will be useful, 112ef0ecd7SIgor Mitsyanko * but WITHOUT ANY WARRANTY; without even the implied warranty of 122ef0ecd7SIgor Mitsyanko * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 132ef0ecd7SIgor Mitsyanko * GNU General Public License for more details. 142ef0ecd7SIgor Mitsyanko * 152ef0ecd7SIgor Mitsyanko */ 162ef0ecd7SIgor Mitsyanko 172ef0ecd7SIgor Mitsyanko #ifndef _QTN_FMAC_PCIE_IPC_H_ 182ef0ecd7SIgor Mitsyanko #define _QTN_FMAC_PCIE_IPC_H_ 192ef0ecd7SIgor Mitsyanko 202ef0ecd7SIgor Mitsyanko #include <linux/types.h> 212ef0ecd7SIgor Mitsyanko 222ef0ecd7SIgor Mitsyanko #include "shm_ipc_defs.h" 232ef0ecd7SIgor Mitsyanko 242ef0ecd7SIgor Mitsyanko /* bitmap for EP status and flags: updated by EP, read by RC */ 252ef0ecd7SIgor Mitsyanko #define QTN_EP_HAS_UBOOT BIT(0) 262ef0ecd7SIgor Mitsyanko #define QTN_EP_HAS_FIRMWARE BIT(1) 272ef0ecd7SIgor Mitsyanko #define QTN_EP_REQ_UBOOT BIT(2) 282ef0ecd7SIgor Mitsyanko #define QTN_EP_REQ_FIRMWARE BIT(3) 292ef0ecd7SIgor Mitsyanko #define QTN_EP_ERROR_UBOOT BIT(4) 302ef0ecd7SIgor Mitsyanko #define QTN_EP_ERROR_FIRMWARE BIT(5) 312ef0ecd7SIgor Mitsyanko 322ef0ecd7SIgor Mitsyanko #define QTN_EP_FW_LOADRDY BIT(8) 332ef0ecd7SIgor Mitsyanko #define QTN_EP_FW_SYNC BIT(9) 342ef0ecd7SIgor Mitsyanko #define QTN_EP_FW_RETRY BIT(10) 352ef0ecd7SIgor Mitsyanko #define QTN_EP_FW_QLINK_DONE BIT(15) 362ef0ecd7SIgor Mitsyanko #define QTN_EP_FW_DONE BIT(16) 372ef0ecd7SIgor Mitsyanko 382ef0ecd7SIgor Mitsyanko /* bitmap for RC status and flags: updated by RC, read by EP */ 392ef0ecd7SIgor Mitsyanko #define QTN_RC_PCIE_LINK BIT(0) 402ef0ecd7SIgor Mitsyanko #define QTN_RC_NET_LINK BIT(1) 412ef0ecd7SIgor Mitsyanko #define QTN_RC_FW_FLASHBOOT BIT(5) 422ef0ecd7SIgor Mitsyanko #define QTN_RC_FW_QLINK BIT(7) 432ef0ecd7SIgor Mitsyanko #define QTN_RC_FW_LOADRDY BIT(8) 442ef0ecd7SIgor Mitsyanko #define QTN_RC_FW_SYNC BIT(9) 452ef0ecd7SIgor Mitsyanko 462ef0ecd7SIgor Mitsyanko /* state transition timeouts */ 472ef0ecd7SIgor Mitsyanko #define QTN_FW_DL_TIMEOUT_MS 3000 482ef0ecd7SIgor Mitsyanko #define QTN_FW_QLINK_TIMEOUT_MS 30000 492ef0ecd7SIgor Mitsyanko #define QTN_EP_RESET_WAIT_MS 1000 502ef0ecd7SIgor Mitsyanko 512ef0ecd7SIgor Mitsyanko #define PCIE_HDP_INT_RX_BITS (0 \ 522ef0ecd7SIgor Mitsyanko | PCIE_HDP_INT_EP_TXDMA \ 532ef0ecd7SIgor Mitsyanko | PCIE_HDP_INT_EP_TXEMPTY \ 542ef0ecd7SIgor Mitsyanko | PCIE_HDP_INT_HHBM_UF \ 552ef0ecd7SIgor Mitsyanko ) 562ef0ecd7SIgor Mitsyanko 572ef0ecd7SIgor Mitsyanko #define PCIE_HDP_INT_TX_BITS (0 \ 582ef0ecd7SIgor Mitsyanko | PCIE_HDP_INT_EP_RXDMA \ 592ef0ecd7SIgor Mitsyanko ) 602ef0ecd7SIgor Mitsyanko 612ef0ecd7SIgor Mitsyanko #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 622ef0ecd7SIgor Mitsyanko #define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32)) 632ef0ecd7SIgor Mitsyanko #define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL)) 642ef0ecd7SIgor Mitsyanko #define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l)) 652ef0ecd7SIgor Mitsyanko #else 662ef0ecd7SIgor Mitsyanko #define QTN_HOST_HI32(a) 0 672ef0ecd7SIgor Mitsyanko #define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL)) 682ef0ecd7SIgor Mitsyanko #define QTN_HOST_ADDR(h, l) ((u32)l) 692ef0ecd7SIgor Mitsyanko #endif 702ef0ecd7SIgor Mitsyanko 712ef0ecd7SIgor Mitsyanko #define QTN_SYSCTL_BAR 0 722ef0ecd7SIgor Mitsyanko #define QTN_SHMEM_BAR 2 732ef0ecd7SIgor Mitsyanko #define QTN_DMA_BAR 3 742ef0ecd7SIgor Mitsyanko 752ef0ecd7SIgor Mitsyanko #define QTN_PCIE_BDA_VERSION 0x1002 762ef0ecd7SIgor Mitsyanko 772ef0ecd7SIgor Mitsyanko #define PCIE_BDA_NAMELEN 32 782ef0ecd7SIgor Mitsyanko #define PCIE_HHBM_MAX_SIZE 2048 792ef0ecd7SIgor Mitsyanko 802ef0ecd7SIgor Mitsyanko #define SKB_BUF_SIZE 2048 812ef0ecd7SIgor Mitsyanko 822ef0ecd7SIgor Mitsyanko #define QTN_PCIE_BOARDFLG "PCIEQTN" 832ef0ecd7SIgor Mitsyanko #define QTN_PCIE_FW_DLMASK 0xF 842ef0ecd7SIgor Mitsyanko #define QTN_PCIE_FW_BUFSZ 2048 852ef0ecd7SIgor Mitsyanko 862ef0ecd7SIgor Mitsyanko #define QTN_ENET_ADDR_LENGTH 6 872ef0ecd7SIgor Mitsyanko 882ef0ecd7SIgor Mitsyanko #define QTN_TXDONE_MASK ((u32)0x80000000) 892ef0ecd7SIgor Mitsyanko #define QTN_GET_LEN(x) ((x) & 0xFFFF) 902ef0ecd7SIgor Mitsyanko 912ef0ecd7SIgor Mitsyanko #define QTN_PCIE_TX_DESC_LEN_MASK 0xFFFF 922ef0ecd7SIgor Mitsyanko #define QTN_PCIE_TX_DESC_LEN_SHIFT 0 932ef0ecd7SIgor Mitsyanko #define QTN_PCIE_TX_DESC_PORT_MASK 0xF 942ef0ecd7SIgor Mitsyanko #define QTN_PCIE_TX_DESC_PORT_SHIFT 16 952ef0ecd7SIgor Mitsyanko #define QTN_PCIE_TX_DESC_TQE_BIT BIT(24) 962ef0ecd7SIgor Mitsyanko 972ef0ecd7SIgor Mitsyanko #define QTN_EP_LHOST_TQE_PORT 4 982ef0ecd7SIgor Mitsyanko 992ef0ecd7SIgor Mitsyanko enum qtnf_pcie_bda_ipc_flags { 1002ef0ecd7SIgor Mitsyanko QTN_PCIE_IPC_FLAG_HBM_MAGIC = BIT(0), 1012ef0ecd7SIgor Mitsyanko QTN_PCIE_IPC_FLAG_SHM_PIO = BIT(1), 1022ef0ecd7SIgor Mitsyanko }; 1032ef0ecd7SIgor Mitsyanko 1042ef0ecd7SIgor Mitsyanko struct qtnf_pcie_bda { 1052ef0ecd7SIgor Mitsyanko __le16 bda_len; 1062ef0ecd7SIgor Mitsyanko __le16 bda_version; 1072ef0ecd7SIgor Mitsyanko __le32 bda_pci_endian; 1082ef0ecd7SIgor Mitsyanko __le32 bda_ep_state; 1092ef0ecd7SIgor Mitsyanko __le32 bda_rc_state; 1102ef0ecd7SIgor Mitsyanko __le32 bda_dma_mask; 1112ef0ecd7SIgor Mitsyanko __le32 bda_msi_addr; 1122ef0ecd7SIgor Mitsyanko __le32 bda_flashsz; 1132ef0ecd7SIgor Mitsyanko u8 bda_boardname[PCIE_BDA_NAMELEN]; 1142ef0ecd7SIgor Mitsyanko __le32 bda_rc_msi_enabled; 1152ef0ecd7SIgor Mitsyanko u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE]; 1162ef0ecd7SIgor Mitsyanko __le32 bda_dsbw_start_index; 1172ef0ecd7SIgor Mitsyanko __le32 bda_dsbw_end_index; 1182ef0ecd7SIgor Mitsyanko __le32 bda_dsbw_total_bytes; 1192ef0ecd7SIgor Mitsyanko __le32 bda_rc_tx_bd_base; 1202ef0ecd7SIgor Mitsyanko __le32 bda_rc_tx_bd_num; 1212ef0ecd7SIgor Mitsyanko u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH]; 1222ef0ecd7SIgor Mitsyanko struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */ 1232ef0ecd7SIgor Mitsyanko struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */ 1242ef0ecd7SIgor Mitsyanko } __packed; 1252ef0ecd7SIgor Mitsyanko 1262ef0ecd7SIgor Mitsyanko struct qtnf_tx_bd { 1272ef0ecd7SIgor Mitsyanko __le32 addr; 1282ef0ecd7SIgor Mitsyanko __le32 addr_h; 1292ef0ecd7SIgor Mitsyanko __le32 info; 1302ef0ecd7SIgor Mitsyanko __le32 info_h; 1312ef0ecd7SIgor Mitsyanko } __packed; 1322ef0ecd7SIgor Mitsyanko 1332ef0ecd7SIgor Mitsyanko struct qtnf_rx_bd { 1342ef0ecd7SIgor Mitsyanko __le32 addr; 1352ef0ecd7SIgor Mitsyanko __le32 addr_h; 1362ef0ecd7SIgor Mitsyanko __le32 info; 1372ef0ecd7SIgor Mitsyanko __le32 info_h; 1382ef0ecd7SIgor Mitsyanko __le32 next_ptr; 1392ef0ecd7SIgor Mitsyanko __le32 next_ptr_h; 1402ef0ecd7SIgor Mitsyanko } __packed; 1412ef0ecd7SIgor Mitsyanko 1422ef0ecd7SIgor Mitsyanko enum qtnf_fw_loadtype { 1432ef0ecd7SIgor Mitsyanko QTN_FW_DBEGIN, 1442ef0ecd7SIgor Mitsyanko QTN_FW_DSUB, 1452ef0ecd7SIgor Mitsyanko QTN_FW_DEND, 1462ef0ecd7SIgor Mitsyanko QTN_FW_CTRL 1472ef0ecd7SIgor Mitsyanko }; 1482ef0ecd7SIgor Mitsyanko 1492ef0ecd7SIgor Mitsyanko struct qtnf_pcie_fw_hdr { 1502ef0ecd7SIgor Mitsyanko u8 boardflg[8]; 1512ef0ecd7SIgor Mitsyanko __le32 fwsize; 1522ef0ecd7SIgor Mitsyanko __le32 seqnum; 1532ef0ecd7SIgor Mitsyanko __le32 type; 1542ef0ecd7SIgor Mitsyanko __le32 pktlen; 1552ef0ecd7SIgor Mitsyanko __le32 crc; 1562ef0ecd7SIgor Mitsyanko } __packed; 1572ef0ecd7SIgor Mitsyanko 1582ef0ecd7SIgor Mitsyanko #endif /* _QTN_FMAC_PCIE_IPC_H_ */ 159