1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */ 3 4 #ifndef _QTN_FMAC_PCIE_H_ 5 #define _QTN_FMAC_PCIE_H_ 6 7 #include <linux/pci.h> 8 #include <linux/spinlock.h> 9 #include <linux/io.h> 10 #include <linux/skbuff.h> 11 #include <linux/workqueue.h> 12 #include <linux/interrupt.h> 13 14 #include "shm_ipc.h" 15 #include "bus.h" 16 17 #define SKB_BUF_SIZE 2048 18 19 #define QTN_FW_DL_TIMEOUT_MS 3000 20 #define QTN_FW_QLINK_TIMEOUT_MS 30000 21 #define QTN_EP_RESET_WAIT_MS 1000 22 23 struct qtnf_pcie_bus_priv { 24 struct pci_dev *pdev; 25 26 spinlock_t tx_reclaim_lock; 27 spinlock_t tx_lock; 28 int mps; 29 30 struct workqueue_struct *workqueue; 31 struct tasklet_struct reclaim_tq; 32 33 void __iomem *sysctl_bar; 34 void __iomem *epmem_bar; 35 void __iomem *dmareg_bar; 36 37 struct qtnf_shm_ipc shm_ipc_ep_in; 38 struct qtnf_shm_ipc shm_ipc_ep_out; 39 40 u16 tx_bd_num; 41 u16 rx_bd_num; 42 43 struct sk_buff **tx_skb; 44 struct sk_buff **rx_skb; 45 46 u32 rx_bd_w_index; 47 u32 rx_bd_r_index; 48 49 u32 tx_bd_w_index; 50 u32 tx_bd_r_index; 51 52 /* diagnostics stats */ 53 u32 pcie_irq_count; 54 u32 tx_full_count; 55 u32 tx_done_count; 56 u32 tx_reclaim_done; 57 u32 tx_reclaim_req; 58 59 u8 msi_enabled; 60 u8 tx_stopped; 61 }; 62 63 int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb); 64 int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv); 65 void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus); 66 void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success, 67 const char *drv_name); 68 void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv, 69 struct qtnf_shm_ipc_region __iomem *ipc_tx_reg, 70 struct qtnf_shm_ipc_region __iomem *ipc_rx_reg, 71 const struct qtnf_shm_ipc_int *ipc_int); 72 int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size, 73 const struct qtnf_bus_ops *bus_ops, u64 dma_mask, 74 bool use_msi); 75 void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *priv); 76 77 static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg) 78 { 79 writel(val, basereg); 80 81 /* flush posted write */ 82 readl(basereg); 83 } 84 85 #endif /* _QTN_FMAC_PCIE_H_ */ 86