1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */
3 
4 #include <linux/module.h>
5 #include <linux/printk.h>
6 #include <linux/pci.h>
7 #include <linux/spinlock.h>
8 #include <linux/mutex.h>
9 #include <linux/netdevice.h>
10 #include <linux/seq_file.h>
11 #include <linux/workqueue.h>
12 #include <linux/completion.h>
13 
14 #include "pcie_priv.h"
15 #include "bus.h"
16 #include "shm_ipc.h"
17 #include "core.h"
18 #include "debug.h"
19 #include "util.h"
20 #include "qtn_hw_ids.h"
21 
22 #define QTN_SYSCTL_BAR	0
23 #define QTN_SHMEM_BAR	2
24 #define QTN_DMA_BAR	3
25 
26 #define QTN_PCIE_MAX_FW_BUFSZ		(1 * 1024 * 1024)
27 
28 static bool use_msi = true;
29 module_param(use_msi, bool, 0644);
30 MODULE_PARM_DESC(use_msi, "set 0 to use legacy interrupt");
31 
32 static unsigned int tx_bd_size_param;
33 module_param(tx_bd_size_param, uint, 0644);
34 MODULE_PARM_DESC(tx_bd_size_param, "Tx descriptors queue size");
35 
36 static unsigned int rx_bd_size_param = 256;
37 module_param(rx_bd_size_param, uint, 0644);
38 MODULE_PARM_DESC(rx_bd_size_param, "Rx descriptors queue size");
39 
40 static u8 flashboot = 1;
41 module_param(flashboot, byte, 0644);
42 MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary file on FS");
43 
44 static unsigned int fw_blksize_param = QTN_PCIE_MAX_FW_BUFSZ;
45 module_param(fw_blksize_param, uint, 0644);
46 MODULE_PARM_DESC(fw_blksize_param, "firmware loading block size in bytes");
47 
48 #define DRV_NAME	"qtnfmac_pcie"
49 
50 int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb)
51 {
52 	struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
53 	int ret;
54 
55 	ret = qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len);
56 
57 	if (ret == -ETIMEDOUT) {
58 		pr_err("EP firmware is dead\n");
59 		bus->fw_state = QTNF_FW_STATE_EP_DEAD;
60 	}
61 
62 	return ret;
63 }
64 
65 int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv)
66 {
67 	struct sk_buff **vaddr;
68 	int len;
69 
70 	len = priv->tx_bd_num * sizeof(*priv->tx_skb) +
71 		priv->rx_bd_num * sizeof(*priv->rx_skb);
72 	vaddr = devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL);
73 
74 	if (!vaddr)
75 		return -ENOMEM;
76 
77 	priv->tx_skb = vaddr;
78 
79 	vaddr += priv->tx_bd_num;
80 	priv->rx_skb = vaddr;
81 
82 	return 0;
83 }
84 
85 static void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus)
86 {
87 	struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
88 	struct pci_dev *pdev = priv->pdev;
89 
90 	get_device(&pdev->dev);
91 	schedule_work(&bus->fw_work);
92 }
93 
94 static int qtnf_dbg_mps_show(struct seq_file *s, void *data)
95 {
96 	struct qtnf_bus *bus = dev_get_drvdata(s->private);
97 	struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
98 
99 	seq_printf(s, "%d\n", pcie_get_mps(priv->pdev));
100 
101 	return 0;
102 }
103 
104 static int qtnf_dbg_msi_show(struct seq_file *s, void *data)
105 {
106 	struct qtnf_bus *bus = dev_get_drvdata(s->private);
107 	struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
108 
109 	seq_printf(s, "%u\n", priv->msi_enabled);
110 
111 	return 0;
112 }
113 
114 static int qtnf_dbg_shm_stats(struct seq_file *s, void *data)
115 {
116 	struct qtnf_bus *bus = dev_get_drvdata(s->private);
117 	struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
118 
119 	seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n",
120 		   priv->shm_ipc_ep_in.tx_packet_count);
121 	seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n",
122 		   priv->shm_ipc_ep_in.rx_packet_count);
123 	seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n",
124 		   priv->shm_ipc_ep_out.tx_timeout_count);
125 	seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n",
126 		   priv->shm_ipc_ep_out.rx_packet_count);
127 
128 	return 0;
129 }
130 
131 void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success)
132 {
133 	struct qtnf_pcie_bus_priv *priv = get_bus_priv(bus);
134 	struct pci_dev *pdev = priv->pdev;
135 	int ret;
136 
137 	if (boot_success) {
138 		bus->fw_state = QTNF_FW_STATE_FW_DNLD_DONE;
139 
140 		ret = qtnf_core_attach(bus);
141 		if (ret) {
142 			pr_err("failed to attach core\n");
143 			boot_success = false;
144 		}
145 	}
146 
147 	if (boot_success) {
148 		qtnf_debugfs_init(bus, DRV_NAME);
149 		qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show);
150 		qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show);
151 		qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats);
152 	} else {
153 		bus->fw_state = QTNF_FW_STATE_DETACHED;
154 	}
155 
156 	put_device(&pdev->dev);
157 }
158 
159 static void qtnf_tune_pcie_mps(struct pci_dev *pdev)
160 {
161 	struct pci_dev *parent;
162 	int mps_p, mps_o, mps_m, mps;
163 	int ret;
164 
165 	/* current mps */
166 	mps_o = pcie_get_mps(pdev);
167 
168 	/* maximum supported mps */
169 	mps_m = 128 << pdev->pcie_mpss;
170 
171 	/* suggested new mps value */
172 	mps = mps_m;
173 
174 	if (pdev->bus && pdev->bus->self) {
175 		/* parent (bus) mps */
176 		parent = pdev->bus->self;
177 
178 		if (pci_is_pcie(parent)) {
179 			mps_p = pcie_get_mps(parent);
180 			mps = min(mps_m, mps_p);
181 		}
182 	}
183 
184 	ret = pcie_set_mps(pdev, mps);
185 	if (ret) {
186 		pr_err("failed to set mps to %d, keep using current %d\n",
187 		       mps, mps_o);
188 		return;
189 	}
190 
191 	pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m);
192 }
193 
194 static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv, bool use_msi)
195 {
196 	struct pci_dev *pdev = priv->pdev;
197 
198 	/* fall back to legacy INTx interrupts by default */
199 	priv->msi_enabled = 0;
200 
201 	/* check if MSI capability is available */
202 	if (use_msi) {
203 		if (!pci_enable_msi(pdev)) {
204 			pr_debug("enabled MSI interrupt\n");
205 			priv->msi_enabled = 1;
206 		} else {
207 			pr_warn("failed to enable MSI interrupts");
208 		}
209 	}
210 
211 	if (!priv->msi_enabled) {
212 		pr_warn("legacy PCIE interrupts enabled\n");
213 		pci_intx(pdev, 1);
214 	}
215 }
216 
217 static void __iomem *qtnf_map_bar(struct pci_dev *pdev, u8 index)
218 {
219 	void __iomem *vaddr;
220 	dma_addr_t busaddr;
221 	size_t len;
222 	int ret;
223 
224 	ret = pcim_iomap_regions(pdev, 1 << index, "qtnfmac_pcie");
225 	if (ret)
226 		return IOMEM_ERR_PTR(ret);
227 
228 	busaddr = pci_resource_start(pdev, index);
229 	len = pci_resource_len(pdev, index);
230 	vaddr = pcim_iomap_table(pdev)[index];
231 	if (!vaddr)
232 		return IOMEM_ERR_PTR(-ENOMEM);
233 
234 	pr_debug("BAR%u vaddr=0x%p busaddr=%pad len=%u\n",
235 		 index, vaddr, &busaddr, (int)len);
236 
237 	return vaddr;
238 }
239 
240 static void qtnf_pcie_control_rx_callback(void *arg, const u8 __iomem *buf,
241 					  size_t len)
242 {
243 	struct qtnf_pcie_bus_priv *priv = arg;
244 	struct qtnf_bus *bus = pci_get_drvdata(priv->pdev);
245 	struct sk_buff *skb;
246 
247 	if (unlikely(len == 0)) {
248 		pr_warn("zero length packet received\n");
249 		return;
250 	}
251 
252 	skb = __dev_alloc_skb(len, GFP_KERNEL);
253 
254 	if (unlikely(!skb)) {
255 		pr_err("failed to allocate skb\n");
256 		return;
257 	}
258 
259 	memcpy_fromio(skb_put(skb, len), buf, len);
260 
261 	qtnf_trans_handle_rx_ctl_packet(bus, skb);
262 }
263 
264 void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
265 			    struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
266 			    struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
267 			    const struct qtnf_shm_ipc_int *ipc_int)
268 {
269 	const struct qtnf_shm_ipc_rx_callback rx_callback = {
270 					qtnf_pcie_control_rx_callback, priv };
271 
272 	qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND,
273 			  ipc_tx_reg, priv->workqueue,
274 			  ipc_int, &rx_callback);
275 	qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND,
276 			  ipc_rx_reg, priv->workqueue,
277 			  ipc_int, &rx_callback);
278 }
279 
280 static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
281 {
282 	struct qtnf_pcie_bus_priv *pcie_priv;
283 	struct qtnf_bus *bus;
284 	void __iomem *sysctl_bar;
285 	void __iomem *epmem_bar;
286 	void __iomem *dmareg_bar;
287 	unsigned int chipid;
288 	int ret;
289 
290 	if (!pci_is_pcie(pdev)) {
291 		pr_err("device %s is not PCI Express\n", pci_name(pdev));
292 		return -EIO;
293 	}
294 
295 	qtnf_tune_pcie_mps(pdev);
296 
297 	ret = pcim_enable_device(pdev);
298 	if (ret) {
299 		pr_err("failed to init PCI device %x\n", pdev->device);
300 		return ret;
301 	}
302 
303 	pci_set_master(pdev);
304 
305 	sysctl_bar = qtnf_map_bar(pdev, QTN_SYSCTL_BAR);
306 	if (IS_ERR(sysctl_bar)) {
307 		pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR);
308 		return ret;
309 	}
310 
311 	dmareg_bar = qtnf_map_bar(pdev, QTN_DMA_BAR);
312 	if (IS_ERR(dmareg_bar)) {
313 		pr_err("failed to map BAR%u\n", QTN_DMA_BAR);
314 		return ret;
315 	}
316 
317 	epmem_bar = qtnf_map_bar(pdev, QTN_SHMEM_BAR);
318 	if (IS_ERR(epmem_bar)) {
319 		pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR);
320 		return ret;
321 	}
322 
323 	chipid = qtnf_chip_id_get(sysctl_bar);
324 
325 	pr_info("identified device: %s\n", qtnf_chipid_to_string(chipid));
326 
327 	switch (chipid) {
328 	case QTN_CHIP_ID_PEARL:
329 	case QTN_CHIP_ID_PEARL_B:
330 	case QTN_CHIP_ID_PEARL_C:
331 		bus = qtnf_pcie_pearl_alloc(pdev);
332 		break;
333 	case QTN_CHIP_ID_TOPAZ:
334 		bus = qtnf_pcie_topaz_alloc(pdev);
335 		break;
336 	default:
337 		pr_err("unsupported chip ID 0x%x\n", chipid);
338 		return -ENOTSUPP;
339 	}
340 
341 	if (!bus)
342 		return -ENOMEM;
343 
344 	pcie_priv = get_bus_priv(bus);
345 	pci_set_drvdata(pdev, bus);
346 	bus->dev = &pdev->dev;
347 	bus->fw_state = QTNF_FW_STATE_RESET;
348 	pcie_priv->pdev = pdev;
349 	pcie_priv->tx_stopped = 0;
350 	pcie_priv->rx_bd_num = rx_bd_size_param;
351 	pcie_priv->flashboot = flashboot;
352 
353 	if (fw_blksize_param > QTN_PCIE_MAX_FW_BUFSZ)
354 		pcie_priv->fw_blksize =  QTN_PCIE_MAX_FW_BUFSZ;
355 	else
356 		pcie_priv->fw_blksize = fw_blksize_param;
357 
358 	mutex_init(&bus->bus_lock);
359 	spin_lock_init(&pcie_priv->tx_lock);
360 	spin_lock_init(&pcie_priv->tx_reclaim_lock);
361 
362 	pcie_priv->tx_full_count = 0;
363 	pcie_priv->tx_done_count = 0;
364 	pcie_priv->pcie_irq_count = 0;
365 	pcie_priv->tx_reclaim_done = 0;
366 	pcie_priv->tx_reclaim_req = 0;
367 
368 	pcie_priv->workqueue = create_singlethread_workqueue("QTNF_PCIE");
369 	if (!pcie_priv->workqueue) {
370 		pr_err("failed to alloc bus workqueue\n");
371 		return -ENODEV;
372 	}
373 
374 	ret = dma_set_mask_and_coherent(&pdev->dev,
375 					pcie_priv->dma_mask_get_cb());
376 	if (ret) {
377 		pr_err("PCIE DMA coherent mask init failed 0x%llx\n",
378 		       pcie_priv->dma_mask_get_cb());
379 		goto error;
380 	}
381 
382 	init_dummy_netdev(&bus->mux_dev);
383 	qtnf_pcie_init_irq(pcie_priv, use_msi);
384 	pcie_priv->sysctl_bar = sysctl_bar;
385 	pcie_priv->dmareg_bar = dmareg_bar;
386 	pcie_priv->epmem_bar = epmem_bar;
387 	pci_save_state(pdev);
388 
389 	ret = pcie_priv->probe_cb(bus, tx_bd_size_param);
390 	if (ret)
391 		goto error;
392 
393 	qtnf_pcie_bringup_fw_async(bus);
394 	return 0;
395 
396 error:
397 	flush_workqueue(pcie_priv->workqueue);
398 	destroy_workqueue(pcie_priv->workqueue);
399 	pci_set_drvdata(pdev, NULL);
400 	return ret;
401 }
402 
403 static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv)
404 {
405 	qtnf_shm_ipc_free(&priv->shm_ipc_ep_in);
406 	qtnf_shm_ipc_free(&priv->shm_ipc_ep_out);
407 }
408 
409 static void qtnf_pcie_remove(struct pci_dev *dev)
410 {
411 	struct qtnf_pcie_bus_priv *priv;
412 	struct qtnf_bus *bus;
413 
414 	bus = pci_get_drvdata(dev);
415 	if (!bus)
416 		return;
417 
418 	priv = get_bus_priv(bus);
419 
420 	cancel_work_sync(&bus->fw_work);
421 
422 	if (bus->fw_state == QTNF_FW_STATE_ACTIVE ||
423 	    bus->fw_state == QTNF_FW_STATE_EP_DEAD)
424 		qtnf_core_detach(bus);
425 
426 	netif_napi_del(&bus->mux_napi);
427 	flush_workqueue(priv->workqueue);
428 	destroy_workqueue(priv->workqueue);
429 	tasklet_kill(&priv->reclaim_tq);
430 
431 	qtnf_pcie_free_shm_ipc(priv);
432 	qtnf_debugfs_remove(bus);
433 	priv->remove_cb(bus);
434 	pci_set_drvdata(priv->pdev, NULL);
435 }
436 
437 #ifdef CONFIG_PM_SLEEP
438 static int qtnf_pcie_suspend(struct device *dev)
439 {
440 	struct qtnf_pcie_bus_priv *priv;
441 	struct qtnf_bus *bus;
442 
443 	bus = pci_get_drvdata(to_pci_dev(dev));
444 	if (!bus)
445 		return -EFAULT;
446 
447 	priv = get_bus_priv(bus);
448 	return priv->suspend_cb(bus);
449 }
450 
451 static int qtnf_pcie_resume(struct device *dev)
452 {
453 	struct qtnf_pcie_bus_priv *priv;
454 	struct qtnf_bus *bus;
455 
456 	bus = pci_get_drvdata(to_pci_dev(dev));
457 	if (!bus)
458 		return -EFAULT;
459 
460 	priv = get_bus_priv(bus);
461 	return priv->resume_cb(bus);
462 }
463 
464 /* Power Management Hooks */
465 static SIMPLE_DEV_PM_OPS(qtnf_pcie_pm_ops, qtnf_pcie_suspend,
466 			 qtnf_pcie_resume);
467 #endif
468 
469 static const struct pci_device_id qtnf_pcie_devid_table[] = {
470 	{
471 		PCIE_VENDOR_ID_QUANTENNA, PCIE_DEVICE_ID_QSR,
472 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
473 	},
474 	{ },
475 };
476 
477 MODULE_DEVICE_TABLE(pci, qtnf_pcie_devid_table);
478 
479 static struct pci_driver qtnf_pcie_drv_data = {
480 	.name = DRV_NAME,
481 	.id_table = qtnf_pcie_devid_table,
482 	.probe = qtnf_pcie_probe,
483 	.remove = qtnf_pcie_remove,
484 #ifdef CONFIG_PM_SLEEP
485 	.driver = {
486 		.pm = &qtnf_pcie_pm_ops,
487 	},
488 #endif
489 };
490 
491 static int __init qtnf_pcie_register(void)
492 {
493 	return pci_register_driver(&qtnf_pcie_drv_data);
494 }
495 
496 static void __exit qtnf_pcie_exit(void)
497 {
498 	pci_unregister_driver(&qtnf_pcie_drv_data);
499 }
500 
501 module_init(qtnf_pcie_register);
502 module_exit(qtnf_pcie_exit);
503 
504 MODULE_AUTHOR("Quantenna Communications");
505 MODULE_DESCRIPTION("Quantenna PCIe bus driver for 802.11 wireless LAN.");
506 MODULE_LICENSE("GPL");
507