1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4  * All rights reserved.
5  */
6 
7 #ifndef WILC_WLAN_H
8 #define WILC_WLAN_H
9 
10 #include <linux/types.h>
11 #include <linux/bitfield.h>
12 
13 /********************************************
14  *
15  *      Mac eth header length
16  *
17  ********************************************/
18 #define MAX_MAC_HDR_LEN			26 /* QOS_MAC_HDR_LEN */
19 #define SUB_MSDU_HEADER_LENGTH		14
20 #define SNAP_HDR_LEN			8
21 #define ETHERNET_HDR_LEN		14
22 #define WORD_ALIGNMENT_PAD		0
23 
24 #define ETH_ETHERNET_HDR_OFFSET		(MAX_MAC_HDR_LEN + \
25 					 SUB_MSDU_HEADER_LENGTH + \
26 					 SNAP_HDR_LEN - \
27 					 ETHERNET_HDR_LEN + \
28 					 WORD_ALIGNMENT_PAD)
29 
30 #define HOST_HDR_OFFSET			4
31 #define ETHERNET_HDR_LEN		14
32 #define IP_HDR_LEN			20
33 #define IP_HDR_OFFSET			ETHERNET_HDR_LEN
34 #define UDP_HDR_OFFSET			(IP_HDR_LEN + IP_HDR_OFFSET)
35 #define UDP_HDR_LEN			8
36 #define UDP_DATA_OFFSET			(UDP_HDR_OFFSET + UDP_HDR_LEN)
37 #define ETH_CONFIG_PKT_HDR_LEN		UDP_DATA_OFFSET
38 
39 #define ETH_CONFIG_PKT_HDR_OFFSET	(ETH_ETHERNET_HDR_OFFSET + \
40 					 ETH_CONFIG_PKT_HDR_LEN)
41 
42 /********************************************
43  *
44  *      Register Defines
45  *
46  ********************************************/
47 #define WILC_PERIPH_REG_BASE		0x1000
48 #define WILC_CHANGING_VIR_IF		0x108c
49 #define WILC_CHIPID			WILC_PERIPH_REG_BASE
50 #define WILC_GLB_RESET_0		(WILC_PERIPH_REG_BASE + 0x400)
51 #define WILC_PIN_MUX_0			(WILC_PERIPH_REG_BASE + 0x408)
52 #define WILC_HOST_TX_CTRL		(WILC_PERIPH_REG_BASE + 0x6c)
53 #define WILC_HOST_RX_CTRL_0		(WILC_PERIPH_REG_BASE + 0x70)
54 #define WILC_HOST_RX_CTRL_1		(WILC_PERIPH_REG_BASE + 0x74)
55 #define WILC_HOST_VMM_CTL		(WILC_PERIPH_REG_BASE + 0x78)
56 #define WILC_HOST_RX_CTRL		(WILC_PERIPH_REG_BASE + 0x80)
57 #define WILC_HOST_RX_EXTRA_SIZE		(WILC_PERIPH_REG_BASE + 0x84)
58 #define WILC_HOST_TX_CTRL_1		(WILC_PERIPH_REG_BASE + 0x88)
59 #define WILC_MISC			(WILC_PERIPH_REG_BASE + 0x428)
60 #define WILC_INTR_REG_BASE		(WILC_PERIPH_REG_BASE + 0xa00)
61 #define WILC_INTR_ENABLE		WILC_INTR_REG_BASE
62 #define WILC_INTR2_ENABLE		(WILC_INTR_REG_BASE + 4)
63 
64 #define WILC_INTR_POLARITY		(WILC_INTR_REG_BASE + 0x10)
65 #define WILC_INTR_TYPE			(WILC_INTR_REG_BASE + 0x20)
66 #define WILC_INTR_CLEAR			(WILC_INTR_REG_BASE + 0x30)
67 #define WILC_INTR_STATUS		(WILC_INTR_REG_BASE + 0x40)
68 
69 #define WILC_RF_REVISION_ID		0x13f4
70 
71 #define WILC_VMM_TBL_SIZE		64
72 #define WILC_VMM_TX_TBL_BASE		0x150400
73 #define WILC_VMM_RX_TBL_BASE		0x150500
74 
75 #define WILC_VMM_BASE			0x150000
76 #define WILC_VMM_CORE_CTL		WILC_VMM_BASE
77 #define WILC_VMM_TBL_CTL		(WILC_VMM_BASE + 0x4)
78 #define WILC_VMM_TBL_ENTRY		(WILC_VMM_BASE + 0x8)
79 #define WILC_VMM_TBL0_SIZE		(WILC_VMM_BASE + 0xc)
80 #define WILC_VMM_TO_HOST_SIZE		(WILC_VMM_BASE + 0x10)
81 #define WILC_VMM_CORE_CFG		(WILC_VMM_BASE + 0x14)
82 #define WILC_VMM_TBL_ACTIVE		(WILC_VMM_BASE + 040)
83 #define WILC_VMM_TBL_STATUS		(WILC_VMM_BASE + 0x44)
84 
85 #define WILC_SPI_REG_BASE		0xe800
86 #define WILC_SPI_CTL			WILC_SPI_REG_BASE
87 #define WILC_SPI_MASTER_DMA_ADDR	(WILC_SPI_REG_BASE + 0x4)
88 #define WILC_SPI_MASTER_DMA_COUNT	(WILC_SPI_REG_BASE + 0x8)
89 #define WILC_SPI_SLAVE_DMA_ADDR		(WILC_SPI_REG_BASE + 0xc)
90 #define WILC_SPI_SLAVE_DMA_COUNT	(WILC_SPI_REG_BASE + 0x10)
91 #define WILC_SPI_TX_MODE		(WILC_SPI_REG_BASE + 0x20)
92 #define WILC_SPI_PROTOCOL_CONFIG	(WILC_SPI_REG_BASE + 0x24)
93 #define WILC_SPI_INTR_CTL		(WILC_SPI_REG_BASE + 0x2c)
94 #define WILC_SPI_INT_STATUS		(WILC_SPI_REG_BASE + 0x40)
95 #define WILC_SPI_INT_CLEAR		(WILC_SPI_REG_BASE + 0x44)
96 
97 #define WILC_SPI_WAKEUP_REG		0x1
98 #define WILC_SPI_WAKEUP_BIT		BIT(1)
99 
100 #define WILC_SPI_PROTOCOL_OFFSET	(WILC_SPI_PROTOCOL_CONFIG - \
101 					 WILC_SPI_REG_BASE)
102 
103 #define WILC_SPI_CLOCKLESS_ADDR_LIMIT	0x30
104 
105 /* Functions IO enables bits */
106 #define WILC_SDIO_CCCR_IO_EN_FUNC1	BIT(1)
107 
108 /* Function/Interrupt enables bits */
109 #define WILC_SDIO_CCCR_IEN_MASTER	BIT(0)
110 #define WILC_SDIO_CCCR_IEN_FUNC1	BIT(1)
111 
112 /* Abort CCCR register bits */
113 #define WILC_SDIO_CCCR_ABORT_RESET	BIT(3)
114 
115 /* Vendor specific CCCR registers */
116 #define WILC_SDIO_WAKEUP_REG		0xf0
117 #define WILC_SDIO_WAKEUP_BIT		BIT(0)
118 
119 #define WILC_SDIO_CLK_STATUS_REG	0xf1
120 #define WILC_SDIO_CLK_STATUS_BIT	BIT(0)
121 
122 #define WILC_SDIO_INTERRUPT_DATA_SZ_REG	0xf2 /* Read size (2 bytes) */
123 
124 #define WILC_SDIO_VMM_TBL_CTRL_REG	0xf6
125 #define WILC_SDIO_IRQ_FLAG_REG		0xf7
126 #define WILC_SDIO_IRQ_CLEAR_FLAG_REG	0xf8
127 
128 #define WILC_SDIO_HOST_TO_FW_REG	0xfa
129 #define WILC_SDIO_HOST_TO_FW_BIT	BIT(0)
130 
131 #define WILC_SDIO_FW_TO_HOST_REG	0xfc
132 #define WILC_SDIO_FW_TO_HOST_BIT	BIT(0)
133 
134 /* Function 1 specific FBR register */
135 #define WILC_SDIO_FBR_CSA_REG		0x10C /* CSA pointer (3 bytes) */
136 #define WILC_SDIO_FBR_DATA_REG		0x10F
137 
138 #define WILC_SDIO_F1_DATA_REG		0x0
139 #define WILC_SDIO_EXT_IRQ_FLAG_REG	0x4
140 
141 #define WILC_AHB_DATA_MEM_BASE		0x30000
142 #define WILC_AHB_SHARE_MEM_BASE		0xd0000
143 
144 #define WILC_VMM_TBL_RX_SHADOW_BASE	WILC_AHB_SHARE_MEM_BASE
145 #define WILC_VMM_TBL_RX_SHADOW_SIZE	256
146 
147 #define WILC_FW_HOST_COMM		0x13c0
148 #define WILC_GP_REG_0			0x149c
149 #define WILC_GP_REG_1			0x14a0
150 
151 #define WILC_HAVE_SDIO_IRQ_GPIO		BIT(0)
152 #define WILC_HAVE_USE_PMU		BIT(1)
153 #define WILC_HAVE_SLEEP_CLK_SRC_RTC	BIT(2)
154 #define WILC_HAVE_SLEEP_CLK_SRC_XO	BIT(3)
155 #define WILC_HAVE_EXT_PA_INV_TX_RX	BIT(4)
156 #define WILC_HAVE_LEGACY_RF_SETTINGS	BIT(5)
157 #define WILC_HAVE_XTAL_24		BIT(6)
158 #define WILC_HAVE_DISABLE_WILC_UART	BIT(7)
159 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE	BIT(8)
160 
161 #define WILC_CORTUS_INTERRUPT_BASE	0x10A8
162 #define WILC_CORTUS_INTERRUPT_1		(WILC_CORTUS_INTERRUPT_BASE + 0x4)
163 #define WILC_CORTUS_INTERRUPT_2		(WILC_CORTUS_INTERRUPT_BASE + 0x8)
164 
165 /* tx control register 1 to 4 for RX */
166 #define WILC_REG_4_TO_1_RX		0x1e1c
167 
168 /* tx control register 1 to 4 for TX Bank_0 */
169 #define WILC_REG_4_TO_1_TX_BANK0	0x1e9c
170 
171 #define WILC_CORTUS_RESET_MUX_SEL	0x1118
172 #define WILC_CORTUS_BOOT_REGISTER	0xc0000
173 
174 #define WILC_CORTUS_BOOT_FROM_IRAM	0x71
175 
176 #define WILC_1000_BASE_ID		0x100000
177 
178 #define WILC_1000_BASE_ID_2A		0x1002A0
179 #define WILC_1000_BASE_ID_2A_REV1	(WILC_1000_BASE_ID_2A + 1)
180 
181 #define WILC_1000_BASE_ID_2B		0x1002B0
182 #define WILC_1000_BASE_ID_2B_REV1	(WILC_1000_BASE_ID_2B + 1)
183 #define WILC_1000_BASE_ID_2B_REV2	(WILC_1000_BASE_ID_2B + 2)
184 
185 #define WILC_CHIP_REV_FIELD		GENMASK(11, 0)
186 
187 /********************************************
188  *
189  *      Wlan Defines
190  *
191  ********************************************/
192 #define WILC_CFG_PKT		1
193 #define WILC_NET_PKT		0
194 #define WILC_MGMT_PKT		2
195 
196 #define WILC_CFG_SET		1
197 #define WILC_CFG_QUERY		0
198 
199 #define WILC_CFG_RSP		1
200 #define WILC_CFG_RSP_STATUS	2
201 #define WILC_CFG_RSP_SCAN	3
202 
203 #define WILC_ABORT_REQ_BIT		BIT(31)
204 
205 #define WILC_RX_BUFF_SIZE	(96 * 1024)
206 #define WILC_TX_BUFF_SIZE	(64 * 1024)
207 
208 #define MODALIAS		"WILC_SPI"
209 
210 #define NQUEUES			4
211 #define AC_BUFFER_SIZE		1000
212 
213 #define VO_AC_COUNT_FIELD		GENMASK(31, 25)
214 #define VO_AC_ACM_STAT_FIELD		BIT(24)
215 #define VI_AC_COUNT_FIELD		GENMASK(23, 17)
216 #define VI_AC_ACM_STAT_FIELD		BIT(16)
217 #define BE_AC_COUNT_FIELD		GENMASK(15, 9)
218 #define BE_AC_ACM_STAT_FIELD		BIT(8)
219 #define BK_AC_COUNT_FIELD		GENMASK(7, 3)
220 #define BK_AC_ACM_STAT_FIELD		BIT(1)
221 
222 #define WILC_PKT_HDR_CONFIG_FIELD	BIT(31)
223 #define WILC_PKT_HDR_OFFSET_FIELD	GENMASK(30, 22)
224 #define WILC_PKT_HDR_TOTAL_LEN_FIELD	GENMASK(21, 11)
225 #define WILC_PKT_HDR_LEN_FIELD		GENMASK(10, 0)
226 
227 #define WILC_INTERRUPT_DATA_SIZE	GENMASK(14, 0)
228 
229 #define WILC_VMM_BUFFER_SIZE		GENMASK(9, 0)
230 
231 #define WILC_VMM_HDR_TYPE		BIT(31)
232 #define WILC_VMM_HDR_MGMT_FIELD		BIT(30)
233 #define WILC_VMM_HDR_PKT_SIZE		GENMASK(29, 15)
234 #define WILC_VMM_HDR_BUFF_SIZE		GENMASK(14, 0)
235 
236 #define WILC_VMM_ENTRY_COUNT		GENMASK(8, 3)
237 #define WILC_VMM_ENTRY_AVAILABLE	BIT(2)
238 /*******************************************/
239 /*        E0 and later Interrupt flags.    */
240 /*******************************************/
241 /*******************************************/
242 /*        E0 and later Interrupt flags.    */
243 /*           IRQ Status word               */
244 /* 15:0 = DMA count in words.              */
245 /* 16: INT0 flag                           */
246 /* 17: INT1 flag                           */
247 /* 18: INT2 flag                           */
248 /* 19: INT3 flag                           */
249 /* 20: INT4 flag                           */
250 /* 21: INT5 flag                           */
251 /*******************************************/
252 #define IRG_FLAGS_OFFSET	16
253 #define IRQ_DMA_WD_CNT_MASK	GENMASK(IRG_FLAGS_OFFSET - 1, 0)
254 #define INT_0			BIT(IRG_FLAGS_OFFSET)
255 #define INT_1			BIT(IRG_FLAGS_OFFSET + 1)
256 #define INT_2			BIT(IRG_FLAGS_OFFSET + 2)
257 #define INT_3			BIT(IRG_FLAGS_OFFSET + 3)
258 #define INT_4			BIT(IRG_FLAGS_OFFSET + 4)
259 #define INT_5			BIT(IRG_FLAGS_OFFSET + 5)
260 #define MAX_NUM_INT		5
261 #define IRG_FLAGS_MASK		GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
262 					IRG_FLAGS_OFFSET)
263 
264 /*******************************************/
265 /*        E0 and later Interrupt flags.    */
266 /*           IRQ Clear word                */
267 /* 0: Clear INT0                           */
268 /* 1: Clear INT1                           */
269 /* 2: Clear INT2                           */
270 /* 3: Clear INT3                           */
271 /* 4: Clear INT4                           */
272 /* 5: Clear INT5                           */
273 /* 6: Select VMM table 1                   */
274 /* 7: Select VMM table 2                   */
275 /* 8: Enable VMM                           */
276 /*******************************************/
277 #define CLR_INT0		BIT(0)
278 #define CLR_INT1		BIT(1)
279 #define CLR_INT2		BIT(2)
280 #define CLR_INT3		BIT(3)
281 #define CLR_INT4		BIT(4)
282 #define CLR_INT5		BIT(5)
283 #define SEL_VMM_TBL0		BIT(6)
284 #define SEL_VMM_TBL1		BIT(7)
285 #define EN_VMM			BIT(8)
286 
287 #define DATA_INT_EXT		INT_0
288 #define ALL_INT_EXT		DATA_INT_EXT
289 #define NUM_INT_EXT		1
290 #define UNHANDLED_IRQ_MASK	GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
291 
292 #define DATA_INT_CLR		CLR_INT0
293 
294 #define ENABLE_RX_VMM		(SEL_VMM_TBL1 | EN_VMM)
295 #define ENABLE_TX_VMM		(SEL_VMM_TBL0 | EN_VMM)
296 /* time for expiring the completion of cfg packets */
297 #define WILC_CFG_PKTS_TIMEOUT	msecs_to_jiffies(2000)
298 
299 #define IS_MANAGMEMENT		0x100
300 #define IS_MANAGMEMENT_CALLBACK	0x080
301 #define IS_MGMT_STATUS_SUCCES	0x040
302 
303 #define WILC_WID_TYPE		GENMASK(15, 12)
304 #define WILC_VMM_ENTRY_FULL_RETRY	1
305 /********************************************
306  *
307  *      Tx/Rx Queue Structure
308  *
309  ********************************************/
310 enum ip_pkt_priority {
311 	AC_VO_Q = 0,
312 	AC_VI_Q = 1,
313 	AC_BE_Q = 2,
314 	AC_BK_Q = 3
315 };
316 
317 struct txq_entry_t {
318 	struct list_head list;
319 	int type;
320 	u8 q_num;
321 	int ack_idx;
322 	u8 *buffer;
323 	int buffer_size;
324 	void *priv;
325 	int status;
326 	struct wilc_vif *vif;
327 	void (*tx_complete_func)(void *priv, int status);
328 };
329 
330 struct txq_fw_recv_queue_stat {
331 	u8 acm;
332 	u8 count;
333 };
334 
335 struct txq_handle {
336 	struct txq_entry_t txq_head;
337 	u16 count;
338 	struct txq_fw_recv_queue_stat fw;
339 };
340 
341 struct rxq_entry_t {
342 	struct list_head list;
343 	u8 *buffer;
344 	int buffer_size;
345 };
346 
347 /********************************************
348  *
349  *      Host IF Structure
350  *
351  ********************************************/
352 struct wilc;
353 struct wilc_hif_func {
354 	int (*hif_init)(struct wilc *wilc, bool resume);
355 	int (*hif_deinit)(struct wilc *wilc);
356 	int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
357 	int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
358 	int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
359 	int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
360 	int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
361 	int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
362 	int (*hif_read_size)(struct wilc *wilc, u32 *size);
363 	int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
364 	int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
365 	int (*hif_sync_ext)(struct wilc *wilc, int nint);
366 	int (*enable_interrupt)(struct wilc *nic);
367 	void (*disable_interrupt)(struct wilc *nic);
368 };
369 
370 #define WILC_MAX_CFG_FRAME_SIZE		1468
371 
372 struct tx_complete_data {
373 	int size;
374 	void *buff;
375 	struct sk_buff *skb;
376 };
377 
378 struct wilc_cfg_cmd_hdr {
379 	u8 cmd_type;
380 	u8 seq_no;
381 	__le16 total_len;
382 	__le32 driver_handler;
383 };
384 
385 struct wilc_cfg_frame {
386 	struct wilc_cfg_cmd_hdr hdr;
387 	u8 frame[WILC_MAX_CFG_FRAME_SIZE];
388 };
389 
390 struct wilc_cfg_rsp {
391 	u8 type;
392 	u8 seq_no;
393 };
394 
395 struct wilc;
396 struct wilc_vif;
397 
398 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
399 				u32 buffer_size);
400 int wilc_wlan_start(struct wilc *wilc);
401 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
402 int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
403 			      struct tx_complete_data *tx_data, u8 *buffer,
404 			      u32 buffer_size,
405 			      void (*tx_complete_fn)(void *, int));
406 int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
407 void wilc_handle_isr(struct wilc *wilc);
408 void wilc_wlan_cleanup(struct net_device *dev);
409 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
410 		      u32 buffer_size, int commit, u32 drv_handler);
411 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
412 		      u32 drv_handler);
413 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
414 			       u32 buffer_size, void (*func)(void *, int));
415 void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
416 int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
417 netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
418 
419 void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
420 void host_wakeup_notify(struct wilc *wilc);
421 void host_sleep_notify(struct wilc *wilc);
422 void chip_allow_sleep(struct wilc *wilc);
423 void chip_wakeup(struct wilc *wilc);
424 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
425 			 u32 count);
426 int wilc_wlan_init(struct net_device *dev);
427 u32 wilc_get_chipid(struct wilc *wilc, bool update);
428 #endif
429