1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/if_ether.h> 8 #include <linux/ip.h> 9 #include <net/dsfield.h> 10 #include "cfg80211.h" 11 #include "wlan_cfg.h" 12 13 #define WAKE_UP_TRIAL_RETRY 10000 14 15 static inline bool is_wilc1000(u32 id) 16 { 17 return (id & (~WILC_CHIP_REV_FIELD)) == WILC_1000_BASE_ID; 18 } 19 20 static inline void acquire_bus(struct wilc *wilc, enum bus_acquire acquire) 21 { 22 mutex_lock(&wilc->hif_cs); 23 if (acquire == WILC_BUS_ACQUIRE_AND_WAKEUP) 24 chip_wakeup(wilc); 25 } 26 27 static inline void release_bus(struct wilc *wilc, enum bus_release release) 28 { 29 if (release == WILC_BUS_RELEASE_ALLOW_SLEEP) 30 chip_allow_sleep(wilc); 31 mutex_unlock(&wilc->hif_cs); 32 } 33 34 static void wilc_wlan_txq_remove(struct wilc *wilc, u8 q_num, 35 struct txq_entry_t *tqe) 36 { 37 list_del(&tqe->list); 38 wilc->txq_entries -= 1; 39 wilc->txq[q_num].count--; 40 } 41 42 static struct txq_entry_t * 43 wilc_wlan_txq_remove_from_head(struct wilc *wilc, u8 q_num) 44 { 45 struct txq_entry_t *tqe = NULL; 46 unsigned long flags; 47 48 spin_lock_irqsave(&wilc->txq_spinlock, flags); 49 50 if (!list_empty(&wilc->txq[q_num].txq_head.list)) { 51 tqe = list_first_entry(&wilc->txq[q_num].txq_head.list, 52 struct txq_entry_t, list); 53 list_del(&tqe->list); 54 wilc->txq_entries -= 1; 55 wilc->txq[q_num].count--; 56 } 57 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 58 return tqe; 59 } 60 61 static void wilc_wlan_txq_add_to_tail(struct net_device *dev, u8 q_num, 62 struct txq_entry_t *tqe) 63 { 64 unsigned long flags; 65 struct wilc_vif *vif = netdev_priv(dev); 66 struct wilc *wilc = vif->wilc; 67 68 spin_lock_irqsave(&wilc->txq_spinlock, flags); 69 70 list_add_tail(&tqe->list, &wilc->txq[q_num].txq_head.list); 71 wilc->txq_entries += 1; 72 wilc->txq[q_num].count++; 73 74 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 75 76 complete(&wilc->txq_event); 77 } 78 79 static void wilc_wlan_txq_add_to_head(struct wilc_vif *vif, u8 q_num, 80 struct txq_entry_t *tqe) 81 { 82 unsigned long flags; 83 struct wilc *wilc = vif->wilc; 84 85 mutex_lock(&wilc->txq_add_to_head_cs); 86 87 spin_lock_irqsave(&wilc->txq_spinlock, flags); 88 89 list_add(&tqe->list, &wilc->txq[q_num].txq_head.list); 90 wilc->txq_entries += 1; 91 wilc->txq[q_num].count++; 92 93 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 94 mutex_unlock(&wilc->txq_add_to_head_cs); 95 complete(&wilc->txq_event); 96 } 97 98 #define NOT_TCP_ACK (-1) 99 100 static inline void add_tcp_session(struct wilc_vif *vif, u32 src_prt, 101 u32 dst_prt, u32 seq) 102 { 103 struct tcp_ack_filter *f = &vif->ack_filter; 104 105 if (f->tcp_session < 2 * MAX_TCP_SESSION) { 106 f->ack_session_info[f->tcp_session].seq_num = seq; 107 f->ack_session_info[f->tcp_session].bigger_ack_num = 0; 108 f->ack_session_info[f->tcp_session].src_port = src_prt; 109 f->ack_session_info[f->tcp_session].dst_port = dst_prt; 110 f->tcp_session++; 111 } 112 } 113 114 static inline void update_tcp_session(struct wilc_vif *vif, u32 index, u32 ack) 115 { 116 struct tcp_ack_filter *f = &vif->ack_filter; 117 118 if (index < 2 * MAX_TCP_SESSION && 119 ack > f->ack_session_info[index].bigger_ack_num) 120 f->ack_session_info[index].bigger_ack_num = ack; 121 } 122 123 static inline void add_tcp_pending_ack(struct wilc_vif *vif, u32 ack, 124 u32 session_index, 125 struct txq_entry_t *txqe) 126 { 127 struct tcp_ack_filter *f = &vif->ack_filter; 128 u32 i = f->pending_base + f->pending_acks_idx; 129 130 if (i < MAX_PENDING_ACKS) { 131 f->pending_acks[i].ack_num = ack; 132 f->pending_acks[i].txqe = txqe; 133 f->pending_acks[i].session_index = session_index; 134 txqe->ack_idx = i; 135 f->pending_acks_idx++; 136 } 137 } 138 139 static inline void tcp_process(struct net_device *dev, struct txq_entry_t *tqe) 140 { 141 void *buffer = tqe->buffer; 142 const struct ethhdr *eth_hdr_ptr = buffer; 143 int i; 144 unsigned long flags; 145 struct wilc_vif *vif = netdev_priv(dev); 146 struct wilc *wilc = vif->wilc; 147 struct tcp_ack_filter *f = &vif->ack_filter; 148 const struct iphdr *ip_hdr_ptr; 149 const struct tcphdr *tcp_hdr_ptr; 150 u32 ihl, total_length, data_offset; 151 152 spin_lock_irqsave(&wilc->txq_spinlock, flags); 153 154 if (eth_hdr_ptr->h_proto != htons(ETH_P_IP)) 155 goto out; 156 157 ip_hdr_ptr = buffer + ETH_HLEN; 158 159 if (ip_hdr_ptr->protocol != IPPROTO_TCP) 160 goto out; 161 162 ihl = ip_hdr_ptr->ihl << 2; 163 tcp_hdr_ptr = buffer + ETH_HLEN + ihl; 164 total_length = ntohs(ip_hdr_ptr->tot_len); 165 166 data_offset = tcp_hdr_ptr->doff << 2; 167 if (total_length == (ihl + data_offset)) { 168 u32 seq_no, ack_no; 169 170 seq_no = ntohl(tcp_hdr_ptr->seq); 171 ack_no = ntohl(tcp_hdr_ptr->ack_seq); 172 for (i = 0; i < f->tcp_session; i++) { 173 u32 j = f->ack_session_info[i].seq_num; 174 175 if (i < 2 * MAX_TCP_SESSION && 176 j == seq_no) { 177 update_tcp_session(vif, i, ack_no); 178 break; 179 } 180 } 181 if (i == f->tcp_session) 182 add_tcp_session(vif, 0, 0, seq_no); 183 184 add_tcp_pending_ack(vif, ack_no, i, tqe); 185 } 186 187 out: 188 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 189 } 190 191 static void wilc_wlan_txq_filter_dup_tcp_ack(struct net_device *dev) 192 { 193 struct wilc_vif *vif = netdev_priv(dev); 194 struct wilc *wilc = vif->wilc; 195 struct tcp_ack_filter *f = &vif->ack_filter; 196 u32 i = 0; 197 u32 dropped = 0; 198 unsigned long flags; 199 200 spin_lock_irqsave(&wilc->txq_spinlock, flags); 201 for (i = f->pending_base; 202 i < (f->pending_base + f->pending_acks_idx); i++) { 203 u32 index; 204 u32 bigger_ack_num; 205 206 if (i >= MAX_PENDING_ACKS) 207 break; 208 209 index = f->pending_acks[i].session_index; 210 211 if (index >= 2 * MAX_TCP_SESSION) 212 break; 213 214 bigger_ack_num = f->ack_session_info[index].bigger_ack_num; 215 216 if (f->pending_acks[i].ack_num < bigger_ack_num) { 217 struct txq_entry_t *tqe; 218 219 tqe = f->pending_acks[i].txqe; 220 if (tqe) { 221 wilc_wlan_txq_remove(wilc, tqe->q_num, tqe); 222 tqe->status = 1; 223 if (tqe->tx_complete_func) 224 tqe->tx_complete_func(tqe->priv, 225 tqe->status); 226 kfree(tqe); 227 dropped++; 228 } 229 } 230 } 231 f->pending_acks_idx = 0; 232 f->tcp_session = 0; 233 234 if (f->pending_base == 0) 235 f->pending_base = MAX_TCP_SESSION; 236 else 237 f->pending_base = 0; 238 239 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 240 241 while (dropped > 0) { 242 wait_for_completion_timeout(&wilc->txq_event, 243 msecs_to_jiffies(1)); 244 dropped--; 245 } 246 } 247 248 void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value) 249 { 250 vif->ack_filter.enabled = value; 251 } 252 253 static int wilc_wlan_txq_add_cfg_pkt(struct wilc_vif *vif, u8 *buffer, 254 u32 buffer_size) 255 { 256 struct txq_entry_t *tqe; 257 struct wilc *wilc = vif->wilc; 258 259 netdev_dbg(vif->ndev, "Adding config packet ...\n"); 260 if (wilc->quit) { 261 netdev_dbg(vif->ndev, "Return due to clear function\n"); 262 complete(&wilc->cfg_event); 263 return 0; 264 } 265 266 tqe = kmalloc(sizeof(*tqe), GFP_ATOMIC); 267 if (!tqe) { 268 complete(&wilc->cfg_event); 269 return 0; 270 } 271 272 tqe->type = WILC_CFG_PKT; 273 tqe->buffer = buffer; 274 tqe->buffer_size = buffer_size; 275 tqe->tx_complete_func = NULL; 276 tqe->priv = NULL; 277 tqe->q_num = AC_VO_Q; 278 tqe->ack_idx = NOT_TCP_ACK; 279 tqe->vif = vif; 280 281 wilc_wlan_txq_add_to_head(vif, AC_VO_Q, tqe); 282 283 return 1; 284 } 285 286 static bool is_ac_q_limit(struct wilc *wl, u8 q_num) 287 { 288 u8 factors[NQUEUES] = {1, 1, 1, 1}; 289 u16 i; 290 unsigned long flags; 291 struct wilc_tx_queue_status *q = &wl->tx_q_limit; 292 u8 end_index; 293 u8 q_limit; 294 bool ret = false; 295 296 spin_lock_irqsave(&wl->txq_spinlock, flags); 297 if (!q->initialized) { 298 for (i = 0; i < AC_BUFFER_SIZE; i++) 299 q->buffer[i] = i % NQUEUES; 300 301 for (i = 0; i < NQUEUES; i++) { 302 q->cnt[i] = AC_BUFFER_SIZE * factors[i] / NQUEUES; 303 q->sum += q->cnt[i]; 304 } 305 q->end_index = AC_BUFFER_SIZE - 1; 306 q->initialized = 1; 307 } 308 309 end_index = q->end_index; 310 q->cnt[q->buffer[end_index]] -= factors[q->buffer[end_index]]; 311 q->cnt[q_num] += factors[q_num]; 312 q->sum += (factors[q_num] - factors[q->buffer[end_index]]); 313 314 q->buffer[end_index] = q_num; 315 if (end_index > 0) 316 q->end_index--; 317 else 318 q->end_index = AC_BUFFER_SIZE - 1; 319 320 if (!q->sum) 321 q_limit = 1; 322 else 323 q_limit = (q->cnt[q_num] * FLOW_CONTROL_UPPER_THRESHOLD / q->sum) + 1; 324 325 if (wl->txq[q_num].count <= q_limit) 326 ret = true; 327 328 spin_unlock_irqrestore(&wl->txq_spinlock, flags); 329 330 return ret; 331 } 332 333 static inline u8 ac_classify(struct wilc *wilc, struct sk_buff *skb) 334 { 335 u8 q_num = AC_BE_Q; 336 u8 dscp; 337 338 switch (skb->protocol) { 339 case htons(ETH_P_IP): 340 dscp = ipv4_get_dsfield(ip_hdr(skb)) & 0xfc; 341 break; 342 case htons(ETH_P_IPV6): 343 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) & 0xfc; 344 break; 345 default: 346 return q_num; 347 } 348 349 switch (dscp) { 350 case 0x08: 351 case 0x20: 352 case 0x40: 353 q_num = AC_BK_Q; 354 break; 355 case 0x80: 356 case 0xA0: 357 case 0x28: 358 q_num = AC_VI_Q; 359 break; 360 case 0xC0: 361 case 0xD0: 362 case 0xE0: 363 case 0x88: 364 case 0xB8: 365 q_num = AC_VO_Q; 366 break; 367 } 368 369 return q_num; 370 } 371 372 static inline int ac_balance(struct wilc *wl, u8 *ratio) 373 { 374 u8 i, max_count = 0; 375 376 if (!ratio) 377 return -EINVAL; 378 379 for (i = 0; i < NQUEUES; i++) 380 if (wl->txq[i].fw.count > max_count) 381 max_count = wl->txq[i].fw.count; 382 383 for (i = 0; i < NQUEUES; i++) 384 ratio[i] = max_count - wl->txq[i].fw.count; 385 386 return 0; 387 } 388 389 static inline void ac_update_fw_ac_pkt_info(struct wilc *wl, u32 reg) 390 { 391 wl->txq[AC_BK_Q].fw.count = FIELD_GET(BK_AC_COUNT_FIELD, reg); 392 wl->txq[AC_BE_Q].fw.count = FIELD_GET(BE_AC_COUNT_FIELD, reg); 393 wl->txq[AC_VI_Q].fw.count = FIELD_GET(VI_AC_COUNT_FIELD, reg); 394 wl->txq[AC_VO_Q].fw.count = FIELD_GET(VO_AC_COUNT_FIELD, reg); 395 396 wl->txq[AC_BK_Q].fw.acm = FIELD_GET(BK_AC_ACM_STAT_FIELD, reg); 397 wl->txq[AC_BE_Q].fw.acm = FIELD_GET(BE_AC_ACM_STAT_FIELD, reg); 398 wl->txq[AC_VI_Q].fw.acm = FIELD_GET(VI_AC_ACM_STAT_FIELD, reg); 399 wl->txq[AC_VO_Q].fw.acm = FIELD_GET(VO_AC_ACM_STAT_FIELD, reg); 400 } 401 402 static inline u8 ac_change(struct wilc *wilc, u8 *ac) 403 { 404 do { 405 if (wilc->txq[*ac].fw.acm == 0) 406 return 0; 407 (*ac)++; 408 } while (*ac < NQUEUES); 409 410 return 1; 411 } 412 413 int wilc_wlan_txq_add_net_pkt(struct net_device *dev, 414 struct tx_complete_data *tx_data, u8 *buffer, 415 u32 buffer_size, 416 void (*tx_complete_fn)(void *, int)) 417 { 418 struct txq_entry_t *tqe; 419 struct wilc_vif *vif = netdev_priv(dev); 420 struct wilc *wilc; 421 u8 q_num; 422 423 wilc = vif->wilc; 424 425 if (wilc->quit) { 426 tx_complete_fn(tx_data, 0); 427 return 0; 428 } 429 430 if (!wilc->initialized) { 431 tx_complete_fn(tx_data, 0); 432 return 0; 433 } 434 435 tqe = kmalloc(sizeof(*tqe), GFP_ATOMIC); 436 437 if (!tqe) { 438 tx_complete_fn(tx_data, 0); 439 return 0; 440 } 441 tqe->type = WILC_NET_PKT; 442 tqe->buffer = buffer; 443 tqe->buffer_size = buffer_size; 444 tqe->tx_complete_func = tx_complete_fn; 445 tqe->priv = tx_data; 446 tqe->vif = vif; 447 448 q_num = ac_classify(wilc, tx_data->skb); 449 tqe->q_num = q_num; 450 if (ac_change(wilc, &q_num)) { 451 tx_complete_fn(tx_data, 0); 452 kfree(tqe); 453 return 0; 454 } 455 456 if (is_ac_q_limit(wilc, q_num)) { 457 tqe->ack_idx = NOT_TCP_ACK; 458 if (vif->ack_filter.enabled) 459 tcp_process(dev, tqe); 460 wilc_wlan_txq_add_to_tail(dev, q_num, tqe); 461 } else { 462 tx_complete_fn(tx_data, 0); 463 kfree(tqe); 464 } 465 466 return wilc->txq_entries; 467 } 468 469 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer, 470 u32 buffer_size, 471 void (*tx_complete_fn)(void *, int)) 472 { 473 struct txq_entry_t *tqe; 474 struct wilc_vif *vif = netdev_priv(dev); 475 struct wilc *wilc; 476 477 wilc = vif->wilc; 478 479 if (wilc->quit) { 480 tx_complete_fn(priv, 0); 481 return 0; 482 } 483 484 if (!wilc->initialized) { 485 tx_complete_fn(priv, 0); 486 return 0; 487 } 488 tqe = kmalloc(sizeof(*tqe), GFP_ATOMIC); 489 490 if (!tqe) { 491 tx_complete_fn(priv, 0); 492 return 0; 493 } 494 tqe->type = WILC_MGMT_PKT; 495 tqe->buffer = buffer; 496 tqe->buffer_size = buffer_size; 497 tqe->tx_complete_func = tx_complete_fn; 498 tqe->priv = priv; 499 tqe->q_num = AC_BE_Q; 500 tqe->ack_idx = NOT_TCP_ACK; 501 tqe->vif = vif; 502 wilc_wlan_txq_add_to_tail(dev, AC_VO_Q, tqe); 503 return 1; 504 } 505 506 static struct txq_entry_t *wilc_wlan_txq_get_first(struct wilc *wilc, u8 q_num) 507 { 508 struct txq_entry_t *tqe = NULL; 509 unsigned long flags; 510 511 spin_lock_irqsave(&wilc->txq_spinlock, flags); 512 513 if (!list_empty(&wilc->txq[q_num].txq_head.list)) 514 tqe = list_first_entry(&wilc->txq[q_num].txq_head.list, 515 struct txq_entry_t, list); 516 517 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 518 519 return tqe; 520 } 521 522 static struct txq_entry_t *wilc_wlan_txq_get_next(struct wilc *wilc, 523 struct txq_entry_t *tqe, 524 u8 q_num) 525 { 526 unsigned long flags; 527 528 spin_lock_irqsave(&wilc->txq_spinlock, flags); 529 530 if (!list_is_last(&tqe->list, &wilc->txq[q_num].txq_head.list)) 531 tqe = list_next_entry(tqe, list); 532 else 533 tqe = NULL; 534 spin_unlock_irqrestore(&wilc->txq_spinlock, flags); 535 536 return tqe; 537 } 538 539 static void wilc_wlan_rxq_add(struct wilc *wilc, struct rxq_entry_t *rqe) 540 { 541 if (wilc->quit) 542 return; 543 544 mutex_lock(&wilc->rxq_cs); 545 list_add_tail(&rqe->list, &wilc->rxq_head.list); 546 mutex_unlock(&wilc->rxq_cs); 547 } 548 549 static struct rxq_entry_t *wilc_wlan_rxq_remove(struct wilc *wilc) 550 { 551 struct rxq_entry_t *rqe = NULL; 552 553 mutex_lock(&wilc->rxq_cs); 554 if (!list_empty(&wilc->rxq_head.list)) { 555 rqe = list_first_entry(&wilc->rxq_head.list, struct rxq_entry_t, 556 list); 557 list_del(&rqe->list); 558 } 559 mutex_unlock(&wilc->rxq_cs); 560 return rqe; 561 } 562 563 void chip_allow_sleep(struct wilc *wilc) 564 { 565 u32 reg = 0; 566 const struct wilc_hif_func *hif_func = wilc->hif_func; 567 u32 wakeup_reg, wakeup_bit; 568 u32 to_host_from_fw_reg, to_host_from_fw_bit; 569 u32 from_host_to_fw_reg, from_host_to_fw_bit; 570 u32 trials = 100; 571 int ret; 572 573 if (wilc->io_type == WILC_HIF_SDIO) { 574 wakeup_reg = WILC_SDIO_WAKEUP_REG; 575 wakeup_bit = WILC_SDIO_WAKEUP_BIT; 576 from_host_to_fw_reg = WILC_SDIO_HOST_TO_FW_REG; 577 from_host_to_fw_bit = WILC_SDIO_HOST_TO_FW_BIT; 578 to_host_from_fw_reg = WILC_SDIO_FW_TO_HOST_REG; 579 to_host_from_fw_bit = WILC_SDIO_FW_TO_HOST_BIT; 580 } else { 581 wakeup_reg = WILC_SPI_WAKEUP_REG; 582 wakeup_bit = WILC_SPI_WAKEUP_BIT; 583 from_host_to_fw_reg = WILC_SPI_HOST_TO_FW_REG; 584 from_host_to_fw_bit = WILC_SPI_HOST_TO_FW_BIT; 585 to_host_from_fw_reg = WILC_SPI_FW_TO_HOST_REG; 586 to_host_from_fw_bit = WILC_SPI_FW_TO_HOST_BIT; 587 } 588 589 while (--trials) { 590 ret = hif_func->hif_read_reg(wilc, to_host_from_fw_reg, ®); 591 if (ret) 592 return; 593 if ((reg & to_host_from_fw_bit) == 0) 594 break; 595 } 596 if (!trials) 597 pr_warn("FW not responding\n"); 598 599 /* Clear bit 1 */ 600 ret = hif_func->hif_read_reg(wilc, wakeup_reg, ®); 601 if (ret) 602 return; 603 if (reg & wakeup_bit) { 604 reg &= ~wakeup_bit; 605 ret = hif_func->hif_write_reg(wilc, wakeup_reg, reg); 606 if (ret) 607 return; 608 } 609 610 ret = hif_func->hif_read_reg(wilc, from_host_to_fw_reg, ®); 611 if (ret) 612 return; 613 if (reg & from_host_to_fw_bit) { 614 reg &= ~from_host_to_fw_bit; 615 ret = hif_func->hif_write_reg(wilc, from_host_to_fw_reg, reg); 616 if (ret) 617 return; 618 619 } 620 } 621 EXPORT_SYMBOL_GPL(chip_allow_sleep); 622 623 void chip_wakeup(struct wilc *wilc) 624 { 625 u32 ret = 0; 626 u32 clk_status_val = 0, trials = 0; 627 u32 wakeup_reg, wakeup_bit; 628 u32 clk_status_reg, clk_status_bit; 629 u32 to_host_from_fw_reg, to_host_from_fw_bit; 630 u32 from_host_to_fw_reg, from_host_to_fw_bit; 631 const struct wilc_hif_func *hif_func = wilc->hif_func; 632 633 if (wilc->io_type == WILC_HIF_SDIO) { 634 wakeup_reg = WILC_SDIO_WAKEUP_REG; 635 wakeup_bit = WILC_SDIO_WAKEUP_BIT; 636 clk_status_reg = WILC_SDIO_CLK_STATUS_REG; 637 clk_status_bit = WILC_SDIO_CLK_STATUS_BIT; 638 from_host_to_fw_reg = WILC_SDIO_HOST_TO_FW_REG; 639 from_host_to_fw_bit = WILC_SDIO_HOST_TO_FW_BIT; 640 to_host_from_fw_reg = WILC_SDIO_FW_TO_HOST_REG; 641 to_host_from_fw_bit = WILC_SDIO_FW_TO_HOST_BIT; 642 } else { 643 wakeup_reg = WILC_SPI_WAKEUP_REG; 644 wakeup_bit = WILC_SPI_WAKEUP_BIT; 645 clk_status_reg = WILC_SPI_CLK_STATUS_REG; 646 clk_status_bit = WILC_SPI_CLK_STATUS_BIT; 647 from_host_to_fw_reg = WILC_SPI_HOST_TO_FW_REG; 648 from_host_to_fw_bit = WILC_SPI_HOST_TO_FW_BIT; 649 to_host_from_fw_reg = WILC_SPI_FW_TO_HOST_REG; 650 to_host_from_fw_bit = WILC_SPI_FW_TO_HOST_BIT; 651 } 652 653 /* indicate host wakeup */ 654 ret = hif_func->hif_write_reg(wilc, from_host_to_fw_reg, 655 from_host_to_fw_bit); 656 if (ret) 657 return; 658 659 /* Set wake-up bit */ 660 ret = hif_func->hif_write_reg(wilc, wakeup_reg, 661 wakeup_bit); 662 if (ret) 663 return; 664 665 while (trials < WAKE_UP_TRIAL_RETRY) { 666 ret = hif_func->hif_read_reg(wilc, clk_status_reg, 667 &clk_status_val); 668 if (ret) { 669 pr_err("Bus error %d %x\n", ret, clk_status_val); 670 return; 671 } 672 if (clk_status_val & clk_status_bit) 673 break; 674 675 trials++; 676 } 677 if (trials >= WAKE_UP_TRIAL_RETRY) { 678 pr_err("Failed to wake-up the chip\n"); 679 return; 680 } 681 /* Sometimes spi fail to read clock regs after reading 682 * writing clockless registers 683 */ 684 if (wilc->io_type == WILC_HIF_SPI) 685 wilc->hif_func->hif_reset(wilc); 686 } 687 EXPORT_SYMBOL_GPL(chip_wakeup); 688 689 void host_wakeup_notify(struct wilc *wilc) 690 { 691 acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); 692 wilc->hif_func->hif_write_reg(wilc, WILC_CORTUS_INTERRUPT_2, 1); 693 release_bus(wilc, WILC_BUS_RELEASE_ONLY); 694 } 695 EXPORT_SYMBOL_GPL(host_wakeup_notify); 696 697 void host_sleep_notify(struct wilc *wilc) 698 { 699 acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); 700 wilc->hif_func->hif_write_reg(wilc, WILC_CORTUS_INTERRUPT_1, 1); 701 release_bus(wilc, WILC_BUS_RELEASE_ONLY); 702 } 703 EXPORT_SYMBOL_GPL(host_sleep_notify); 704 705 int wilc_wlan_handle_txq(struct wilc *wilc, u32 *txq_count) 706 { 707 int i, entries = 0; 708 u8 k, ac; 709 u32 sum; 710 u32 reg; 711 u8 ac_desired_ratio[NQUEUES] = {0, 0, 0, 0}; 712 u8 ac_preserve_ratio[NQUEUES] = {1, 1, 1, 1}; 713 u8 *num_pkts_to_add; 714 u8 vmm_entries_ac[WILC_VMM_TBL_SIZE]; 715 u32 offset = 0; 716 bool max_size_over = 0, ac_exist = 0; 717 int vmm_sz = 0; 718 struct txq_entry_t *tqe_q[NQUEUES]; 719 int ret = 0; 720 int counter; 721 int timeout; 722 u32 vmm_table[WILC_VMM_TBL_SIZE]; 723 u8 ac_pkt_num_to_chip[NQUEUES] = {0, 0, 0, 0}; 724 const struct wilc_hif_func *func; 725 int srcu_idx; 726 u8 *txb = wilc->tx_buffer; 727 struct wilc_vif *vif; 728 729 if (wilc->quit) 730 goto out_update_cnt; 731 732 if (ac_balance(wilc, ac_desired_ratio)) 733 return -EINVAL; 734 735 mutex_lock(&wilc->txq_add_to_head_cs); 736 737 srcu_idx = srcu_read_lock(&wilc->srcu); 738 list_for_each_entry_rcu(vif, &wilc->vif_list, list) 739 wilc_wlan_txq_filter_dup_tcp_ack(vif->ndev); 740 srcu_read_unlock(&wilc->srcu, srcu_idx); 741 742 for (ac = 0; ac < NQUEUES; ac++) 743 tqe_q[ac] = wilc_wlan_txq_get_first(wilc, ac); 744 745 i = 0; 746 sum = 0; 747 max_size_over = 0; 748 num_pkts_to_add = ac_desired_ratio; 749 do { 750 ac_exist = 0; 751 for (ac = 0; (ac < NQUEUES) && (!max_size_over); ac++) { 752 if (!tqe_q[ac]) 753 continue; 754 755 ac_exist = 1; 756 for (k = 0; (k < num_pkts_to_add[ac]) && 757 (!max_size_over) && tqe_q[ac]; k++) { 758 if (i >= (WILC_VMM_TBL_SIZE - 1)) { 759 max_size_over = 1; 760 break; 761 } 762 763 if (tqe_q[ac]->type == WILC_CFG_PKT) 764 vmm_sz = ETH_CONFIG_PKT_HDR_OFFSET; 765 else if (tqe_q[ac]->type == WILC_NET_PKT) 766 vmm_sz = ETH_ETHERNET_HDR_OFFSET; 767 else 768 vmm_sz = HOST_HDR_OFFSET; 769 770 vmm_sz += tqe_q[ac]->buffer_size; 771 vmm_sz = ALIGN(vmm_sz, 4); 772 773 if ((sum + vmm_sz) > WILC_TX_BUFF_SIZE) { 774 max_size_over = 1; 775 break; 776 } 777 vmm_table[i] = vmm_sz / 4; 778 if (tqe_q[ac]->type == WILC_CFG_PKT) 779 vmm_table[i] |= BIT(10); 780 781 cpu_to_le32s(&vmm_table[i]); 782 vmm_entries_ac[i] = ac; 783 784 i++; 785 sum += vmm_sz; 786 tqe_q[ac] = wilc_wlan_txq_get_next(wilc, 787 tqe_q[ac], 788 ac); 789 } 790 } 791 num_pkts_to_add = ac_preserve_ratio; 792 } while (!max_size_over && ac_exist); 793 794 if (i == 0) 795 goto out_unlock; 796 vmm_table[i] = 0x0; 797 798 acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); 799 counter = 0; 800 func = wilc->hif_func; 801 do { 802 ret = func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); 803 if (ret) 804 break; 805 806 if ((reg & 0x1) == 0) { 807 ac_update_fw_ac_pkt_info(wilc, reg); 808 break; 809 } 810 811 counter++; 812 if (counter > 200) { 813 counter = 0; 814 ret = func->hif_write_reg(wilc, WILC_HOST_TX_CTRL, 0); 815 break; 816 } 817 } while (!wilc->quit); 818 819 if (ret) 820 goto out_release_bus; 821 822 timeout = 200; 823 do { 824 ret = func->hif_block_tx(wilc, 825 WILC_VMM_TBL_RX_SHADOW_BASE, 826 (u8 *)vmm_table, 827 ((i + 1) * 4)); 828 if (ret) 829 break; 830 831 ret = func->hif_write_reg(wilc, WILC_HOST_VMM_CTL, 0x2); 832 if (ret) 833 break; 834 835 do { 836 ret = func->hif_read_reg(wilc, WILC_HOST_VMM_CTL, ®); 837 if (ret) 838 break; 839 if (FIELD_GET(WILC_VMM_ENTRY_AVAILABLE, reg)) { 840 entries = FIELD_GET(WILC_VMM_ENTRY_COUNT, reg); 841 break; 842 } 843 } while (--timeout); 844 if (timeout <= 0) { 845 ret = func->hif_write_reg(wilc, WILC_HOST_VMM_CTL, 0x0); 846 break; 847 } 848 849 if (ret) 850 break; 851 852 if (entries == 0) { 853 ret = func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); 854 if (ret) 855 break; 856 reg &= ~BIT(0); 857 ret = func->hif_write_reg(wilc, WILC_HOST_TX_CTRL, reg); 858 } 859 } while (0); 860 861 if (ret) 862 goto out_release_bus; 863 864 if (entries == 0) { 865 /* 866 * No VMM space available in firmware so retry to transmit 867 * the packet from tx queue. 868 */ 869 ret = WILC_VMM_ENTRY_FULL_RETRY; 870 goto out_release_bus; 871 } 872 873 release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); 874 875 offset = 0; 876 i = 0; 877 do { 878 struct txq_entry_t *tqe; 879 u32 header, buffer_offset; 880 char *bssid; 881 u8 mgmt_ptk = 0; 882 883 tqe = wilc_wlan_txq_remove_from_head(wilc, vmm_entries_ac[i]); 884 ac_pkt_num_to_chip[vmm_entries_ac[i]]++; 885 if (!tqe) 886 break; 887 888 vif = tqe->vif; 889 if (vmm_table[i] == 0) 890 break; 891 892 le32_to_cpus(&vmm_table[i]); 893 vmm_sz = FIELD_GET(WILC_VMM_BUFFER_SIZE, vmm_table[i]); 894 vmm_sz *= 4; 895 896 if (tqe->type == WILC_MGMT_PKT) 897 mgmt_ptk = 1; 898 899 header = (FIELD_PREP(WILC_VMM_HDR_TYPE, tqe->type) | 900 FIELD_PREP(WILC_VMM_HDR_MGMT_FIELD, mgmt_ptk) | 901 FIELD_PREP(WILC_VMM_HDR_PKT_SIZE, tqe->buffer_size) | 902 FIELD_PREP(WILC_VMM_HDR_BUFF_SIZE, vmm_sz)); 903 904 cpu_to_le32s(&header); 905 memcpy(&txb[offset], &header, 4); 906 if (tqe->type == WILC_CFG_PKT) { 907 buffer_offset = ETH_CONFIG_PKT_HDR_OFFSET; 908 } else if (tqe->type == WILC_NET_PKT) { 909 int prio = tqe->q_num; 910 911 bssid = tqe->vif->bssid; 912 buffer_offset = ETH_ETHERNET_HDR_OFFSET; 913 memcpy(&txb[offset + 4], &prio, sizeof(prio)); 914 memcpy(&txb[offset + 8], bssid, 6); 915 } else { 916 buffer_offset = HOST_HDR_OFFSET; 917 } 918 919 memcpy(&txb[offset + buffer_offset], 920 tqe->buffer, tqe->buffer_size); 921 offset += vmm_sz; 922 i++; 923 tqe->status = 1; 924 if (tqe->tx_complete_func) 925 tqe->tx_complete_func(tqe->priv, tqe->status); 926 if (tqe->ack_idx != NOT_TCP_ACK && 927 tqe->ack_idx < MAX_PENDING_ACKS) 928 vif->ack_filter.pending_acks[tqe->ack_idx].txqe = NULL; 929 kfree(tqe); 930 } while (--entries); 931 for (i = 0; i < NQUEUES; i++) 932 wilc->txq[i].fw.count += ac_pkt_num_to_chip[i]; 933 934 acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); 935 936 ret = func->hif_clear_int_ext(wilc, ENABLE_TX_VMM); 937 if (ret) 938 goto out_release_bus; 939 940 ret = func->hif_block_tx_ext(wilc, 0, txb, offset); 941 942 out_release_bus: 943 release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); 944 945 out_unlock: 946 mutex_unlock(&wilc->txq_add_to_head_cs); 947 948 out_update_cnt: 949 *txq_count = wilc->txq_entries; 950 return ret; 951 } 952 953 static void wilc_wlan_handle_rx_buff(struct wilc *wilc, u8 *buffer, int size) 954 { 955 int offset = 0; 956 u32 header; 957 u32 pkt_len, pkt_offset, tp_len; 958 int is_cfg_packet; 959 u8 *buff_ptr; 960 961 do { 962 buff_ptr = buffer + offset; 963 header = get_unaligned_le32(buff_ptr); 964 965 is_cfg_packet = FIELD_GET(WILC_PKT_HDR_CONFIG_FIELD, header); 966 pkt_offset = FIELD_GET(WILC_PKT_HDR_OFFSET_FIELD, header); 967 tp_len = FIELD_GET(WILC_PKT_HDR_TOTAL_LEN_FIELD, header); 968 pkt_len = FIELD_GET(WILC_PKT_HDR_LEN_FIELD, header); 969 970 if (pkt_len == 0 || tp_len == 0) 971 break; 972 973 if (pkt_offset & IS_MANAGMEMENT) { 974 buff_ptr += HOST_HDR_OFFSET; 975 wilc_wfi_mgmt_rx(wilc, buff_ptr, pkt_len); 976 } else { 977 if (!is_cfg_packet) { 978 wilc_frmw_to_host(wilc, buff_ptr, pkt_len, 979 pkt_offset); 980 } else { 981 struct wilc_cfg_rsp rsp; 982 983 buff_ptr += pkt_offset; 984 985 wilc_wlan_cfg_indicate_rx(wilc, buff_ptr, 986 pkt_len, 987 &rsp); 988 if (rsp.type == WILC_CFG_RSP) { 989 if (wilc->cfg_seq_no == rsp.seq_no) 990 complete(&wilc->cfg_event); 991 } else if (rsp.type == WILC_CFG_RSP_STATUS) { 992 wilc_mac_indicate(wilc); 993 } 994 } 995 } 996 offset += tp_len; 997 } while (offset < size); 998 } 999 1000 static void wilc_wlan_handle_rxq(struct wilc *wilc) 1001 { 1002 int size; 1003 u8 *buffer; 1004 struct rxq_entry_t *rqe; 1005 1006 while (!wilc->quit) { 1007 rqe = wilc_wlan_rxq_remove(wilc); 1008 if (!rqe) 1009 break; 1010 1011 buffer = rqe->buffer; 1012 size = rqe->buffer_size; 1013 wilc_wlan_handle_rx_buff(wilc, buffer, size); 1014 1015 kfree(rqe); 1016 } 1017 if (wilc->quit) 1018 complete(&wilc->cfg_event); 1019 } 1020 1021 static void wilc_unknown_isr_ext(struct wilc *wilc) 1022 { 1023 wilc->hif_func->hif_clear_int_ext(wilc, 0); 1024 } 1025 1026 static void wilc_wlan_handle_isr_ext(struct wilc *wilc, u32 int_status) 1027 { 1028 u32 offset = wilc->rx_buffer_offset; 1029 u8 *buffer = NULL; 1030 u32 size; 1031 u32 retries = 0; 1032 int ret = 0; 1033 struct rxq_entry_t *rqe; 1034 1035 size = FIELD_GET(WILC_INTERRUPT_DATA_SIZE, int_status) << 2; 1036 1037 while (!size && retries < 10) { 1038 wilc->hif_func->hif_read_size(wilc, &size); 1039 size = FIELD_GET(WILC_INTERRUPT_DATA_SIZE, size) << 2; 1040 retries++; 1041 } 1042 1043 if (size <= 0) 1044 return; 1045 1046 if (WILC_RX_BUFF_SIZE - offset < size) 1047 offset = 0; 1048 1049 buffer = &wilc->rx_buffer[offset]; 1050 1051 wilc->hif_func->hif_clear_int_ext(wilc, DATA_INT_CLR | ENABLE_RX_VMM); 1052 ret = wilc->hif_func->hif_block_rx_ext(wilc, 0, buffer, size); 1053 if (ret) 1054 return; 1055 1056 offset += size; 1057 wilc->rx_buffer_offset = offset; 1058 rqe = kmalloc(sizeof(*rqe), GFP_KERNEL); 1059 if (!rqe) 1060 return; 1061 1062 rqe->buffer = buffer; 1063 rqe->buffer_size = size; 1064 wilc_wlan_rxq_add(wilc, rqe); 1065 wilc_wlan_handle_rxq(wilc); 1066 } 1067 1068 void wilc_handle_isr(struct wilc *wilc) 1069 { 1070 u32 int_status; 1071 1072 acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); 1073 wilc->hif_func->hif_read_int(wilc, &int_status); 1074 1075 if (int_status & DATA_INT_EXT) 1076 wilc_wlan_handle_isr_ext(wilc, int_status); 1077 1078 if (!(int_status & (ALL_INT_EXT))) 1079 wilc_unknown_isr_ext(wilc); 1080 1081 release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); 1082 } 1083 EXPORT_SYMBOL_GPL(wilc_handle_isr); 1084 1085 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer, 1086 u32 buffer_size) 1087 { 1088 u32 offset; 1089 u32 addr, size, size2, blksz; 1090 u8 *dma_buffer; 1091 int ret = 0; 1092 u32 reg = 0; 1093 1094 blksz = BIT(12); 1095 1096 dma_buffer = kmalloc(blksz, GFP_KERNEL); 1097 if (!dma_buffer) 1098 return -EIO; 1099 1100 offset = 0; 1101 pr_debug("%s: Downloading firmware size = %d\n", __func__, buffer_size); 1102 1103 acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); 1104 1105 wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); 1106 reg &= ~BIT(10); 1107 ret = wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); 1108 wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); 1109 if (reg & BIT(10)) 1110 pr_err("%s: Failed to reset\n", __func__); 1111 1112 release_bus(wilc, WILC_BUS_RELEASE_ONLY); 1113 do { 1114 addr = get_unaligned_le32(&buffer[offset]); 1115 size = get_unaligned_le32(&buffer[offset + 4]); 1116 acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); 1117 offset += 8; 1118 while (((int)size) && (offset < buffer_size)) { 1119 if (size <= blksz) 1120 size2 = size; 1121 else 1122 size2 = blksz; 1123 1124 memcpy(dma_buffer, &buffer[offset], size2); 1125 ret = wilc->hif_func->hif_block_tx(wilc, addr, 1126 dma_buffer, size2); 1127 if (ret) 1128 break; 1129 1130 addr += size2; 1131 offset += size2; 1132 size -= size2; 1133 } 1134 release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); 1135 1136 if (ret) { 1137 pr_err("%s Bus error\n", __func__); 1138 goto fail; 1139 } 1140 pr_debug("%s Offset = %d\n", __func__, offset); 1141 } while (offset < buffer_size); 1142 1143 fail: 1144 1145 kfree(dma_buffer); 1146 1147 return ret; 1148 } 1149 1150 int wilc_wlan_start(struct wilc *wilc) 1151 { 1152 u32 reg = 0; 1153 int ret; 1154 u32 chipid; 1155 1156 if (wilc->io_type == WILC_HIF_SDIO) { 1157 reg = 0; 1158 reg |= BIT(3); 1159 } else if (wilc->io_type == WILC_HIF_SPI) { 1160 reg = 1; 1161 } 1162 acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); 1163 ret = wilc->hif_func->hif_write_reg(wilc, WILC_VMM_CORE_CFG, reg); 1164 if (ret) 1165 goto release; 1166 1167 reg = 0; 1168 if (wilc->io_type == WILC_HIF_SDIO && wilc->dev_irq_num) 1169 reg |= WILC_HAVE_SDIO_IRQ_GPIO; 1170 1171 ret = wilc->hif_func->hif_write_reg(wilc, WILC_GP_REG_1, reg); 1172 if (ret) 1173 goto release; 1174 1175 wilc->hif_func->hif_sync_ext(wilc, NUM_INT_EXT); 1176 1177 ret = wilc->hif_func->hif_read_reg(wilc, WILC_CHIPID, &chipid); 1178 if (ret) 1179 goto release; 1180 1181 wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); 1182 if ((reg & BIT(10)) == BIT(10)) { 1183 reg &= ~BIT(10); 1184 wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); 1185 wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); 1186 } 1187 1188 reg |= BIT(10); 1189 ret = wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); 1190 wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); 1191 1192 release: 1193 release_bus(wilc, WILC_BUS_RELEASE_ONLY); 1194 return ret; 1195 } 1196 1197 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif) 1198 { 1199 u32 reg = 0; 1200 int ret; 1201 1202 acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); 1203 1204 ret = wilc->hif_func->hif_read_reg(wilc, WILC_GP_REG_0, ®); 1205 if (ret) { 1206 netdev_err(vif->ndev, "Error while reading reg\n"); 1207 goto release; 1208 } 1209 1210 ret = wilc->hif_func->hif_write_reg(wilc, WILC_GP_REG_0, 1211 (reg | WILC_ABORT_REQ_BIT)); 1212 if (ret) { 1213 netdev_err(vif->ndev, "Error while writing reg\n"); 1214 goto release; 1215 } 1216 1217 ret = wilc->hif_func->hif_read_reg(wilc, WILC_FW_HOST_COMM, ®); 1218 if (ret) { 1219 netdev_err(vif->ndev, "Error while reading reg\n"); 1220 goto release; 1221 } 1222 reg = BIT(0); 1223 1224 ret = wilc->hif_func->hif_write_reg(wilc, WILC_FW_HOST_COMM, reg); 1225 if (ret) { 1226 netdev_err(vif->ndev, "Error while writing reg\n"); 1227 goto release; 1228 } 1229 1230 ret = 0; 1231 release: 1232 release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); 1233 1234 return ret; 1235 } 1236 1237 void wilc_wlan_cleanup(struct net_device *dev) 1238 { 1239 struct txq_entry_t *tqe; 1240 struct rxq_entry_t *rqe; 1241 u8 ac; 1242 struct wilc_vif *vif = netdev_priv(dev); 1243 struct wilc *wilc = vif->wilc; 1244 1245 wilc->quit = 1; 1246 for (ac = 0; ac < NQUEUES; ac++) { 1247 while ((tqe = wilc_wlan_txq_remove_from_head(wilc, ac))) { 1248 if (tqe->tx_complete_func) 1249 tqe->tx_complete_func(tqe->priv, 0); 1250 kfree(tqe); 1251 } 1252 } 1253 1254 while ((rqe = wilc_wlan_rxq_remove(wilc))) 1255 kfree(rqe); 1256 1257 kfree(wilc->rx_buffer); 1258 wilc->rx_buffer = NULL; 1259 kfree(wilc->tx_buffer); 1260 wilc->tx_buffer = NULL; 1261 wilc->hif_func->hif_deinit(NULL); 1262 } 1263 1264 static int wilc_wlan_cfg_commit(struct wilc_vif *vif, int type, 1265 u32 drv_handler) 1266 { 1267 struct wilc *wilc = vif->wilc; 1268 struct wilc_cfg_frame *cfg = &wilc->cfg_frame; 1269 int t_len = wilc->cfg_frame_offset + sizeof(struct wilc_cfg_cmd_hdr); 1270 1271 if (type == WILC_CFG_SET) 1272 cfg->hdr.cmd_type = 'W'; 1273 else 1274 cfg->hdr.cmd_type = 'Q'; 1275 1276 cfg->hdr.seq_no = wilc->cfg_seq_no % 256; 1277 cfg->hdr.total_len = cpu_to_le16(t_len); 1278 cfg->hdr.driver_handler = cpu_to_le32(drv_handler); 1279 wilc->cfg_seq_no = cfg->hdr.seq_no; 1280 1281 if (!wilc_wlan_txq_add_cfg_pkt(vif, (u8 *)&cfg->hdr, t_len)) 1282 return -1; 1283 1284 return 0; 1285 } 1286 1287 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer, 1288 u32 buffer_size, int commit, u32 drv_handler) 1289 { 1290 u32 offset; 1291 int ret_size; 1292 struct wilc *wilc = vif->wilc; 1293 1294 mutex_lock(&wilc->cfg_cmd_lock); 1295 1296 if (start) 1297 wilc->cfg_frame_offset = 0; 1298 1299 offset = wilc->cfg_frame_offset; 1300 ret_size = wilc_wlan_cfg_set_wid(wilc->cfg_frame.frame, offset, 1301 wid, buffer, buffer_size); 1302 offset += ret_size; 1303 wilc->cfg_frame_offset = offset; 1304 1305 if (!commit) { 1306 mutex_unlock(&wilc->cfg_cmd_lock); 1307 return ret_size; 1308 } 1309 1310 netdev_dbg(vif->ndev, "%s: seqno[%d]\n", __func__, wilc->cfg_seq_no); 1311 1312 if (wilc_wlan_cfg_commit(vif, WILC_CFG_SET, drv_handler)) 1313 ret_size = 0; 1314 1315 if (!wait_for_completion_timeout(&wilc->cfg_event, 1316 WILC_CFG_PKTS_TIMEOUT)) { 1317 netdev_dbg(vif->ndev, "%s: Timed Out\n", __func__); 1318 ret_size = 0; 1319 } 1320 1321 wilc->cfg_frame_offset = 0; 1322 wilc->cfg_seq_no += 1; 1323 mutex_unlock(&wilc->cfg_cmd_lock); 1324 1325 return ret_size; 1326 } 1327 1328 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit, 1329 u32 drv_handler) 1330 { 1331 u32 offset; 1332 int ret_size; 1333 struct wilc *wilc = vif->wilc; 1334 1335 mutex_lock(&wilc->cfg_cmd_lock); 1336 1337 if (start) 1338 wilc->cfg_frame_offset = 0; 1339 1340 offset = wilc->cfg_frame_offset; 1341 ret_size = wilc_wlan_cfg_get_wid(wilc->cfg_frame.frame, offset, wid); 1342 offset += ret_size; 1343 wilc->cfg_frame_offset = offset; 1344 1345 if (!commit) { 1346 mutex_unlock(&wilc->cfg_cmd_lock); 1347 return ret_size; 1348 } 1349 1350 if (wilc_wlan_cfg_commit(vif, WILC_CFG_QUERY, drv_handler)) 1351 ret_size = 0; 1352 1353 if (!wait_for_completion_timeout(&wilc->cfg_event, 1354 WILC_CFG_PKTS_TIMEOUT)) { 1355 netdev_dbg(vif->ndev, "%s: Timed Out\n", __func__); 1356 ret_size = 0; 1357 } 1358 wilc->cfg_frame_offset = 0; 1359 wilc->cfg_seq_no += 1; 1360 mutex_unlock(&wilc->cfg_cmd_lock); 1361 1362 return ret_size; 1363 } 1364 1365 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids, 1366 u32 count) 1367 { 1368 int i; 1369 int ret = 0; 1370 u32 drv = wilc_get_vif_idx(vif); 1371 1372 if (mode == WILC_GET_CFG) { 1373 for (i = 0; i < count; i++) { 1374 if (!wilc_wlan_cfg_get(vif, !i, 1375 wids[i].id, 1376 (i == count - 1), 1377 drv)) { 1378 ret = -ETIMEDOUT; 1379 break; 1380 } 1381 } 1382 for (i = 0; i < count; i++) { 1383 wids[i].size = wilc_wlan_cfg_get_val(vif->wilc, 1384 wids[i].id, 1385 wids[i].val, 1386 wids[i].size); 1387 } 1388 } else if (mode == WILC_SET_CFG) { 1389 for (i = 0; i < count; i++) { 1390 if (!wilc_wlan_cfg_set(vif, !i, 1391 wids[i].id, 1392 wids[i].val, 1393 wids[i].size, 1394 (i == count - 1), 1395 drv)) { 1396 ret = -ETIMEDOUT; 1397 break; 1398 } 1399 } 1400 } 1401 1402 return ret; 1403 } 1404 1405 static int init_chip(struct net_device *dev) 1406 { 1407 u32 chipid; 1408 u32 reg; 1409 int ret = 0; 1410 struct wilc_vif *vif = netdev_priv(dev); 1411 struct wilc *wilc = vif->wilc; 1412 1413 acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); 1414 1415 chipid = wilc_get_chipid(wilc, true); 1416 1417 if ((chipid & 0xfff) != 0xa0) { 1418 ret = wilc->hif_func->hif_read_reg(wilc, 1419 WILC_CORTUS_RESET_MUX_SEL, 1420 ®); 1421 if (ret) { 1422 netdev_err(dev, "fail read reg 0x1118\n"); 1423 goto release; 1424 } 1425 reg |= BIT(0); 1426 ret = wilc->hif_func->hif_write_reg(wilc, 1427 WILC_CORTUS_RESET_MUX_SEL, 1428 reg); 1429 if (ret) { 1430 netdev_err(dev, "fail write reg 0x1118\n"); 1431 goto release; 1432 } 1433 ret = wilc->hif_func->hif_write_reg(wilc, 1434 WILC_CORTUS_BOOT_REGISTER, 1435 WILC_CORTUS_BOOT_FROM_IRAM); 1436 if (ret) { 1437 netdev_err(dev, "fail write reg 0xc0000\n"); 1438 goto release; 1439 } 1440 } 1441 1442 release: 1443 release_bus(wilc, WILC_BUS_RELEASE_ONLY); 1444 1445 return ret; 1446 } 1447 1448 u32 wilc_get_chipid(struct wilc *wilc, bool update) 1449 { 1450 static u32 chipid; 1451 u32 tempchipid = 0; 1452 u32 rfrevid = 0; 1453 1454 if (chipid == 0 || update) { 1455 wilc->hif_func->hif_read_reg(wilc, WILC_CHIPID, &tempchipid); 1456 wilc->hif_func->hif_read_reg(wilc, WILC_RF_REVISION_ID, 1457 &rfrevid); 1458 if (!is_wilc1000(tempchipid)) { 1459 chipid = 0; 1460 return chipid; 1461 } 1462 if (tempchipid == WILC_1000_BASE_ID_2A) { /* 0x1002A0 */ 1463 if (rfrevid != 0x1) 1464 tempchipid = WILC_1000_BASE_ID_2A_REV1; 1465 } else if (tempchipid == WILC_1000_BASE_ID_2B) { /* 0x1002B0 */ 1466 if (rfrevid == 0x4) 1467 tempchipid = WILC_1000_BASE_ID_2B_REV1; 1468 else if (rfrevid != 0x3) 1469 tempchipid = WILC_1000_BASE_ID_2B_REV2; 1470 } 1471 1472 chipid = tempchipid; 1473 } 1474 return chipid; 1475 } 1476 1477 int wilc_wlan_init(struct net_device *dev) 1478 { 1479 int ret = 0; 1480 struct wilc_vif *vif = netdev_priv(dev); 1481 struct wilc *wilc; 1482 1483 wilc = vif->wilc; 1484 1485 wilc->quit = 0; 1486 1487 if (wilc->hif_func->hif_init(wilc, false)) { 1488 ret = -EIO; 1489 goto fail; 1490 } 1491 1492 if (!wilc->tx_buffer) 1493 wilc->tx_buffer = kmalloc(WILC_TX_BUFF_SIZE, GFP_KERNEL); 1494 1495 if (!wilc->tx_buffer) { 1496 ret = -ENOBUFS; 1497 goto fail; 1498 } 1499 1500 if (!wilc->rx_buffer) 1501 wilc->rx_buffer = kmalloc(WILC_RX_BUFF_SIZE, GFP_KERNEL); 1502 1503 if (!wilc->rx_buffer) { 1504 ret = -ENOBUFS; 1505 goto fail; 1506 } 1507 1508 if (init_chip(dev)) { 1509 ret = -EIO; 1510 goto fail; 1511 } 1512 1513 return 0; 1514 1515 fail: 1516 1517 kfree(wilc->rx_buffer); 1518 wilc->rx_buffer = NULL; 1519 kfree(wilc->tx_buffer); 1520 wilc->tx_buffer = NULL; 1521 1522 return ret; 1523 } 1524