1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4  * All rights reserved.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/spi/spi.h>
9 #include <linux/crc7.h>
10 #include <linux/crc-itu-t.h>
11 #include <linux/gpio/consumer.h>
12 
13 #include "netdev.h"
14 #include "cfg80211.h"
15 
16 #define SPI_MODALIAS		"wilc1000_spi"
17 
18 static bool enable_crc7;	/* protect SPI commands with CRC7 */
19 module_param(enable_crc7, bool, 0644);
20 MODULE_PARM_DESC(enable_crc7,
21 		 "Enable CRC7 checksum to protect command transfers\n"
22 		 "\t\t\tagainst corruption during the SPI transfer.\n"
23 		 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
24 		 "\t\t\tof enabling this is small.");
25 
26 static bool enable_crc16;	/* protect SPI data with CRC16 */
27 module_param(enable_crc16, bool, 0644);
28 MODULE_PARM_DESC(enable_crc16,
29 		 "Enable CRC16 checksum to protect data transfers\n"
30 		 "\t\t\tagainst corruption during the SPI transfer.\n"
31 		 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
32 		 "\t\t\tof enabling this may be substantial.");
33 
34 /*
35  * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or
36  * more zero bytes between the command response and the DATA Start tag
37  * (0xf3).  This behavior appears to be undocumented in "ATWILC1000
38  * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
39  * zero bytes when the SPI bus operates at 48MHz and none when it
40  * operates at 1MHz.
41  */
42 #define WILC_SPI_RSP_HDR_EXTRA_DATA	8
43 
44 struct wilc_spi {
45 	bool isinit;		/* true if SPI protocol has been configured */
46 	bool probing_crc;	/* true if we're probing chip's CRC config */
47 	bool crc7_enabled;	/* true if crc7 is currently enabled */
48 	bool crc16_enabled;	/* true if crc16 is currently enabled */
49 	struct wilc_gpios {
50 		struct gpio_desc *enable;	/* ENABLE GPIO or NULL */
51 		struct gpio_desc *reset;	/* RESET GPIO or NULL */
52 	} gpios;
53 };
54 
55 static const struct wilc_hif_func wilc_hif_spi;
56 
57 static int wilc_spi_reset(struct wilc *wilc);
58 
59 /********************************************
60  *
61  *      Spi protocol Function
62  *
63  ********************************************/
64 
65 #define CMD_DMA_WRITE				0xc1
66 #define CMD_DMA_READ				0xc2
67 #define CMD_INTERNAL_WRITE			0xc3
68 #define CMD_INTERNAL_READ			0xc4
69 #define CMD_TERMINATE				0xc5
70 #define CMD_REPEAT				0xc6
71 #define CMD_DMA_EXT_WRITE			0xc7
72 #define CMD_DMA_EXT_READ			0xc8
73 #define CMD_SINGLE_WRITE			0xc9
74 #define CMD_SINGLE_READ				0xca
75 #define CMD_RESET				0xcf
76 
77 #define SPI_ENABLE_VMM_RETRY_LIMIT		2
78 
79 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
80 #define RSP_START_FIELD				GENMASK(7, 4)
81 #define RSP_TYPE_FIELD				GENMASK(3, 0)
82 
83 /* SPI response values for the response fields: */
84 #define RSP_START_TAG				0xc
85 #define RSP_TYPE_FIRST_PACKET			0x1
86 #define RSP_TYPE_INNER_PACKET			0x2
87 #define RSP_TYPE_LAST_PACKET			0x3
88 #define RSP_STATE_NO_ERROR			0x00
89 
90 #define PROTOCOL_REG_PKT_SZ_MASK		GENMASK(6, 4)
91 #define PROTOCOL_REG_CRC16_MASK			GENMASK(3, 3)
92 #define PROTOCOL_REG_CRC7_MASK			GENMASK(2, 2)
93 
94 /*
95  * The SPI data packet size may be any integer power of two in the
96  * range from 256 to 8192 bytes.
97  */
98 #define DATA_PKT_LOG_SZ_MIN			8	/* 256 B */
99 #define DATA_PKT_LOG_SZ_MAX			13	/* 8 KiB */
100 
101 /*
102  * Select the data packet size (log2 of number of bytes): Use the
103  * maximum data packet size.  We only retransmit complete packets, so
104  * there is no benefit from using smaller data packets.
105  */
106 #define DATA_PKT_LOG_SZ				DATA_PKT_LOG_SZ_MAX
107 #define DATA_PKT_SZ				(1 << DATA_PKT_LOG_SZ)
108 
109 #define WILC_SPI_COMMAND_STAT_SUCCESS		0
110 #define WILC_GET_RESP_HDR_START(h)		(((h) >> 4) & 0xf)
111 
112 struct wilc_spi_cmd {
113 	u8 cmd_type;
114 	union {
115 		struct {
116 			u8 addr[3];
117 			u8 crc[];
118 		} __packed simple_cmd;
119 		struct {
120 			u8 addr[3];
121 			u8 size[2];
122 			u8 crc[];
123 		} __packed dma_cmd;
124 		struct {
125 			u8 addr[3];
126 			u8 size[3];
127 			u8 crc[];
128 		} __packed dma_cmd_ext;
129 		struct {
130 			u8 addr[2];
131 			__be32 data;
132 			u8 crc[];
133 		} __packed internal_w_cmd;
134 		struct {
135 			u8 addr[3];
136 			__be32 data;
137 			u8 crc[];
138 		} __packed w_cmd;
139 	} u;
140 } __packed;
141 
142 struct wilc_spi_read_rsp_data {
143 	u8 header;
144 	u8 data[4];
145 	u8 crc[];
146 } __packed;
147 
148 struct wilc_spi_rsp_data {
149 	u8 rsp_cmd_type;
150 	u8 status;
151 	u8 data[];
152 } __packed;
153 
154 struct wilc_spi_special_cmd_rsp {
155 	u8 skip_byte;
156 	u8 rsp_cmd_type;
157 	u8 status;
158 } __packed;
159 
160 static int wilc_parse_gpios(struct wilc *wilc)
161 {
162 	struct spi_device *spi = to_spi_device(wilc->dev);
163 	struct wilc_spi *spi_priv = wilc->bus_data;
164 	struct wilc_gpios *gpios = &spi_priv->gpios;
165 
166 	/* get ENABLE pin and deassert it (if it is defined): */
167 	gpios->enable = devm_gpiod_get_optional(&spi->dev,
168 						"enable", GPIOD_OUT_LOW);
169 	/* get RESET pin and assert it (if it is defined): */
170 	if (gpios->enable) {
171 		/* if enable pin exists, reset must exist as well */
172 		gpios->reset = devm_gpiod_get(&spi->dev,
173 					      "reset", GPIOD_OUT_HIGH);
174 		if (IS_ERR(gpios->reset)) {
175 			dev_err(&spi->dev, "missing reset gpio.\n");
176 			return PTR_ERR(gpios->reset);
177 		}
178 	} else {
179 		gpios->reset = devm_gpiod_get_optional(&spi->dev,
180 						       "reset", GPIOD_OUT_HIGH);
181 	}
182 	return 0;
183 }
184 
185 static void wilc_wlan_power(struct wilc *wilc, bool on)
186 {
187 	struct wilc_spi *spi_priv = wilc->bus_data;
188 	struct wilc_gpios *gpios = &spi_priv->gpios;
189 
190 	if (on) {
191 		/* assert ENABLE: */
192 		gpiod_set_value(gpios->enable, 1);
193 		mdelay(5);
194 		/* deassert RESET: */
195 		gpiod_set_value(gpios->reset, 0);
196 	} else {
197 		/* assert RESET: */
198 		gpiod_set_value(gpios->reset, 1);
199 		/* deassert ENABLE: */
200 		gpiod_set_value(gpios->enable, 0);
201 	}
202 }
203 
204 static int wilc_bus_probe(struct spi_device *spi)
205 {
206 	int ret;
207 	struct wilc *wilc;
208 	struct wilc_spi *spi_priv;
209 
210 	spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
211 	if (!spi_priv)
212 		return -ENOMEM;
213 
214 	ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
215 	if (ret)
216 		goto free;
217 
218 	spi_set_drvdata(spi, wilc);
219 	wilc->dev = &spi->dev;
220 	wilc->bus_data = spi_priv;
221 	wilc->dev_irq_num = spi->irq;
222 
223 	ret = wilc_parse_gpios(wilc);
224 	if (ret < 0)
225 		goto netdev_cleanup;
226 
227 	wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc");
228 	if (IS_ERR(wilc->rtc_clk)) {
229 		ret = PTR_ERR(wilc->rtc_clk);
230 		goto netdev_cleanup;
231 	}
232 	clk_prepare_enable(wilc->rtc_clk);
233 
234 	return 0;
235 
236 netdev_cleanup:
237 	wilc_netdev_cleanup(wilc);
238 free:
239 	kfree(spi_priv);
240 	return ret;
241 }
242 
243 static void wilc_bus_remove(struct spi_device *spi)
244 {
245 	struct wilc *wilc = spi_get_drvdata(spi);
246 	struct wilc_spi *spi_priv = wilc->bus_data;
247 
248 	clk_disable_unprepare(wilc->rtc_clk);
249 	wilc_netdev_cleanup(wilc);
250 	kfree(spi_priv);
251 }
252 
253 static const struct of_device_id wilc_of_match[] = {
254 	{ .compatible = "microchip,wilc1000", },
255 	{ /* sentinel */ }
256 };
257 MODULE_DEVICE_TABLE(of, wilc_of_match);
258 
259 static const struct spi_device_id wilc_spi_id[] = {
260 	{ "wilc1000", 0 },
261 	{ /* sentinel */ }
262 };
263 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
264 
265 static struct spi_driver wilc_spi_driver = {
266 	.driver = {
267 		.name = SPI_MODALIAS,
268 		.of_match_table = wilc_of_match,
269 	},
270 	.id_table = wilc_spi_id,
271 	.probe =  wilc_bus_probe,
272 	.remove = wilc_bus_remove,
273 };
274 module_spi_driver(wilc_spi_driver);
275 MODULE_LICENSE("GPL");
276 
277 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
278 {
279 	struct spi_device *spi = to_spi_device(wilc->dev);
280 	int ret;
281 	struct spi_message msg;
282 
283 	if (len > 0 && b) {
284 		struct spi_transfer tr = {
285 			.tx_buf = b,
286 			.len = len,
287 			.delay = {
288 				.value = 0,
289 				.unit = SPI_DELAY_UNIT_USECS
290 			},
291 		};
292 		char *r_buffer = kzalloc(len, GFP_KERNEL);
293 
294 		if (!r_buffer)
295 			return -ENOMEM;
296 
297 		tr.rx_buf = r_buffer;
298 		dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
299 
300 		memset(&msg, 0, sizeof(msg));
301 		spi_message_init(&msg);
302 		msg.spi = spi;
303 		spi_message_add_tail(&tr, &msg);
304 
305 		ret = spi_sync(spi, &msg);
306 		if (ret < 0)
307 			dev_err(&spi->dev, "SPI transaction failed\n");
308 
309 		kfree(r_buffer);
310 	} else {
311 		dev_err(&spi->dev,
312 			"can't write data with the following length: %d\n",
313 			len);
314 		ret = -EINVAL;
315 	}
316 
317 	return ret;
318 }
319 
320 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
321 {
322 	struct spi_device *spi = to_spi_device(wilc->dev);
323 	int ret;
324 
325 	if (rlen > 0) {
326 		struct spi_message msg;
327 		struct spi_transfer tr = {
328 			.rx_buf = rb,
329 			.len = rlen,
330 			.delay = {
331 				.value = 0,
332 				.unit = SPI_DELAY_UNIT_USECS
333 			},
334 
335 		};
336 		char *t_buffer = kzalloc(rlen, GFP_KERNEL);
337 
338 		if (!t_buffer)
339 			return -ENOMEM;
340 
341 		tr.tx_buf = t_buffer;
342 
343 		memset(&msg, 0, sizeof(msg));
344 		spi_message_init(&msg);
345 		msg.spi = spi;
346 		spi_message_add_tail(&tr, &msg);
347 
348 		ret = spi_sync(spi, &msg);
349 		if (ret < 0)
350 			dev_err(&spi->dev, "SPI transaction failed\n");
351 		kfree(t_buffer);
352 	} else {
353 		dev_err(&spi->dev,
354 			"can't read data with the following length: %u\n",
355 			rlen);
356 		ret = -EINVAL;
357 	}
358 
359 	return ret;
360 }
361 
362 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
363 {
364 	struct spi_device *spi = to_spi_device(wilc->dev);
365 	int ret;
366 
367 	if (rlen > 0) {
368 		struct spi_message msg;
369 		struct spi_transfer tr = {
370 			.rx_buf = rb,
371 			.tx_buf = wb,
372 			.len = rlen,
373 			.bits_per_word = 8,
374 			.delay = {
375 				.value = 0,
376 				.unit = SPI_DELAY_UNIT_USECS
377 			},
378 
379 		};
380 
381 		memset(&msg, 0, sizeof(msg));
382 		spi_message_init(&msg);
383 		msg.spi = spi;
384 
385 		spi_message_add_tail(&tr, &msg);
386 		ret = spi_sync(spi, &msg);
387 		if (ret < 0)
388 			dev_err(&spi->dev, "SPI transaction failed\n");
389 	} else {
390 		dev_err(&spi->dev,
391 			"can't read data with the following length: %u\n",
392 			rlen);
393 		ret = -EINVAL;
394 	}
395 
396 	return ret;
397 }
398 
399 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
400 {
401 	struct spi_device *spi = to_spi_device(wilc->dev);
402 	struct wilc_spi *spi_priv = wilc->bus_data;
403 	int ix, nbytes;
404 	int result = 0;
405 	u8 cmd, order, crc[2];
406 	u16 crc_calc;
407 
408 	/*
409 	 * Data
410 	 */
411 	ix = 0;
412 	do {
413 		if (sz <= DATA_PKT_SZ) {
414 			nbytes = sz;
415 			order = 0x3;
416 		} else {
417 			nbytes = DATA_PKT_SZ;
418 			if (ix == 0)
419 				order = 0x1;
420 			else
421 				order = 0x02;
422 		}
423 
424 		/*
425 		 * Write command
426 		 */
427 		cmd = 0xf0;
428 		cmd |= order;
429 
430 		if (wilc_spi_tx(wilc, &cmd, 1)) {
431 			dev_err(&spi->dev,
432 				"Failed data block cmd write, bus error...\n");
433 			result = -EINVAL;
434 			break;
435 		}
436 
437 		/*
438 		 * Write data
439 		 */
440 		if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
441 			dev_err(&spi->dev,
442 				"Failed data block write, bus error...\n");
443 			result = -EINVAL;
444 			break;
445 		}
446 
447 		/*
448 		 * Write CRC
449 		 */
450 		if (spi_priv->crc16_enabled) {
451 			crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
452 			crc[0] = crc_calc >> 8;
453 			crc[1] = crc_calc;
454 			if (wilc_spi_tx(wilc, crc, 2)) {
455 				dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
456 				result = -EINVAL;
457 				break;
458 			}
459 		}
460 
461 		/*
462 		 * No need to wait for response
463 		 */
464 		ix += nbytes;
465 		sz -= nbytes;
466 	} while (sz);
467 
468 	return result;
469 }
470 
471 /********************************************
472  *
473  *      Spi Internal Read/Write Function
474  *
475  ********************************************/
476 static u8 wilc_get_crc7(u8 *buffer, u32 len)
477 {
478 	return crc7_be(0xfe, buffer, len);
479 }
480 
481 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
482 				u8 clockless)
483 {
484 	struct spi_device *spi = to_spi_device(wilc->dev);
485 	struct wilc_spi *spi_priv = wilc->bus_data;
486 	u8 wb[32], rb[32];
487 	int cmd_len, resp_len, i;
488 	u16 crc_calc, crc_recv;
489 	struct wilc_spi_cmd *c;
490 	struct wilc_spi_rsp_data *r;
491 	struct wilc_spi_read_rsp_data *r_data;
492 
493 	memset(wb, 0x0, sizeof(wb));
494 	memset(rb, 0x0, sizeof(rb));
495 	c = (struct wilc_spi_cmd *)wb;
496 	c->cmd_type = cmd;
497 	if (cmd == CMD_SINGLE_READ) {
498 		c->u.simple_cmd.addr[0] = adr >> 16;
499 		c->u.simple_cmd.addr[1] = adr >> 8;
500 		c->u.simple_cmd.addr[2] = adr;
501 	} else if (cmd == CMD_INTERNAL_READ) {
502 		c->u.simple_cmd.addr[0] = adr >> 8;
503 		if (clockless == 1)
504 			c->u.simple_cmd.addr[0] |= BIT(7);
505 		c->u.simple_cmd.addr[1] = adr;
506 		c->u.simple_cmd.addr[2] = 0x0;
507 	} else {
508 		dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
509 		return -EINVAL;
510 	}
511 
512 	cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
513 	resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA;
514 
515 	if (spi_priv->crc7_enabled) {
516 		c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
517 		cmd_len += 1;
518 		resp_len += 2;
519 	}
520 
521 	if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
522 		dev_err(&spi->dev,
523 			"spi buffer size too small (%d) (%d) (%zu)\n",
524 			cmd_len, resp_len, ARRAY_SIZE(wb));
525 		return -EINVAL;
526 	}
527 
528 	if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
529 		dev_err(&spi->dev, "Failed cmd write, bus error...\n");
530 		return -EINVAL;
531 	}
532 
533 	r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
534 	if (r->rsp_cmd_type != cmd && !clockless) {
535 		if (!spi_priv->probing_crc)
536 			dev_err(&spi->dev,
537 				"Failed cmd, cmd (%02x), resp (%02x)\n",
538 				cmd, r->rsp_cmd_type);
539 		return -EINVAL;
540 	}
541 
542 	if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
543 		dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
544 			r->status);
545 		return -EINVAL;
546 	}
547 
548 	for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i)
549 		if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf)
550 			break;
551 
552 	if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) {
553 		dev_err(&spi->dev, "Error, data start missing\n");
554 		return -EINVAL;
555 	}
556 
557 	r_data = (struct wilc_spi_read_rsp_data *)&r->data[i];
558 
559 	if (b)
560 		memcpy(b, r_data->data, 4);
561 
562 	if (!clockless && spi_priv->crc16_enabled) {
563 		crc_recv = (r_data->crc[0] << 8) | r_data->crc[1];
564 		crc_calc = crc_itu_t(0xffff, r_data->data, 4);
565 		if (crc_recv != crc_calc) {
566 			dev_err(&spi->dev, "%s: bad CRC 0x%04x "
567 				"(calculated 0x%04x)\n", __func__,
568 				crc_recv, crc_calc);
569 			return -EINVAL;
570 		}
571 	}
572 
573 	return 0;
574 }
575 
576 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
577 			      u8 clockless)
578 {
579 	struct spi_device *spi = to_spi_device(wilc->dev);
580 	struct wilc_spi *spi_priv = wilc->bus_data;
581 	u8 wb[32], rb[32];
582 	int cmd_len, resp_len;
583 	struct wilc_spi_cmd *c;
584 	struct wilc_spi_rsp_data *r;
585 
586 	memset(wb, 0x0, sizeof(wb));
587 	memset(rb, 0x0, sizeof(rb));
588 	c = (struct wilc_spi_cmd *)wb;
589 	c->cmd_type = cmd;
590 	if (cmd == CMD_INTERNAL_WRITE) {
591 		c->u.internal_w_cmd.addr[0] = adr >> 8;
592 		if (clockless == 1)
593 			c->u.internal_w_cmd.addr[0] |= BIT(7);
594 
595 		c->u.internal_w_cmd.addr[1] = adr;
596 		c->u.internal_w_cmd.data = cpu_to_be32(data);
597 		cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
598 		if (spi_priv->crc7_enabled)
599 			c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
600 	} else if (cmd == CMD_SINGLE_WRITE) {
601 		c->u.w_cmd.addr[0] = adr >> 16;
602 		c->u.w_cmd.addr[1] = adr >> 8;
603 		c->u.w_cmd.addr[2] = adr;
604 		c->u.w_cmd.data = cpu_to_be32(data);
605 		cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
606 		if (spi_priv->crc7_enabled)
607 			c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
608 	} else {
609 		dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
610 		return -EINVAL;
611 	}
612 
613 	if (spi_priv->crc7_enabled)
614 		cmd_len += 1;
615 
616 	resp_len = sizeof(*r);
617 
618 	if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
619 		dev_err(&spi->dev,
620 			"spi buffer size too small (%d) (%d) (%zu)\n",
621 			cmd_len, resp_len, ARRAY_SIZE(wb));
622 		return -EINVAL;
623 	}
624 
625 	if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
626 		dev_err(&spi->dev, "Failed cmd write, bus error...\n");
627 		return -EINVAL;
628 	}
629 
630 	r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
631 	/*
632 	 * Clockless registers operations might return unexptected responses,
633 	 * even if successful.
634 	 */
635 	if (r->rsp_cmd_type != cmd && !clockless) {
636 		dev_err(&spi->dev,
637 			"Failed cmd response, cmd (%02x), resp (%02x)\n",
638 			cmd, r->rsp_cmd_type);
639 		return -EINVAL;
640 	}
641 
642 	if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
643 		dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
644 			r->status);
645 		return -EINVAL;
646 	}
647 
648 	return 0;
649 }
650 
651 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
652 {
653 	struct spi_device *spi = to_spi_device(wilc->dev);
654 	struct wilc_spi *spi_priv = wilc->bus_data;
655 	u16 crc_recv, crc_calc;
656 	u8 wb[32], rb[32];
657 	int cmd_len, resp_len;
658 	int retry, ix = 0;
659 	u8 crc[2];
660 	struct wilc_spi_cmd *c;
661 	struct wilc_spi_rsp_data *r;
662 
663 	memset(wb, 0x0, sizeof(wb));
664 	memset(rb, 0x0, sizeof(rb));
665 	c = (struct wilc_spi_cmd *)wb;
666 	c->cmd_type = cmd;
667 	if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
668 		c->u.dma_cmd.addr[0] = adr >> 16;
669 		c->u.dma_cmd.addr[1] = adr >> 8;
670 		c->u.dma_cmd.addr[2] = adr;
671 		c->u.dma_cmd.size[0] = sz >> 8;
672 		c->u.dma_cmd.size[1] = sz;
673 		cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
674 		if (spi_priv->crc7_enabled)
675 			c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
676 	} else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
677 		c->u.dma_cmd_ext.addr[0] = adr >> 16;
678 		c->u.dma_cmd_ext.addr[1] = adr >> 8;
679 		c->u.dma_cmd_ext.addr[2] = adr;
680 		c->u.dma_cmd_ext.size[0] = sz >> 16;
681 		c->u.dma_cmd_ext.size[1] = sz >> 8;
682 		c->u.dma_cmd_ext.size[2] = sz;
683 		cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
684 		if (spi_priv->crc7_enabled)
685 			c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
686 	} else {
687 		dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
688 			cmd);
689 		return -EINVAL;
690 	}
691 	if (spi_priv->crc7_enabled)
692 		cmd_len += 1;
693 
694 	resp_len = sizeof(*r);
695 
696 	if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
697 		dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
698 			cmd_len, resp_len, ARRAY_SIZE(wb));
699 		return -EINVAL;
700 	}
701 
702 	if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
703 		dev_err(&spi->dev, "Failed cmd write, bus error...\n");
704 		return -EINVAL;
705 	}
706 
707 	r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
708 	if (r->rsp_cmd_type != cmd) {
709 		dev_err(&spi->dev,
710 			"Failed cmd response, cmd (%02x), resp (%02x)\n",
711 			cmd, r->rsp_cmd_type);
712 		return -EINVAL;
713 	}
714 
715 	if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
716 		dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
717 			r->status);
718 		return -EINVAL;
719 	}
720 
721 	if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
722 		return 0;
723 
724 	while (sz > 0) {
725 		int nbytes;
726 		u8 rsp;
727 
728 		nbytes = min_t(u32, sz, DATA_PKT_SZ);
729 
730 		/*
731 		 * Data Response header
732 		 */
733 		retry = 100;
734 		do {
735 			if (wilc_spi_rx(wilc, &rsp, 1)) {
736 				dev_err(&spi->dev,
737 					"Failed resp read, bus err\n");
738 				return -EINVAL;
739 			}
740 			if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
741 				break;
742 		} while (retry--);
743 
744 		/*
745 		 * Read bytes
746 		 */
747 		if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
748 			dev_err(&spi->dev,
749 				"Failed block read, bus err\n");
750 			return -EINVAL;
751 		}
752 
753 		/*
754 		 * Read CRC
755 		 */
756 		if (spi_priv->crc16_enabled) {
757 			if (wilc_spi_rx(wilc, crc, 2)) {
758 				dev_err(&spi->dev,
759 					"Failed block CRC read, bus err\n");
760 				return -EINVAL;
761 			}
762 			crc_recv = (crc[0] << 8) | crc[1];
763 			crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
764 			if (crc_recv != crc_calc) {
765 				dev_err(&spi->dev, "%s: bad CRC 0x%04x "
766 					"(calculated 0x%04x)\n", __func__,
767 					crc_recv, crc_calc);
768 				return -EINVAL;
769 			}
770 		}
771 
772 		ix += nbytes;
773 		sz -= nbytes;
774 	}
775 	return 0;
776 }
777 
778 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
779 {
780 	struct spi_device *spi = to_spi_device(wilc->dev);
781 	struct wilc_spi *spi_priv = wilc->bus_data;
782 	u8 wb[32], rb[32];
783 	int cmd_len, resp_len = 0;
784 	struct wilc_spi_cmd *c;
785 	struct wilc_spi_special_cmd_rsp *r;
786 
787 	if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET)
788 		return -EINVAL;
789 
790 	memset(wb, 0x0, sizeof(wb));
791 	memset(rb, 0x0, sizeof(rb));
792 	c = (struct wilc_spi_cmd *)wb;
793 	c->cmd_type = cmd;
794 
795 	if (cmd == CMD_RESET)
796 		memset(c->u.simple_cmd.addr, 0xFF, 3);
797 
798 	cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
799 	resp_len = sizeof(*r);
800 
801 	if (spi_priv->crc7_enabled) {
802 		c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
803 		cmd_len += 1;
804 	}
805 	if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
806 		dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n",
807 			cmd_len, resp_len, ARRAY_SIZE(wb));
808 		return -EINVAL;
809 	}
810 
811 	if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
812 		dev_err(&spi->dev, "Failed cmd write, bus error...\n");
813 		return -EINVAL;
814 	}
815 
816 	r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len];
817 	if (r->rsp_cmd_type != cmd) {
818 		if (!spi_priv->probing_crc)
819 			dev_err(&spi->dev,
820 				"Failed cmd response, cmd (%02x), resp (%02x)\n",
821 				cmd, r->rsp_cmd_type);
822 		return -EINVAL;
823 	}
824 
825 	if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
826 		dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
827 			r->status);
828 		return -EINVAL;
829 	}
830 	return 0;
831 }
832 
833 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
834 {
835 	struct spi_device *spi = to_spi_device(wilc->dev);
836 	int result;
837 	u8 cmd = CMD_SINGLE_READ;
838 	u8 clockless = 0;
839 
840 	if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
841 		/* Clockless register */
842 		cmd = CMD_INTERNAL_READ;
843 		clockless = 1;
844 	}
845 
846 	result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
847 	if (result) {
848 		dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
849 		return result;
850 	}
851 
852 	le32_to_cpus(data);
853 
854 	return 0;
855 }
856 
857 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
858 {
859 	struct spi_device *spi = to_spi_device(wilc->dev);
860 	int result;
861 
862 	if (size <= 4)
863 		return -EINVAL;
864 
865 	result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
866 	if (result) {
867 		dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
868 		return result;
869 	}
870 
871 	return 0;
872 }
873 
874 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
875 {
876 	struct spi_device *spi = to_spi_device(wilc->dev);
877 	int result;
878 
879 	result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
880 	if (result) {
881 		dev_err(&spi->dev, "Failed internal write cmd...\n");
882 		return result;
883 	}
884 
885 	return 0;
886 }
887 
888 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
889 {
890 	struct spi_device *spi = to_spi_device(wilc->dev);
891 	struct wilc_spi *spi_priv = wilc->bus_data;
892 	int result;
893 
894 	result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
895 	if (result) {
896 		if (!spi_priv->probing_crc)
897 			dev_err(&spi->dev, "Failed internal read cmd...\n");
898 		return result;
899 	}
900 
901 	le32_to_cpus(data);
902 
903 	return 0;
904 }
905 
906 /********************************************
907  *
908  *      Spi interfaces
909  *
910  ********************************************/
911 
912 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
913 {
914 	struct spi_device *spi = to_spi_device(wilc->dev);
915 	int result;
916 	u8 cmd = CMD_SINGLE_WRITE;
917 	u8 clockless = 0;
918 
919 	if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
920 		/* Clockless register */
921 		cmd = CMD_INTERNAL_WRITE;
922 		clockless = 1;
923 	}
924 
925 	result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
926 	if (result) {
927 		dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
928 		return result;
929 	}
930 
931 	return 0;
932 }
933 
934 static int spi_data_rsp(struct wilc *wilc, u8 cmd)
935 {
936 	struct spi_device *spi = to_spi_device(wilc->dev);
937 	int result, i;
938 	u8 rsp[4];
939 
940 	/*
941 	 * The response to data packets is two bytes long.  For
942 	 * efficiency's sake, wilc_spi_write() wisely ignores the
943 	 * responses for all packets but the final one.  The downside
944 	 * of that optimization is that when the final data packet is
945 	 * short, we may receive (part of) the response to the
946 	 * second-to-last packet before the one for the final packet.
947 	 * To handle this, we always read 4 bytes and then search for
948 	 * the last byte that contains the "Response Start" code (0xc
949 	 * in the top 4 bits).  We then know that this byte is the
950 	 * first response byte of the final data packet.
951 	 */
952 	result = wilc_spi_rx(wilc, rsp, sizeof(rsp));
953 	if (result) {
954 		dev_err(&spi->dev, "Failed bus error...\n");
955 		return result;
956 	}
957 
958 	for (i = sizeof(rsp) - 2; i >= 0; --i)
959 		if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG)
960 			break;
961 
962 	if (i < 0) {
963 		dev_err(&spi->dev,
964 			"Data packet response missing (%02x %02x %02x %02x)\n",
965 			rsp[0], rsp[1], rsp[2], rsp[3]);
966 		return -1;
967 	}
968 
969 	/* rsp[i] is the last response start byte */
970 
971 	if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET
972 	    || rsp[i + 1] != RSP_STATE_NO_ERROR) {
973 		dev_err(&spi->dev, "Data response error (%02x %02x)\n",
974 			rsp[i], rsp[i + 1]);
975 		return -1;
976 	}
977 	return 0;
978 }
979 
980 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
981 {
982 	struct spi_device *spi = to_spi_device(wilc->dev);
983 	int result;
984 
985 	/*
986 	 * has to be greated than 4
987 	 */
988 	if (size <= 4)
989 		return -EINVAL;
990 
991 	result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
992 	if (result) {
993 		dev_err(&spi->dev,
994 			"Failed cmd, write block (%08x)...\n", addr);
995 		return result;
996 	}
997 
998 	/*
999 	 * Data
1000 	 */
1001 	result = spi_data_write(wilc, buf, size);
1002 	if (result) {
1003 		dev_err(&spi->dev, "Failed block data write...\n");
1004 		return result;
1005 	}
1006 
1007 	/*
1008 	 * Data response
1009 	 */
1010 	return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
1011 }
1012 
1013 /********************************************
1014  *
1015  *      Bus interfaces
1016  *
1017  ********************************************/
1018 
1019 static int wilc_spi_reset(struct wilc *wilc)
1020 {
1021 	struct spi_device *spi = to_spi_device(wilc->dev);
1022 	struct wilc_spi *spi_priv = wilc->bus_data;
1023 	int result;
1024 
1025 	result = wilc_spi_special_cmd(wilc, CMD_RESET);
1026 	if (result && !spi_priv->probing_crc)
1027 		dev_err(&spi->dev, "Failed cmd reset\n");
1028 
1029 	return result;
1030 }
1031 
1032 static int wilc_spi_deinit(struct wilc *wilc)
1033 {
1034 	struct wilc_spi *spi_priv = wilc->bus_data;
1035 
1036 	spi_priv->isinit = false;
1037 	wilc_wlan_power(wilc, false);
1038 	return 0;
1039 }
1040 
1041 static int wilc_spi_init(struct wilc *wilc, bool resume)
1042 {
1043 	struct spi_device *spi = to_spi_device(wilc->dev);
1044 	struct wilc_spi *spi_priv = wilc->bus_data;
1045 	u32 reg;
1046 	u32 chipid;
1047 	int ret, i;
1048 
1049 	if (spi_priv->isinit) {
1050 		/* Confirm we can read chipid register without error: */
1051 		ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1052 		if (ret == 0)
1053 			return 0;
1054 
1055 		dev_err(&spi->dev, "Fail cmd read chip id...\n");
1056 	}
1057 
1058 	wilc_wlan_power(wilc, true);
1059 
1060 	/*
1061 	 * configure protocol
1062 	 */
1063 
1064 	/*
1065 	 * Infer the CRC settings that are currently in effect.  This
1066 	 * is necessary because we can't be sure that the chip has
1067 	 * been RESET (e.g, after module unload and reload).
1068 	 */
1069 	spi_priv->probing_crc = true;
1070 	spi_priv->crc7_enabled = enable_crc7;
1071 	spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */
1072 	for (i = 0; i < 2; ++i) {
1073 		ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
1074 		if (ret == 0)
1075 			break;
1076 		spi_priv->crc7_enabled = !enable_crc7;
1077 	}
1078 	if (ret) {
1079 		dev_err(&spi->dev, "Failed with CRC7 on and off.\n");
1080 		return ret;
1081 	}
1082 
1083 	/* set up the desired CRC configuration: */
1084 	reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK);
1085 	if (enable_crc7)
1086 		reg |= PROTOCOL_REG_CRC7_MASK;
1087 	if (enable_crc16)
1088 		reg |= PROTOCOL_REG_CRC16_MASK;
1089 
1090 	/* set up the data packet size: */
1091 	BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN
1092 		     || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX);
1093 	reg &= ~PROTOCOL_REG_PKT_SZ_MASK;
1094 	reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK,
1095 			  DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN);
1096 
1097 	/* establish the new setup: */
1098 	ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
1099 	if (ret) {
1100 		dev_err(&spi->dev,
1101 			"[wilc spi %d]: Failed internal write reg\n",
1102 			__LINE__);
1103 		return ret;
1104 	}
1105 	/* update our state to match new protocol settings: */
1106 	spi_priv->crc7_enabled = enable_crc7;
1107 	spi_priv->crc16_enabled = enable_crc16;
1108 
1109 	/* re-read to make sure new settings are in effect: */
1110 	spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg);
1111 
1112 	spi_priv->probing_crc = false;
1113 
1114 	/*
1115 	 * make sure can read chip id without protocol error
1116 	 */
1117 	ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1118 	if (ret) {
1119 		dev_err(&spi->dev, "Fail cmd read chip id...\n");
1120 		return ret;
1121 	}
1122 
1123 	spi_priv->isinit = true;
1124 
1125 	return 0;
1126 }
1127 
1128 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
1129 {
1130 	int ret;
1131 
1132 	ret = spi_internal_read(wilc,
1133 				WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
1134 	*size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
1135 
1136 	return ret;
1137 }
1138 
1139 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
1140 {
1141 	return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
1142 				 int_status);
1143 }
1144 
1145 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1146 {
1147 	int ret;
1148 	int retry = SPI_ENABLE_VMM_RETRY_LIMIT;
1149 	u32 check;
1150 
1151 	while (retry) {
1152 		ret = spi_internal_write(wilc,
1153 					 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1154 					 val);
1155 		if (ret)
1156 			break;
1157 
1158 		ret = spi_internal_read(wilc,
1159 					WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1160 					&check);
1161 		if (ret || ((check & EN_VMM) == (val & EN_VMM)))
1162 			break;
1163 
1164 		retry--;
1165 	}
1166 	return ret;
1167 }
1168 
1169 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1170 {
1171 	struct spi_device *spi = to_spi_device(wilc->dev);
1172 	u32 reg;
1173 	int ret, i;
1174 
1175 	if (nint > MAX_NUM_INT) {
1176 		dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1177 		return -EINVAL;
1178 	}
1179 
1180 	/*
1181 	 * interrupt pin mux select
1182 	 */
1183 	ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1184 	if (ret) {
1185 		dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1186 			WILC_PIN_MUX_0);
1187 		return ret;
1188 	}
1189 	reg |= BIT(8);
1190 	ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1191 	if (ret) {
1192 		dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1193 			WILC_PIN_MUX_0);
1194 		return ret;
1195 	}
1196 
1197 	/*
1198 	 * interrupt enable
1199 	 */
1200 	ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1201 	if (ret) {
1202 		dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1203 			WILC_INTR_ENABLE);
1204 		return ret;
1205 	}
1206 
1207 	for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1208 		reg |= (BIT((27 + i)));
1209 
1210 	ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1211 	if (ret) {
1212 		dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1213 			WILC_INTR_ENABLE);
1214 		return ret;
1215 	}
1216 	if (nint) {
1217 		ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1218 		if (ret) {
1219 			dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1220 				WILC_INTR2_ENABLE);
1221 			return ret;
1222 		}
1223 
1224 		for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1225 			reg |= BIT(i);
1226 
1227 		ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg);
1228 		if (ret) {
1229 			dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1230 				WILC_INTR2_ENABLE);
1231 			return ret;
1232 		}
1233 	}
1234 
1235 	return 0;
1236 }
1237 
1238 /* Global spi HIF function table */
1239 static const struct wilc_hif_func wilc_hif_spi = {
1240 	.hif_init = wilc_spi_init,
1241 	.hif_deinit = wilc_spi_deinit,
1242 	.hif_read_reg = wilc_spi_read_reg,
1243 	.hif_write_reg = wilc_spi_write_reg,
1244 	.hif_block_rx = wilc_spi_read,
1245 	.hif_block_tx = wilc_spi_write,
1246 	.hif_read_int = wilc_spi_read_int,
1247 	.hif_clear_int_ext = wilc_spi_clear_int_ext,
1248 	.hif_read_size = wilc_spi_read_size,
1249 	.hif_block_tx_ext = wilc_spi_write,
1250 	.hif_block_rx_ext = wilc_spi_read,
1251 	.hif_sync_ext = wilc_spi_sync_ext,
1252 	.hif_reset = wilc_spi_reset,
1253 };
1254