1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 #include <linux/crc-itu-t.h> 11 12 #include "netdev.h" 13 #include "cfg80211.h" 14 15 static bool enable_crc7; /* protect SPI commands with CRC7 */ 16 module_param(enable_crc7, bool, 0644); 17 MODULE_PARM_DESC(enable_crc7, 18 "Enable CRC7 checksum to protect command transfers\n" 19 "\t\t\tagainst corruption during the SPI transfer.\n" 20 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 21 "\t\t\tof enabling this is small."); 22 23 static bool enable_crc16; /* protect SPI data with CRC16 */ 24 module_param(enable_crc16, bool, 0644); 25 MODULE_PARM_DESC(enable_crc16, 26 "Enable CRC16 checksum to protect data transfers\n" 27 "\t\t\tagainst corruption during the SPI transfer.\n" 28 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 29 "\t\t\tof enabling this may be substantial."); 30 31 /* 32 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 33 * more zero bytes between the command response and the DATA Start tag 34 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 35 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 36 * zero bytes when the SPI bus operates at 48MHz and none when it 37 * operates at 1MHz. 38 */ 39 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 40 41 struct wilc_spi { 42 bool probing_crc; /* true if we're probing chip's CRC config */ 43 bool crc7_enabled; /* true if crc7 is currently enabled */ 44 bool crc16_enabled; /* true if crc16 is currently enabled */ 45 }; 46 47 static const struct wilc_hif_func wilc_hif_spi; 48 49 /******************************************** 50 * 51 * Spi protocol Function 52 * 53 ********************************************/ 54 55 #define CMD_DMA_WRITE 0xc1 56 #define CMD_DMA_READ 0xc2 57 #define CMD_INTERNAL_WRITE 0xc3 58 #define CMD_INTERNAL_READ 0xc4 59 #define CMD_TERMINATE 0xc5 60 #define CMD_REPEAT 0xc6 61 #define CMD_DMA_EXT_WRITE 0xc7 62 #define CMD_DMA_EXT_READ 0xc8 63 #define CMD_SINGLE_WRITE 0xc9 64 #define CMD_SINGLE_READ 0xca 65 #define CMD_RESET 0xcf 66 67 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 68 69 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 70 #define RSP_START_FIELD GENMASK(7, 4) 71 #define RSP_TYPE_FIELD GENMASK(3, 0) 72 73 /* SPI response values for the response fields: */ 74 #define RSP_START_TAG 0xc 75 #define RSP_TYPE_FIRST_PACKET 0x1 76 #define RSP_TYPE_INNER_PACKET 0x2 77 #define RSP_TYPE_LAST_PACKET 0x3 78 #define RSP_STATE_NO_ERROR 0x00 79 80 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 81 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 82 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 83 84 /* 85 * The SPI data packet size may be any integer power of two in the 86 * range from 256 to 8192 bytes. 87 */ 88 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 89 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 90 91 /* 92 * Select the data packet size (log2 of number of bytes): Use the 93 * maximum data packet size. We only retransmit complete packets, so 94 * there is no benefit from using smaller data packets. 95 */ 96 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 97 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 98 99 #define USE_SPI_DMA 0 100 101 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 102 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 103 104 struct wilc_spi_cmd { 105 u8 cmd_type; 106 union { 107 struct { 108 u8 addr[3]; 109 u8 crc[]; 110 } __packed simple_cmd; 111 struct { 112 u8 addr[3]; 113 u8 size[2]; 114 u8 crc[]; 115 } __packed dma_cmd; 116 struct { 117 u8 addr[3]; 118 u8 size[3]; 119 u8 crc[]; 120 } __packed dma_cmd_ext; 121 struct { 122 u8 addr[2]; 123 __be32 data; 124 u8 crc[]; 125 } __packed internal_w_cmd; 126 struct { 127 u8 addr[3]; 128 __be32 data; 129 u8 crc[]; 130 } __packed w_cmd; 131 } u; 132 } __packed; 133 134 struct wilc_spi_read_rsp_data { 135 u8 header; 136 u8 data[4]; 137 u8 crc[]; 138 } __packed; 139 140 struct wilc_spi_rsp_data { 141 u8 rsp_cmd_type; 142 u8 status; 143 u8 data[]; 144 } __packed; 145 146 static int wilc_bus_probe(struct spi_device *spi) 147 { 148 int ret; 149 struct wilc *wilc; 150 struct wilc_spi *spi_priv; 151 152 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 153 if (!spi_priv) 154 return -ENOMEM; 155 156 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 157 if (ret) { 158 kfree(spi_priv); 159 return ret; 160 } 161 162 spi_set_drvdata(spi, wilc); 163 wilc->dev = &spi->dev; 164 wilc->bus_data = spi_priv; 165 wilc->dev_irq_num = spi->irq; 166 167 wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk"); 168 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) { 169 kfree(spi_priv); 170 return -EPROBE_DEFER; 171 } else if (!IS_ERR(wilc->rtc_clk)) 172 clk_prepare_enable(wilc->rtc_clk); 173 174 return 0; 175 } 176 177 static int wilc_bus_remove(struct spi_device *spi) 178 { 179 struct wilc *wilc = spi_get_drvdata(spi); 180 181 if (!IS_ERR(wilc->rtc_clk)) 182 clk_disable_unprepare(wilc->rtc_clk); 183 184 wilc_netdev_cleanup(wilc); 185 return 0; 186 } 187 188 static const struct of_device_id wilc_of_match[] = { 189 { .compatible = "microchip,wilc1000", }, 190 { /* sentinel */ } 191 }; 192 MODULE_DEVICE_TABLE(of, wilc_of_match); 193 194 static struct spi_driver wilc_spi_driver = { 195 .driver = { 196 .name = MODALIAS, 197 .of_match_table = wilc_of_match, 198 }, 199 .probe = wilc_bus_probe, 200 .remove = wilc_bus_remove, 201 }; 202 module_spi_driver(wilc_spi_driver); 203 MODULE_LICENSE("GPL"); 204 205 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 206 { 207 struct spi_device *spi = to_spi_device(wilc->dev); 208 int ret; 209 struct spi_message msg; 210 211 if (len > 0 && b) { 212 struct spi_transfer tr = { 213 .tx_buf = b, 214 .len = len, 215 .delay = { 216 .value = 0, 217 .unit = SPI_DELAY_UNIT_USECS 218 }, 219 }; 220 char *r_buffer = kzalloc(len, GFP_KERNEL); 221 222 if (!r_buffer) 223 return -ENOMEM; 224 225 tr.rx_buf = r_buffer; 226 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 227 228 memset(&msg, 0, sizeof(msg)); 229 spi_message_init(&msg); 230 msg.spi = spi; 231 msg.is_dma_mapped = USE_SPI_DMA; 232 spi_message_add_tail(&tr, &msg); 233 234 ret = spi_sync(spi, &msg); 235 if (ret < 0) 236 dev_err(&spi->dev, "SPI transaction failed\n"); 237 238 kfree(r_buffer); 239 } else { 240 dev_err(&spi->dev, 241 "can't write data with the following length: %d\n", 242 len); 243 ret = -EINVAL; 244 } 245 246 return ret; 247 } 248 249 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 250 { 251 struct spi_device *spi = to_spi_device(wilc->dev); 252 int ret; 253 254 if (rlen > 0) { 255 struct spi_message msg; 256 struct spi_transfer tr = { 257 .rx_buf = rb, 258 .len = rlen, 259 .delay = { 260 .value = 0, 261 .unit = SPI_DELAY_UNIT_USECS 262 }, 263 264 }; 265 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 266 267 if (!t_buffer) 268 return -ENOMEM; 269 270 tr.tx_buf = t_buffer; 271 272 memset(&msg, 0, sizeof(msg)); 273 spi_message_init(&msg); 274 msg.spi = spi; 275 msg.is_dma_mapped = USE_SPI_DMA; 276 spi_message_add_tail(&tr, &msg); 277 278 ret = spi_sync(spi, &msg); 279 if (ret < 0) 280 dev_err(&spi->dev, "SPI transaction failed\n"); 281 kfree(t_buffer); 282 } else { 283 dev_err(&spi->dev, 284 "can't read data with the following length: %u\n", 285 rlen); 286 ret = -EINVAL; 287 } 288 289 return ret; 290 } 291 292 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 293 { 294 struct spi_device *spi = to_spi_device(wilc->dev); 295 int ret; 296 297 if (rlen > 0) { 298 struct spi_message msg; 299 struct spi_transfer tr = { 300 .rx_buf = rb, 301 .tx_buf = wb, 302 .len = rlen, 303 .bits_per_word = 8, 304 .delay = { 305 .value = 0, 306 .unit = SPI_DELAY_UNIT_USECS 307 }, 308 309 }; 310 311 memset(&msg, 0, sizeof(msg)); 312 spi_message_init(&msg); 313 msg.spi = spi; 314 msg.is_dma_mapped = USE_SPI_DMA; 315 316 spi_message_add_tail(&tr, &msg); 317 ret = spi_sync(spi, &msg); 318 if (ret < 0) 319 dev_err(&spi->dev, "SPI transaction failed\n"); 320 } else { 321 dev_err(&spi->dev, 322 "can't read data with the following length: %u\n", 323 rlen); 324 ret = -EINVAL; 325 } 326 327 return ret; 328 } 329 330 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 331 { 332 struct spi_device *spi = to_spi_device(wilc->dev); 333 struct wilc_spi *spi_priv = wilc->bus_data; 334 int ix, nbytes; 335 int result = 0; 336 u8 cmd, order, crc[2]; 337 u16 crc_calc; 338 339 /* 340 * Data 341 */ 342 ix = 0; 343 do { 344 if (sz <= DATA_PKT_SZ) { 345 nbytes = sz; 346 order = 0x3; 347 } else { 348 nbytes = DATA_PKT_SZ; 349 if (ix == 0) 350 order = 0x1; 351 else 352 order = 0x02; 353 } 354 355 /* 356 * Write command 357 */ 358 cmd = 0xf0; 359 cmd |= order; 360 361 if (wilc_spi_tx(wilc, &cmd, 1)) { 362 dev_err(&spi->dev, 363 "Failed data block cmd write, bus error...\n"); 364 result = -EINVAL; 365 break; 366 } 367 368 /* 369 * Write data 370 */ 371 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 372 dev_err(&spi->dev, 373 "Failed data block write, bus error...\n"); 374 result = -EINVAL; 375 break; 376 } 377 378 /* 379 * Write CRC 380 */ 381 if (spi_priv->crc16_enabled) { 382 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 383 crc[0] = crc_calc >> 8; 384 crc[1] = crc_calc; 385 if (wilc_spi_tx(wilc, crc, 2)) { 386 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 387 result = -EINVAL; 388 break; 389 } 390 } 391 392 /* 393 * No need to wait for response 394 */ 395 ix += nbytes; 396 sz -= nbytes; 397 } while (sz); 398 399 return result; 400 } 401 402 /******************************************** 403 * 404 * Spi Internal Read/Write Function 405 * 406 ********************************************/ 407 static u8 wilc_get_crc7(u8 *buffer, u32 len) 408 { 409 return crc7_be(0xfe, buffer, len); 410 } 411 412 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 413 u8 clockless) 414 { 415 struct spi_device *spi = to_spi_device(wilc->dev); 416 struct wilc_spi *spi_priv = wilc->bus_data; 417 u8 wb[32], rb[32]; 418 int cmd_len, resp_len, i; 419 u16 crc_calc, crc_recv; 420 struct wilc_spi_cmd *c; 421 struct wilc_spi_rsp_data *r; 422 struct wilc_spi_read_rsp_data *r_data; 423 424 memset(wb, 0x0, sizeof(wb)); 425 memset(rb, 0x0, sizeof(rb)); 426 c = (struct wilc_spi_cmd *)wb; 427 c->cmd_type = cmd; 428 if (cmd == CMD_SINGLE_READ) { 429 c->u.simple_cmd.addr[0] = adr >> 16; 430 c->u.simple_cmd.addr[1] = adr >> 8; 431 c->u.simple_cmd.addr[2] = adr; 432 } else if (cmd == CMD_INTERNAL_READ) { 433 c->u.simple_cmd.addr[0] = adr >> 8; 434 if (clockless == 1) 435 c->u.simple_cmd.addr[0] |= BIT(7); 436 c->u.simple_cmd.addr[1] = adr; 437 c->u.simple_cmd.addr[2] = 0x0; 438 } else { 439 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 440 return -EINVAL; 441 } 442 443 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 444 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 445 446 if (spi_priv->crc7_enabled) { 447 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 448 cmd_len += 1; 449 resp_len += 2; 450 } 451 452 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 453 dev_err(&spi->dev, 454 "spi buffer size too small (%d) (%d) (%zu)\n", 455 cmd_len, resp_len, ARRAY_SIZE(wb)); 456 return -EINVAL; 457 } 458 459 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 460 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 461 return -EINVAL; 462 } 463 464 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 465 if (r->rsp_cmd_type != cmd) { 466 if (!spi_priv->probing_crc) 467 dev_err(&spi->dev, 468 "Failed cmd, cmd (%02x), resp (%02x)\n", 469 cmd, r->rsp_cmd_type); 470 return -EINVAL; 471 } 472 473 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 474 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 475 r->status); 476 return -EINVAL; 477 } 478 479 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 480 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 481 break; 482 483 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 484 dev_err(&spi->dev, "Error, data start missing\n"); 485 return -EINVAL; 486 } 487 488 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 489 490 if (b) 491 memcpy(b, r_data->data, 4); 492 493 if (!clockless && spi_priv->crc16_enabled) { 494 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 495 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 496 if (crc_recv != crc_calc) { 497 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 498 "(calculated 0x%04x)\n", __func__, 499 crc_recv, crc_calc); 500 return -EINVAL; 501 } 502 } 503 504 return 0; 505 } 506 507 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 508 u8 clockless) 509 { 510 struct spi_device *spi = to_spi_device(wilc->dev); 511 struct wilc_spi *spi_priv = wilc->bus_data; 512 u8 wb[32], rb[32]; 513 int cmd_len, resp_len; 514 struct wilc_spi_cmd *c; 515 struct wilc_spi_rsp_data *r; 516 517 memset(wb, 0x0, sizeof(wb)); 518 memset(rb, 0x0, sizeof(rb)); 519 c = (struct wilc_spi_cmd *)wb; 520 c->cmd_type = cmd; 521 if (cmd == CMD_INTERNAL_WRITE) { 522 c->u.internal_w_cmd.addr[0] = adr >> 8; 523 if (clockless == 1) 524 c->u.internal_w_cmd.addr[0] |= BIT(7); 525 526 c->u.internal_w_cmd.addr[1] = adr; 527 c->u.internal_w_cmd.data = cpu_to_be32(data); 528 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 529 if (spi_priv->crc7_enabled) 530 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 531 } else if (cmd == CMD_SINGLE_WRITE) { 532 c->u.w_cmd.addr[0] = adr >> 16; 533 c->u.w_cmd.addr[1] = adr >> 8; 534 c->u.w_cmd.addr[2] = adr; 535 c->u.w_cmd.data = cpu_to_be32(data); 536 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 537 if (spi_priv->crc7_enabled) 538 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 539 } else { 540 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 541 return -EINVAL; 542 } 543 544 if (spi_priv->crc7_enabled) 545 cmd_len += 1; 546 547 resp_len = sizeof(*r); 548 549 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 550 dev_err(&spi->dev, 551 "spi buffer size too small (%d) (%d) (%zu)\n", 552 cmd_len, resp_len, ARRAY_SIZE(wb)); 553 return -EINVAL; 554 } 555 556 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 557 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 558 return -EINVAL; 559 } 560 561 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 562 if (r->rsp_cmd_type != cmd) { 563 dev_err(&spi->dev, 564 "Failed cmd response, cmd (%02x), resp (%02x)\n", 565 cmd, r->rsp_cmd_type); 566 return -EINVAL; 567 } 568 569 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 570 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 571 r->status); 572 return -EINVAL; 573 } 574 575 return 0; 576 } 577 578 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 579 { 580 struct spi_device *spi = to_spi_device(wilc->dev); 581 struct wilc_spi *spi_priv = wilc->bus_data; 582 u16 crc_recv, crc_calc; 583 u8 wb[32], rb[32]; 584 int cmd_len, resp_len; 585 int retry, ix = 0; 586 u8 crc[2]; 587 struct wilc_spi_cmd *c; 588 struct wilc_spi_rsp_data *r; 589 590 memset(wb, 0x0, sizeof(wb)); 591 memset(rb, 0x0, sizeof(rb)); 592 c = (struct wilc_spi_cmd *)wb; 593 c->cmd_type = cmd; 594 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 595 c->u.dma_cmd.addr[0] = adr >> 16; 596 c->u.dma_cmd.addr[1] = adr >> 8; 597 c->u.dma_cmd.addr[2] = adr; 598 c->u.dma_cmd.size[0] = sz >> 8; 599 c->u.dma_cmd.size[1] = sz; 600 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 601 if (spi_priv->crc7_enabled) 602 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 603 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 604 c->u.dma_cmd_ext.addr[0] = adr >> 16; 605 c->u.dma_cmd_ext.addr[1] = adr >> 8; 606 c->u.dma_cmd_ext.addr[2] = adr; 607 c->u.dma_cmd_ext.size[0] = sz >> 16; 608 c->u.dma_cmd_ext.size[1] = sz >> 8; 609 c->u.dma_cmd_ext.size[2] = sz; 610 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 611 if (spi_priv->crc7_enabled) 612 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 613 } else { 614 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 615 cmd); 616 return -EINVAL; 617 } 618 if (spi_priv->crc7_enabled) 619 cmd_len += 1; 620 621 resp_len = sizeof(*r); 622 623 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 624 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 625 cmd_len, resp_len, ARRAY_SIZE(wb)); 626 return -EINVAL; 627 } 628 629 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 630 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 631 return -EINVAL; 632 } 633 634 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 635 if (r->rsp_cmd_type != cmd) { 636 dev_err(&spi->dev, 637 "Failed cmd response, cmd (%02x), resp (%02x)\n", 638 cmd, r->rsp_cmd_type); 639 return -EINVAL; 640 } 641 642 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 643 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 644 r->status); 645 return -EINVAL; 646 } 647 648 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 649 return 0; 650 651 while (sz > 0) { 652 int nbytes; 653 u8 rsp; 654 655 if (sz <= DATA_PKT_SZ) 656 nbytes = sz; 657 else 658 nbytes = DATA_PKT_SZ; 659 660 /* 661 * Data Response header 662 */ 663 retry = 100; 664 do { 665 if (wilc_spi_rx(wilc, &rsp, 1)) { 666 dev_err(&spi->dev, 667 "Failed resp read, bus err\n"); 668 return -EINVAL; 669 } 670 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 671 break; 672 } while (retry--); 673 674 /* 675 * Read bytes 676 */ 677 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 678 dev_err(&spi->dev, 679 "Failed block read, bus err\n"); 680 return -EINVAL; 681 } 682 683 /* 684 * Read CRC 685 */ 686 if (spi_priv->crc16_enabled) { 687 if (wilc_spi_rx(wilc, crc, 2)) { 688 dev_err(&spi->dev, 689 "Failed block CRC read, bus err\n"); 690 return -EINVAL; 691 } 692 crc_recv = (crc[0] << 8) | crc[1]; 693 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 694 if (crc_recv != crc_calc) { 695 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 696 "(calculated 0x%04x)\n", __func__, 697 crc_recv, crc_calc); 698 return -EINVAL; 699 } 700 } 701 702 ix += nbytes; 703 sz -= nbytes; 704 } 705 return 0; 706 } 707 708 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 709 { 710 struct spi_device *spi = to_spi_device(wilc->dev); 711 int result; 712 u8 cmd = CMD_SINGLE_READ; 713 u8 clockless = 0; 714 715 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 716 /* Clockless register */ 717 cmd = CMD_INTERNAL_READ; 718 clockless = 1; 719 } 720 721 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 722 if (result) { 723 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 724 return result; 725 } 726 727 le32_to_cpus(data); 728 729 return 0; 730 } 731 732 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 733 { 734 struct spi_device *spi = to_spi_device(wilc->dev); 735 int result; 736 737 if (size <= 4) 738 return -EINVAL; 739 740 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); 741 if (result) { 742 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 743 return result; 744 } 745 746 return 0; 747 } 748 749 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 750 { 751 struct spi_device *spi = to_spi_device(wilc->dev); 752 int result; 753 754 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); 755 if (result) { 756 dev_err(&spi->dev, "Failed internal write cmd...\n"); 757 return result; 758 } 759 760 return 0; 761 } 762 763 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 764 { 765 struct spi_device *spi = to_spi_device(wilc->dev); 766 struct wilc_spi *spi_priv = wilc->bus_data; 767 int result; 768 769 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); 770 if (result) { 771 if (!spi_priv->probing_crc) 772 dev_err(&spi->dev, "Failed internal read cmd...\n"); 773 return result; 774 } 775 776 le32_to_cpus(data); 777 778 return 0; 779 } 780 781 /******************************************** 782 * 783 * Spi interfaces 784 * 785 ********************************************/ 786 787 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 788 { 789 struct spi_device *spi = to_spi_device(wilc->dev); 790 int result; 791 u8 cmd = CMD_SINGLE_WRITE; 792 u8 clockless = 0; 793 794 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 795 /* Clockless register */ 796 cmd = CMD_INTERNAL_WRITE; 797 clockless = 1; 798 } 799 800 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 801 if (result) { 802 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 803 return result; 804 } 805 806 return 0; 807 } 808 809 static int spi_data_rsp(struct wilc *wilc, u8 cmd) 810 { 811 struct spi_device *spi = to_spi_device(wilc->dev); 812 int result, i; 813 u8 rsp[4]; 814 815 /* 816 * The response to data packets is two bytes long. For 817 * efficiency's sake, wilc_spi_write() wisely ignores the 818 * responses for all packets but the final one. The downside 819 * of that optimization is that when the final data packet is 820 * short, we may receive (part of) the response to the 821 * second-to-last packet before the one for the final packet. 822 * To handle this, we always read 4 bytes and then search for 823 * the last byte that contains the "Response Start" code (0xc 824 * in the top 4 bits). We then know that this byte is the 825 * first response byte of the final data packet. 826 */ 827 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 828 if (result) { 829 dev_err(&spi->dev, "Failed bus error...\n"); 830 return result; 831 } 832 833 for (i = sizeof(rsp) - 2; i >= 0; --i) 834 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 835 break; 836 837 if (i < 0) { 838 dev_err(&spi->dev, 839 "Data packet response missing (%02x %02x %02x %02x)\n", 840 rsp[0], rsp[1], rsp[2], rsp[3]); 841 return -1; 842 } 843 844 /* rsp[i] is the last response start byte */ 845 846 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 847 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 848 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 849 rsp[i], rsp[i + 1]); 850 return -1; 851 } 852 return 0; 853 } 854 855 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 856 { 857 struct spi_device *spi = to_spi_device(wilc->dev); 858 int result; 859 860 /* 861 * has to be greated than 4 862 */ 863 if (size <= 4) 864 return -EINVAL; 865 866 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); 867 if (result) { 868 dev_err(&spi->dev, 869 "Failed cmd, write block (%08x)...\n", addr); 870 return result; 871 } 872 873 /* 874 * Data 875 */ 876 result = spi_data_write(wilc, buf, size); 877 if (result) { 878 dev_err(&spi->dev, "Failed block data write...\n"); 879 return result; 880 } 881 882 /* 883 * Data response 884 */ 885 return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 886 } 887 888 /******************************************** 889 * 890 * Bus interfaces 891 * 892 ********************************************/ 893 894 static int wilc_spi_deinit(struct wilc *wilc) 895 { 896 /* 897 * TODO: 898 */ 899 return 0; 900 } 901 902 static int wilc_spi_init(struct wilc *wilc, bool resume) 903 { 904 struct spi_device *spi = to_spi_device(wilc->dev); 905 struct wilc_spi *spi_priv = wilc->bus_data; 906 u32 reg; 907 u32 chipid; 908 static int isinit; 909 int ret, i; 910 911 if (isinit) { 912 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 913 if (ret) 914 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 915 916 return ret; 917 } 918 919 /* 920 * configure protocol 921 */ 922 923 /* 924 * Infer the CRC settings that are currently in effect. This 925 * is necessary because we can't be sure that the chip has 926 * been RESET (e.g, after module unload and reload). 927 */ 928 spi_priv->probing_crc = true; 929 spi_priv->crc7_enabled = enable_crc7; 930 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 931 for (i = 0; i < 2; ++i) { 932 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 933 if (ret == 0) 934 break; 935 spi_priv->crc7_enabled = !enable_crc7; 936 } 937 if (ret) { 938 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 939 return ret; 940 } 941 942 /* set up the desired CRC configuration: */ 943 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 944 if (enable_crc7) 945 reg |= PROTOCOL_REG_CRC7_MASK; 946 if (enable_crc16) 947 reg |= PROTOCOL_REG_CRC16_MASK; 948 949 /* set up the data packet size: */ 950 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 951 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 952 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 953 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 954 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 955 956 /* establish the new setup: */ 957 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 958 if (ret) { 959 dev_err(&spi->dev, 960 "[wilc spi %d]: Failed internal write reg\n", 961 __LINE__); 962 return ret; 963 } 964 /* update our state to match new protocol settings: */ 965 spi_priv->crc7_enabled = enable_crc7; 966 spi_priv->crc16_enabled = enable_crc16; 967 968 /* re-read to make sure new settings are in effect: */ 969 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 970 971 spi_priv->probing_crc = false; 972 973 /* 974 * make sure can read back chip id correctly 975 */ 976 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 977 if (ret) { 978 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 979 return ret; 980 } 981 982 isinit = 1; 983 984 return 0; 985 } 986 987 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 988 { 989 int ret; 990 991 ret = spi_internal_read(wilc, 992 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 993 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 994 995 return ret; 996 } 997 998 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 999 { 1000 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1001 int_status); 1002 } 1003 1004 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1005 { 1006 int ret; 1007 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1008 u32 check; 1009 1010 while (retry) { 1011 ret = spi_internal_write(wilc, 1012 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1013 val); 1014 if (ret) 1015 break; 1016 1017 ret = spi_internal_read(wilc, 1018 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1019 &check); 1020 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1021 break; 1022 1023 retry--; 1024 } 1025 return ret; 1026 } 1027 1028 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1029 { 1030 struct spi_device *spi = to_spi_device(wilc->dev); 1031 u32 reg; 1032 int ret, i; 1033 1034 if (nint > MAX_NUM_INT) { 1035 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1036 return -EINVAL; 1037 } 1038 1039 /* 1040 * interrupt pin mux select 1041 */ 1042 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1043 if (ret) { 1044 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1045 WILC_PIN_MUX_0); 1046 return ret; 1047 } 1048 reg |= BIT(8); 1049 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1050 if (ret) { 1051 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1052 WILC_PIN_MUX_0); 1053 return ret; 1054 } 1055 1056 /* 1057 * interrupt enable 1058 */ 1059 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1060 if (ret) { 1061 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1062 WILC_INTR_ENABLE); 1063 return ret; 1064 } 1065 1066 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1067 reg |= (BIT((27 + i))); 1068 1069 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1070 if (ret) { 1071 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1072 WILC_INTR_ENABLE); 1073 return ret; 1074 } 1075 if (nint) { 1076 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1077 if (ret) { 1078 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1079 WILC_INTR2_ENABLE); 1080 return ret; 1081 } 1082 1083 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1084 reg |= BIT(i); 1085 1086 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1087 if (ret) { 1088 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1089 WILC_INTR2_ENABLE); 1090 return ret; 1091 } 1092 } 1093 1094 return 0; 1095 } 1096 1097 /* Global spi HIF function table */ 1098 static const struct wilc_hif_func wilc_hif_spi = { 1099 .hif_init = wilc_spi_init, 1100 .hif_deinit = wilc_spi_deinit, 1101 .hif_read_reg = wilc_spi_read_reg, 1102 .hif_write_reg = wilc_spi_write_reg, 1103 .hif_block_rx = wilc_spi_read, 1104 .hif_block_tx = wilc_spi_write, 1105 .hif_read_int = wilc_spi_read_int, 1106 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1107 .hif_read_size = wilc_spi_read_size, 1108 .hif_block_tx_ext = wilc_spi_write, 1109 .hif_block_rx_ext = wilc_spi_read, 1110 .hif_sync_ext = wilc_spi_sync_ext, 1111 }; 1112