1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 #include <linux/crc-itu-t.h> 11 12 #include "netdev.h" 13 #include "cfg80211.h" 14 15 #define SPI_MODALIAS "wilc1000_spi" 16 17 static bool enable_crc7; /* protect SPI commands with CRC7 */ 18 module_param(enable_crc7, bool, 0644); 19 MODULE_PARM_DESC(enable_crc7, 20 "Enable CRC7 checksum to protect command transfers\n" 21 "\t\t\tagainst corruption during the SPI transfer.\n" 22 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 23 "\t\t\tof enabling this is small."); 24 25 static bool enable_crc16; /* protect SPI data with CRC16 */ 26 module_param(enable_crc16, bool, 0644); 27 MODULE_PARM_DESC(enable_crc16, 28 "Enable CRC16 checksum to protect data transfers\n" 29 "\t\t\tagainst corruption during the SPI transfer.\n" 30 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 31 "\t\t\tof enabling this may be substantial."); 32 33 /* 34 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 35 * more zero bytes between the command response and the DATA Start tag 36 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 37 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 38 * zero bytes when the SPI bus operates at 48MHz and none when it 39 * operates at 1MHz. 40 */ 41 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 42 43 struct wilc_spi { 44 bool isinit; /* true if SPI protocol has been configured */ 45 bool probing_crc; /* true if we're probing chip's CRC config */ 46 bool crc7_enabled; /* true if crc7 is currently enabled */ 47 bool crc16_enabled; /* true if crc16 is currently enabled */ 48 }; 49 50 static const struct wilc_hif_func wilc_hif_spi; 51 52 static int wilc_spi_reset(struct wilc *wilc); 53 54 /******************************************** 55 * 56 * Spi protocol Function 57 * 58 ********************************************/ 59 60 #define CMD_DMA_WRITE 0xc1 61 #define CMD_DMA_READ 0xc2 62 #define CMD_INTERNAL_WRITE 0xc3 63 #define CMD_INTERNAL_READ 0xc4 64 #define CMD_TERMINATE 0xc5 65 #define CMD_REPEAT 0xc6 66 #define CMD_DMA_EXT_WRITE 0xc7 67 #define CMD_DMA_EXT_READ 0xc8 68 #define CMD_SINGLE_WRITE 0xc9 69 #define CMD_SINGLE_READ 0xca 70 #define CMD_RESET 0xcf 71 72 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 73 74 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 75 #define RSP_START_FIELD GENMASK(7, 4) 76 #define RSP_TYPE_FIELD GENMASK(3, 0) 77 78 /* SPI response values for the response fields: */ 79 #define RSP_START_TAG 0xc 80 #define RSP_TYPE_FIRST_PACKET 0x1 81 #define RSP_TYPE_INNER_PACKET 0x2 82 #define RSP_TYPE_LAST_PACKET 0x3 83 #define RSP_STATE_NO_ERROR 0x00 84 85 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 86 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 87 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 88 89 /* 90 * The SPI data packet size may be any integer power of two in the 91 * range from 256 to 8192 bytes. 92 */ 93 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 94 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 95 96 /* 97 * Select the data packet size (log2 of number of bytes): Use the 98 * maximum data packet size. We only retransmit complete packets, so 99 * there is no benefit from using smaller data packets. 100 */ 101 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 102 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 103 104 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 105 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 106 107 struct wilc_spi_cmd { 108 u8 cmd_type; 109 union { 110 struct { 111 u8 addr[3]; 112 u8 crc[]; 113 } __packed simple_cmd; 114 struct { 115 u8 addr[3]; 116 u8 size[2]; 117 u8 crc[]; 118 } __packed dma_cmd; 119 struct { 120 u8 addr[3]; 121 u8 size[3]; 122 u8 crc[]; 123 } __packed dma_cmd_ext; 124 struct { 125 u8 addr[2]; 126 __be32 data; 127 u8 crc[]; 128 } __packed internal_w_cmd; 129 struct { 130 u8 addr[3]; 131 __be32 data; 132 u8 crc[]; 133 } __packed w_cmd; 134 } u; 135 } __packed; 136 137 struct wilc_spi_read_rsp_data { 138 u8 header; 139 u8 data[4]; 140 u8 crc[]; 141 } __packed; 142 143 struct wilc_spi_rsp_data { 144 u8 rsp_cmd_type; 145 u8 status; 146 u8 data[]; 147 } __packed; 148 149 struct wilc_spi_special_cmd_rsp { 150 u8 skip_byte; 151 u8 rsp_cmd_type; 152 u8 status; 153 } __packed; 154 155 static int wilc_bus_probe(struct spi_device *spi) 156 { 157 int ret; 158 struct wilc *wilc; 159 struct wilc_spi *spi_priv; 160 161 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 162 if (!spi_priv) 163 return -ENOMEM; 164 165 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 166 if (ret) 167 goto free; 168 169 spi_set_drvdata(spi, wilc); 170 wilc->dev = &spi->dev; 171 wilc->bus_data = spi_priv; 172 wilc->dev_irq_num = spi->irq; 173 174 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); 175 if (IS_ERR(wilc->rtc_clk)) { 176 ret = PTR_ERR(wilc->rtc_clk); 177 goto netdev_cleanup; 178 } 179 clk_prepare_enable(wilc->rtc_clk); 180 181 return 0; 182 183 netdev_cleanup: 184 wilc_netdev_cleanup(wilc); 185 free: 186 kfree(spi_priv); 187 return ret; 188 } 189 190 static int wilc_bus_remove(struct spi_device *spi) 191 { 192 struct wilc *wilc = spi_get_drvdata(spi); 193 194 clk_disable_unprepare(wilc->rtc_clk); 195 wilc_netdev_cleanup(wilc); 196 197 return 0; 198 } 199 200 static const struct of_device_id wilc_of_match[] = { 201 { .compatible = "microchip,wilc1000", }, 202 { /* sentinel */ } 203 }; 204 MODULE_DEVICE_TABLE(of, wilc_of_match); 205 206 static const struct spi_device_id wilc_spi_id[] = { 207 { "wilc1000", 0 }, 208 { /* sentinel */ } 209 }; 210 MODULE_DEVICE_TABLE(spi, wilc_spi_id); 211 212 static struct spi_driver wilc_spi_driver = { 213 .driver = { 214 .name = SPI_MODALIAS, 215 .of_match_table = wilc_of_match, 216 }, 217 .id_table = wilc_spi_id, 218 .probe = wilc_bus_probe, 219 .remove = wilc_bus_remove, 220 }; 221 module_spi_driver(wilc_spi_driver); 222 MODULE_LICENSE("GPL"); 223 224 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 225 { 226 struct spi_device *spi = to_spi_device(wilc->dev); 227 int ret; 228 struct spi_message msg; 229 230 if (len > 0 && b) { 231 struct spi_transfer tr = { 232 .tx_buf = b, 233 .len = len, 234 .delay = { 235 .value = 0, 236 .unit = SPI_DELAY_UNIT_USECS 237 }, 238 }; 239 char *r_buffer = kzalloc(len, GFP_KERNEL); 240 241 if (!r_buffer) 242 return -ENOMEM; 243 244 tr.rx_buf = r_buffer; 245 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 246 247 memset(&msg, 0, sizeof(msg)); 248 spi_message_init(&msg); 249 msg.spi = spi; 250 spi_message_add_tail(&tr, &msg); 251 252 ret = spi_sync(spi, &msg); 253 if (ret < 0) 254 dev_err(&spi->dev, "SPI transaction failed\n"); 255 256 kfree(r_buffer); 257 } else { 258 dev_err(&spi->dev, 259 "can't write data with the following length: %d\n", 260 len); 261 ret = -EINVAL; 262 } 263 264 return ret; 265 } 266 267 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 268 { 269 struct spi_device *spi = to_spi_device(wilc->dev); 270 int ret; 271 272 if (rlen > 0) { 273 struct spi_message msg; 274 struct spi_transfer tr = { 275 .rx_buf = rb, 276 .len = rlen, 277 .delay = { 278 .value = 0, 279 .unit = SPI_DELAY_UNIT_USECS 280 }, 281 282 }; 283 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 284 285 if (!t_buffer) 286 return -ENOMEM; 287 288 tr.tx_buf = t_buffer; 289 290 memset(&msg, 0, sizeof(msg)); 291 spi_message_init(&msg); 292 msg.spi = spi; 293 spi_message_add_tail(&tr, &msg); 294 295 ret = spi_sync(spi, &msg); 296 if (ret < 0) 297 dev_err(&spi->dev, "SPI transaction failed\n"); 298 kfree(t_buffer); 299 } else { 300 dev_err(&spi->dev, 301 "can't read data with the following length: %u\n", 302 rlen); 303 ret = -EINVAL; 304 } 305 306 return ret; 307 } 308 309 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 310 { 311 struct spi_device *spi = to_spi_device(wilc->dev); 312 int ret; 313 314 if (rlen > 0) { 315 struct spi_message msg; 316 struct spi_transfer tr = { 317 .rx_buf = rb, 318 .tx_buf = wb, 319 .len = rlen, 320 .bits_per_word = 8, 321 .delay = { 322 .value = 0, 323 .unit = SPI_DELAY_UNIT_USECS 324 }, 325 326 }; 327 328 memset(&msg, 0, sizeof(msg)); 329 spi_message_init(&msg); 330 msg.spi = spi; 331 332 spi_message_add_tail(&tr, &msg); 333 ret = spi_sync(spi, &msg); 334 if (ret < 0) 335 dev_err(&spi->dev, "SPI transaction failed\n"); 336 } else { 337 dev_err(&spi->dev, 338 "can't read data with the following length: %u\n", 339 rlen); 340 ret = -EINVAL; 341 } 342 343 return ret; 344 } 345 346 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 347 { 348 struct spi_device *spi = to_spi_device(wilc->dev); 349 struct wilc_spi *spi_priv = wilc->bus_data; 350 int ix, nbytes; 351 int result = 0; 352 u8 cmd, order, crc[2]; 353 u16 crc_calc; 354 355 /* 356 * Data 357 */ 358 ix = 0; 359 do { 360 if (sz <= DATA_PKT_SZ) { 361 nbytes = sz; 362 order = 0x3; 363 } else { 364 nbytes = DATA_PKT_SZ; 365 if (ix == 0) 366 order = 0x1; 367 else 368 order = 0x02; 369 } 370 371 /* 372 * Write command 373 */ 374 cmd = 0xf0; 375 cmd |= order; 376 377 if (wilc_spi_tx(wilc, &cmd, 1)) { 378 dev_err(&spi->dev, 379 "Failed data block cmd write, bus error...\n"); 380 result = -EINVAL; 381 break; 382 } 383 384 /* 385 * Write data 386 */ 387 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 388 dev_err(&spi->dev, 389 "Failed data block write, bus error...\n"); 390 result = -EINVAL; 391 break; 392 } 393 394 /* 395 * Write CRC 396 */ 397 if (spi_priv->crc16_enabled) { 398 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 399 crc[0] = crc_calc >> 8; 400 crc[1] = crc_calc; 401 if (wilc_spi_tx(wilc, crc, 2)) { 402 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 403 result = -EINVAL; 404 break; 405 } 406 } 407 408 /* 409 * No need to wait for response 410 */ 411 ix += nbytes; 412 sz -= nbytes; 413 } while (sz); 414 415 return result; 416 } 417 418 /******************************************** 419 * 420 * Spi Internal Read/Write Function 421 * 422 ********************************************/ 423 static u8 wilc_get_crc7(u8 *buffer, u32 len) 424 { 425 return crc7_be(0xfe, buffer, len); 426 } 427 428 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 429 u8 clockless) 430 { 431 struct spi_device *spi = to_spi_device(wilc->dev); 432 struct wilc_spi *spi_priv = wilc->bus_data; 433 u8 wb[32], rb[32]; 434 int cmd_len, resp_len, i; 435 u16 crc_calc, crc_recv; 436 struct wilc_spi_cmd *c; 437 struct wilc_spi_rsp_data *r; 438 struct wilc_spi_read_rsp_data *r_data; 439 440 memset(wb, 0x0, sizeof(wb)); 441 memset(rb, 0x0, sizeof(rb)); 442 c = (struct wilc_spi_cmd *)wb; 443 c->cmd_type = cmd; 444 if (cmd == CMD_SINGLE_READ) { 445 c->u.simple_cmd.addr[0] = adr >> 16; 446 c->u.simple_cmd.addr[1] = adr >> 8; 447 c->u.simple_cmd.addr[2] = adr; 448 } else if (cmd == CMD_INTERNAL_READ) { 449 c->u.simple_cmd.addr[0] = adr >> 8; 450 if (clockless == 1) 451 c->u.simple_cmd.addr[0] |= BIT(7); 452 c->u.simple_cmd.addr[1] = adr; 453 c->u.simple_cmd.addr[2] = 0x0; 454 } else { 455 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 456 return -EINVAL; 457 } 458 459 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 460 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 461 462 if (spi_priv->crc7_enabled) { 463 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 464 cmd_len += 1; 465 resp_len += 2; 466 } 467 468 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 469 dev_err(&spi->dev, 470 "spi buffer size too small (%d) (%d) (%zu)\n", 471 cmd_len, resp_len, ARRAY_SIZE(wb)); 472 return -EINVAL; 473 } 474 475 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 476 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 477 return -EINVAL; 478 } 479 480 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 481 if (r->rsp_cmd_type != cmd && !clockless) { 482 if (!spi_priv->probing_crc) 483 dev_err(&spi->dev, 484 "Failed cmd, cmd (%02x), resp (%02x)\n", 485 cmd, r->rsp_cmd_type); 486 return -EINVAL; 487 } 488 489 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 490 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 491 r->status); 492 return -EINVAL; 493 } 494 495 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 496 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 497 break; 498 499 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 500 dev_err(&spi->dev, "Error, data start missing\n"); 501 return -EINVAL; 502 } 503 504 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 505 506 if (b) 507 memcpy(b, r_data->data, 4); 508 509 if (!clockless && spi_priv->crc16_enabled) { 510 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 511 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 512 if (crc_recv != crc_calc) { 513 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 514 "(calculated 0x%04x)\n", __func__, 515 crc_recv, crc_calc); 516 return -EINVAL; 517 } 518 } 519 520 return 0; 521 } 522 523 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 524 u8 clockless) 525 { 526 struct spi_device *spi = to_spi_device(wilc->dev); 527 struct wilc_spi *spi_priv = wilc->bus_data; 528 u8 wb[32], rb[32]; 529 int cmd_len, resp_len; 530 struct wilc_spi_cmd *c; 531 struct wilc_spi_rsp_data *r; 532 533 memset(wb, 0x0, sizeof(wb)); 534 memset(rb, 0x0, sizeof(rb)); 535 c = (struct wilc_spi_cmd *)wb; 536 c->cmd_type = cmd; 537 if (cmd == CMD_INTERNAL_WRITE) { 538 c->u.internal_w_cmd.addr[0] = adr >> 8; 539 if (clockless == 1) 540 c->u.internal_w_cmd.addr[0] |= BIT(7); 541 542 c->u.internal_w_cmd.addr[1] = adr; 543 c->u.internal_w_cmd.data = cpu_to_be32(data); 544 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 545 if (spi_priv->crc7_enabled) 546 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 547 } else if (cmd == CMD_SINGLE_WRITE) { 548 c->u.w_cmd.addr[0] = adr >> 16; 549 c->u.w_cmd.addr[1] = adr >> 8; 550 c->u.w_cmd.addr[2] = adr; 551 c->u.w_cmd.data = cpu_to_be32(data); 552 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 553 if (spi_priv->crc7_enabled) 554 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 555 } else { 556 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 557 return -EINVAL; 558 } 559 560 if (spi_priv->crc7_enabled) 561 cmd_len += 1; 562 563 resp_len = sizeof(*r); 564 565 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 566 dev_err(&spi->dev, 567 "spi buffer size too small (%d) (%d) (%zu)\n", 568 cmd_len, resp_len, ARRAY_SIZE(wb)); 569 return -EINVAL; 570 } 571 572 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 573 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 574 return -EINVAL; 575 } 576 577 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 578 /* 579 * Clockless registers operations might return unexptected responses, 580 * even if successful. 581 */ 582 if (r->rsp_cmd_type != cmd && !clockless) { 583 dev_err(&spi->dev, 584 "Failed cmd response, cmd (%02x), resp (%02x)\n", 585 cmd, r->rsp_cmd_type); 586 return -EINVAL; 587 } 588 589 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 590 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 591 r->status); 592 return -EINVAL; 593 } 594 595 return 0; 596 } 597 598 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 599 { 600 struct spi_device *spi = to_spi_device(wilc->dev); 601 struct wilc_spi *spi_priv = wilc->bus_data; 602 u16 crc_recv, crc_calc; 603 u8 wb[32], rb[32]; 604 int cmd_len, resp_len; 605 int retry, ix = 0; 606 u8 crc[2]; 607 struct wilc_spi_cmd *c; 608 struct wilc_spi_rsp_data *r; 609 610 memset(wb, 0x0, sizeof(wb)); 611 memset(rb, 0x0, sizeof(rb)); 612 c = (struct wilc_spi_cmd *)wb; 613 c->cmd_type = cmd; 614 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 615 c->u.dma_cmd.addr[0] = adr >> 16; 616 c->u.dma_cmd.addr[1] = adr >> 8; 617 c->u.dma_cmd.addr[2] = adr; 618 c->u.dma_cmd.size[0] = sz >> 8; 619 c->u.dma_cmd.size[1] = sz; 620 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 621 if (spi_priv->crc7_enabled) 622 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 623 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 624 c->u.dma_cmd_ext.addr[0] = adr >> 16; 625 c->u.dma_cmd_ext.addr[1] = adr >> 8; 626 c->u.dma_cmd_ext.addr[2] = adr; 627 c->u.dma_cmd_ext.size[0] = sz >> 16; 628 c->u.dma_cmd_ext.size[1] = sz >> 8; 629 c->u.dma_cmd_ext.size[2] = sz; 630 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 631 if (spi_priv->crc7_enabled) 632 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 633 } else { 634 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 635 cmd); 636 return -EINVAL; 637 } 638 if (spi_priv->crc7_enabled) 639 cmd_len += 1; 640 641 resp_len = sizeof(*r); 642 643 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 644 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 645 cmd_len, resp_len, ARRAY_SIZE(wb)); 646 return -EINVAL; 647 } 648 649 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 650 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 651 return -EINVAL; 652 } 653 654 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 655 if (r->rsp_cmd_type != cmd) { 656 dev_err(&spi->dev, 657 "Failed cmd response, cmd (%02x), resp (%02x)\n", 658 cmd, r->rsp_cmd_type); 659 return -EINVAL; 660 } 661 662 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 663 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 664 r->status); 665 return -EINVAL; 666 } 667 668 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 669 return 0; 670 671 while (sz > 0) { 672 int nbytes; 673 u8 rsp; 674 675 if (sz <= DATA_PKT_SZ) 676 nbytes = sz; 677 else 678 nbytes = DATA_PKT_SZ; 679 680 /* 681 * Data Response header 682 */ 683 retry = 100; 684 do { 685 if (wilc_spi_rx(wilc, &rsp, 1)) { 686 dev_err(&spi->dev, 687 "Failed resp read, bus err\n"); 688 return -EINVAL; 689 } 690 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 691 break; 692 } while (retry--); 693 694 /* 695 * Read bytes 696 */ 697 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 698 dev_err(&spi->dev, 699 "Failed block read, bus err\n"); 700 return -EINVAL; 701 } 702 703 /* 704 * Read CRC 705 */ 706 if (spi_priv->crc16_enabled) { 707 if (wilc_spi_rx(wilc, crc, 2)) { 708 dev_err(&spi->dev, 709 "Failed block CRC read, bus err\n"); 710 return -EINVAL; 711 } 712 crc_recv = (crc[0] << 8) | crc[1]; 713 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 714 if (crc_recv != crc_calc) { 715 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 716 "(calculated 0x%04x)\n", __func__, 717 crc_recv, crc_calc); 718 return -EINVAL; 719 } 720 } 721 722 ix += nbytes; 723 sz -= nbytes; 724 } 725 return 0; 726 } 727 728 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) 729 { 730 struct spi_device *spi = to_spi_device(wilc->dev); 731 struct wilc_spi *spi_priv = wilc->bus_data; 732 u8 wb[32], rb[32]; 733 int cmd_len, resp_len = 0; 734 struct wilc_spi_cmd *c; 735 struct wilc_spi_special_cmd_rsp *r; 736 737 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) 738 return -EINVAL; 739 740 memset(wb, 0x0, sizeof(wb)); 741 memset(rb, 0x0, sizeof(rb)); 742 c = (struct wilc_spi_cmd *)wb; 743 c->cmd_type = cmd; 744 745 if (cmd == CMD_RESET) 746 memset(c->u.simple_cmd.addr, 0xFF, 3); 747 748 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 749 resp_len = sizeof(*r); 750 751 if (spi_priv->crc7_enabled) { 752 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 753 cmd_len += 1; 754 } 755 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 756 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", 757 cmd_len, resp_len, ARRAY_SIZE(wb)); 758 return -EINVAL; 759 } 760 761 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 762 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 763 return -EINVAL; 764 } 765 766 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len]; 767 if (r->rsp_cmd_type != cmd) { 768 if (!spi_priv->probing_crc) 769 dev_err(&spi->dev, 770 "Failed cmd response, cmd (%02x), resp (%02x)\n", 771 cmd, r->rsp_cmd_type); 772 return -EINVAL; 773 } 774 775 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 776 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 777 r->status); 778 return -EINVAL; 779 } 780 return 0; 781 } 782 783 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 784 { 785 struct spi_device *spi = to_spi_device(wilc->dev); 786 int result; 787 u8 cmd = CMD_SINGLE_READ; 788 u8 clockless = 0; 789 790 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 791 /* Clockless register */ 792 cmd = CMD_INTERNAL_READ; 793 clockless = 1; 794 } 795 796 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 797 if (result) { 798 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 799 return result; 800 } 801 802 le32_to_cpus(data); 803 804 return 0; 805 } 806 807 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 808 { 809 struct spi_device *spi = to_spi_device(wilc->dev); 810 int result; 811 812 if (size <= 4) 813 return -EINVAL; 814 815 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); 816 if (result) { 817 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 818 return result; 819 } 820 821 return 0; 822 } 823 824 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 825 { 826 struct spi_device *spi = to_spi_device(wilc->dev); 827 int result; 828 829 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); 830 if (result) { 831 dev_err(&spi->dev, "Failed internal write cmd...\n"); 832 return result; 833 } 834 835 return 0; 836 } 837 838 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 839 { 840 struct spi_device *spi = to_spi_device(wilc->dev); 841 struct wilc_spi *spi_priv = wilc->bus_data; 842 int result; 843 844 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); 845 if (result) { 846 if (!spi_priv->probing_crc) 847 dev_err(&spi->dev, "Failed internal read cmd...\n"); 848 return result; 849 } 850 851 le32_to_cpus(data); 852 853 return 0; 854 } 855 856 /******************************************** 857 * 858 * Spi interfaces 859 * 860 ********************************************/ 861 862 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 863 { 864 struct spi_device *spi = to_spi_device(wilc->dev); 865 int result; 866 u8 cmd = CMD_SINGLE_WRITE; 867 u8 clockless = 0; 868 869 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 870 /* Clockless register */ 871 cmd = CMD_INTERNAL_WRITE; 872 clockless = 1; 873 } 874 875 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 876 if (result) { 877 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 878 return result; 879 } 880 881 return 0; 882 } 883 884 static int spi_data_rsp(struct wilc *wilc, u8 cmd) 885 { 886 struct spi_device *spi = to_spi_device(wilc->dev); 887 int result, i; 888 u8 rsp[4]; 889 890 /* 891 * The response to data packets is two bytes long. For 892 * efficiency's sake, wilc_spi_write() wisely ignores the 893 * responses for all packets but the final one. The downside 894 * of that optimization is that when the final data packet is 895 * short, we may receive (part of) the response to the 896 * second-to-last packet before the one for the final packet. 897 * To handle this, we always read 4 bytes and then search for 898 * the last byte that contains the "Response Start" code (0xc 899 * in the top 4 bits). We then know that this byte is the 900 * first response byte of the final data packet. 901 */ 902 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 903 if (result) { 904 dev_err(&spi->dev, "Failed bus error...\n"); 905 return result; 906 } 907 908 for (i = sizeof(rsp) - 2; i >= 0; --i) 909 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 910 break; 911 912 if (i < 0) { 913 dev_err(&spi->dev, 914 "Data packet response missing (%02x %02x %02x %02x)\n", 915 rsp[0], rsp[1], rsp[2], rsp[3]); 916 return -1; 917 } 918 919 /* rsp[i] is the last response start byte */ 920 921 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 922 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 923 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 924 rsp[i], rsp[i + 1]); 925 return -1; 926 } 927 return 0; 928 } 929 930 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 931 { 932 struct spi_device *spi = to_spi_device(wilc->dev); 933 int result; 934 935 /* 936 * has to be greated than 4 937 */ 938 if (size <= 4) 939 return -EINVAL; 940 941 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); 942 if (result) { 943 dev_err(&spi->dev, 944 "Failed cmd, write block (%08x)...\n", addr); 945 return result; 946 } 947 948 /* 949 * Data 950 */ 951 result = spi_data_write(wilc, buf, size); 952 if (result) { 953 dev_err(&spi->dev, "Failed block data write...\n"); 954 return result; 955 } 956 957 /* 958 * Data response 959 */ 960 return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 961 } 962 963 /******************************************** 964 * 965 * Bus interfaces 966 * 967 ********************************************/ 968 969 static int wilc_spi_reset(struct wilc *wilc) 970 { 971 struct spi_device *spi = to_spi_device(wilc->dev); 972 struct wilc_spi *spi_priv = wilc->bus_data; 973 int result; 974 975 result = wilc_spi_special_cmd(wilc, CMD_RESET); 976 if (result && !spi_priv->probing_crc) 977 dev_err(&spi->dev, "Failed cmd reset\n"); 978 979 return result; 980 } 981 982 static int wilc_spi_deinit(struct wilc *wilc) 983 { 984 /* 985 * TODO: 986 */ 987 return 0; 988 } 989 990 static int wilc_spi_init(struct wilc *wilc, bool resume) 991 { 992 struct spi_device *spi = to_spi_device(wilc->dev); 993 struct wilc_spi *spi_priv = wilc->bus_data; 994 u32 reg; 995 u32 chipid; 996 int ret, i; 997 998 if (spi_priv->isinit) { 999 /* Confirm we can read chipid register without error: */ 1000 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1001 if (ret == 0) 1002 return 0; 1003 1004 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1005 } 1006 1007 /* 1008 * configure protocol 1009 */ 1010 1011 /* 1012 * Infer the CRC settings that are currently in effect. This 1013 * is necessary because we can't be sure that the chip has 1014 * been RESET (e.g, after module unload and reload). 1015 */ 1016 spi_priv->probing_crc = true; 1017 spi_priv->crc7_enabled = enable_crc7; 1018 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 1019 for (i = 0; i < 2; ++i) { 1020 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1021 if (ret == 0) 1022 break; 1023 spi_priv->crc7_enabled = !enable_crc7; 1024 } 1025 if (ret) { 1026 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 1027 return ret; 1028 } 1029 1030 /* set up the desired CRC configuration: */ 1031 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 1032 if (enable_crc7) 1033 reg |= PROTOCOL_REG_CRC7_MASK; 1034 if (enable_crc16) 1035 reg |= PROTOCOL_REG_CRC16_MASK; 1036 1037 /* set up the data packet size: */ 1038 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 1039 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 1040 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 1041 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 1042 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 1043 1044 /* establish the new setup: */ 1045 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 1046 if (ret) { 1047 dev_err(&spi->dev, 1048 "[wilc spi %d]: Failed internal write reg\n", 1049 __LINE__); 1050 return ret; 1051 } 1052 /* update our state to match new protocol settings: */ 1053 spi_priv->crc7_enabled = enable_crc7; 1054 spi_priv->crc16_enabled = enable_crc16; 1055 1056 /* re-read to make sure new settings are in effect: */ 1057 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1058 1059 spi_priv->probing_crc = false; 1060 1061 /* 1062 * make sure can read chip id without protocol error 1063 */ 1064 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1065 if (ret) { 1066 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1067 return ret; 1068 } 1069 1070 spi_priv->isinit = true; 1071 1072 return 0; 1073 } 1074 1075 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 1076 { 1077 int ret; 1078 1079 ret = spi_internal_read(wilc, 1080 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 1081 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 1082 1083 return ret; 1084 } 1085 1086 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 1087 { 1088 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1089 int_status); 1090 } 1091 1092 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1093 { 1094 int ret; 1095 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1096 u32 check; 1097 1098 while (retry) { 1099 ret = spi_internal_write(wilc, 1100 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1101 val); 1102 if (ret) 1103 break; 1104 1105 ret = spi_internal_read(wilc, 1106 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1107 &check); 1108 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1109 break; 1110 1111 retry--; 1112 } 1113 return ret; 1114 } 1115 1116 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1117 { 1118 struct spi_device *spi = to_spi_device(wilc->dev); 1119 u32 reg; 1120 int ret, i; 1121 1122 if (nint > MAX_NUM_INT) { 1123 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1124 return -EINVAL; 1125 } 1126 1127 /* 1128 * interrupt pin mux select 1129 */ 1130 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1131 if (ret) { 1132 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1133 WILC_PIN_MUX_0); 1134 return ret; 1135 } 1136 reg |= BIT(8); 1137 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1138 if (ret) { 1139 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1140 WILC_PIN_MUX_0); 1141 return ret; 1142 } 1143 1144 /* 1145 * interrupt enable 1146 */ 1147 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1148 if (ret) { 1149 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1150 WILC_INTR_ENABLE); 1151 return ret; 1152 } 1153 1154 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1155 reg |= (BIT((27 + i))); 1156 1157 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1158 if (ret) { 1159 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1160 WILC_INTR_ENABLE); 1161 return ret; 1162 } 1163 if (nint) { 1164 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1165 if (ret) { 1166 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1167 WILC_INTR2_ENABLE); 1168 return ret; 1169 } 1170 1171 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1172 reg |= BIT(i); 1173 1174 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg); 1175 if (ret) { 1176 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1177 WILC_INTR2_ENABLE); 1178 return ret; 1179 } 1180 } 1181 1182 return 0; 1183 } 1184 1185 /* Global spi HIF function table */ 1186 static const struct wilc_hif_func wilc_hif_spi = { 1187 .hif_init = wilc_spi_init, 1188 .hif_deinit = wilc_spi_deinit, 1189 .hif_read_reg = wilc_spi_read_reg, 1190 .hif_write_reg = wilc_spi_write_reg, 1191 .hif_block_rx = wilc_spi_read, 1192 .hif_block_tx = wilc_spi_write, 1193 .hif_read_int = wilc_spi_read_int, 1194 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1195 .hif_read_size = wilc_spi_read_size, 1196 .hif_block_tx_ext = wilc_spi_write, 1197 .hif_block_rx_ext = wilc_spi_read, 1198 .hif_sync_ext = wilc_spi_sync_ext, 1199 .hif_reset = wilc_spi_reset, 1200 }; 1201