1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/spi/spi.h> 9 #include <linux/crc7.h> 10 #include <linux/crc-itu-t.h> 11 12 #include "netdev.h" 13 #include "cfg80211.h" 14 15 static bool enable_crc7; /* protect SPI commands with CRC7 */ 16 module_param(enable_crc7, bool, 0644); 17 MODULE_PARM_DESC(enable_crc7, 18 "Enable CRC7 checksum to protect command transfers\n" 19 "\t\t\tagainst corruption during the SPI transfer.\n" 20 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 21 "\t\t\tof enabling this is small."); 22 23 static bool enable_crc16; /* protect SPI data with CRC16 */ 24 module_param(enable_crc16, bool, 0644); 25 MODULE_PARM_DESC(enable_crc16, 26 "Enable CRC16 checksum to protect data transfers\n" 27 "\t\t\tagainst corruption during the SPI transfer.\n" 28 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 29 "\t\t\tof enabling this may be substantial."); 30 31 /* 32 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 33 * more zero bytes between the command response and the DATA Start tag 34 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 35 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 36 * zero bytes when the SPI bus operates at 48MHz and none when it 37 * operates at 1MHz. 38 */ 39 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8 40 41 struct wilc_spi { 42 bool isinit; /* true if SPI protocol has been configured */ 43 bool probing_crc; /* true if we're probing chip's CRC config */ 44 bool crc7_enabled; /* true if crc7 is currently enabled */ 45 bool crc16_enabled; /* true if crc16 is currently enabled */ 46 }; 47 48 static const struct wilc_hif_func wilc_hif_spi; 49 50 static int wilc_spi_reset(struct wilc *wilc); 51 52 /******************************************** 53 * 54 * Spi protocol Function 55 * 56 ********************************************/ 57 58 #define CMD_DMA_WRITE 0xc1 59 #define CMD_DMA_READ 0xc2 60 #define CMD_INTERNAL_WRITE 0xc3 61 #define CMD_INTERNAL_READ 0xc4 62 #define CMD_TERMINATE 0xc5 63 #define CMD_REPEAT 0xc6 64 #define CMD_DMA_EXT_WRITE 0xc7 65 #define CMD_DMA_EXT_READ 0xc8 66 #define CMD_SINGLE_WRITE 0xc9 67 #define CMD_SINGLE_READ 0xca 68 #define CMD_RESET 0xcf 69 70 #define SPI_ENABLE_VMM_RETRY_LIMIT 2 71 72 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 73 #define RSP_START_FIELD GENMASK(7, 4) 74 #define RSP_TYPE_FIELD GENMASK(3, 0) 75 76 /* SPI response values for the response fields: */ 77 #define RSP_START_TAG 0xc 78 #define RSP_TYPE_FIRST_PACKET 0x1 79 #define RSP_TYPE_INNER_PACKET 0x2 80 #define RSP_TYPE_LAST_PACKET 0x3 81 #define RSP_STATE_NO_ERROR 0x00 82 83 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 84 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 85 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 86 87 /* 88 * The SPI data packet size may be any integer power of two in the 89 * range from 256 to 8192 bytes. 90 */ 91 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 92 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 93 94 /* 95 * Select the data packet size (log2 of number of bytes): Use the 96 * maximum data packet size. We only retransmit complete packets, so 97 * there is no benefit from using smaller data packets. 98 */ 99 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 100 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 101 102 #define USE_SPI_DMA 0 103 104 #define WILC_SPI_COMMAND_STAT_SUCCESS 0 105 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 106 107 struct wilc_spi_cmd { 108 u8 cmd_type; 109 union { 110 struct { 111 u8 addr[3]; 112 u8 crc[]; 113 } __packed simple_cmd; 114 struct { 115 u8 addr[3]; 116 u8 size[2]; 117 u8 crc[]; 118 } __packed dma_cmd; 119 struct { 120 u8 addr[3]; 121 u8 size[3]; 122 u8 crc[]; 123 } __packed dma_cmd_ext; 124 struct { 125 u8 addr[2]; 126 __be32 data; 127 u8 crc[]; 128 } __packed internal_w_cmd; 129 struct { 130 u8 addr[3]; 131 __be32 data; 132 u8 crc[]; 133 } __packed w_cmd; 134 } u; 135 } __packed; 136 137 struct wilc_spi_read_rsp_data { 138 u8 header; 139 u8 data[4]; 140 u8 crc[]; 141 } __packed; 142 143 struct wilc_spi_rsp_data { 144 u8 rsp_cmd_type; 145 u8 status; 146 u8 data[]; 147 } __packed; 148 149 struct wilc_spi_special_cmd_rsp { 150 u8 skip_byte; 151 u8 rsp_cmd_type; 152 u8 status; 153 } __packed; 154 155 static int wilc_bus_probe(struct spi_device *spi) 156 { 157 int ret; 158 struct wilc *wilc; 159 struct wilc_spi *spi_priv; 160 161 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 162 if (!spi_priv) 163 return -ENOMEM; 164 165 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 166 if (ret) 167 goto free; 168 169 spi_set_drvdata(spi, wilc); 170 wilc->dev = &spi->dev; 171 wilc->bus_data = spi_priv; 172 wilc->dev_irq_num = spi->irq; 173 174 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); 175 if (IS_ERR(wilc->rtc_clk)) { 176 ret = PTR_ERR(wilc->rtc_clk); 177 goto netdev_cleanup; 178 } 179 clk_prepare_enable(wilc->rtc_clk); 180 181 return 0; 182 183 netdev_cleanup: 184 wilc_netdev_cleanup(wilc); 185 free: 186 kfree(spi_priv); 187 return ret; 188 } 189 190 static int wilc_bus_remove(struct spi_device *spi) 191 { 192 struct wilc *wilc = spi_get_drvdata(spi); 193 194 clk_disable_unprepare(wilc->rtc_clk); 195 wilc_netdev_cleanup(wilc); 196 197 return 0; 198 } 199 200 static const struct of_device_id wilc_of_match[] = { 201 { .compatible = "microchip,wilc1000", }, 202 { /* sentinel */ } 203 }; 204 MODULE_DEVICE_TABLE(of, wilc_of_match); 205 206 static struct spi_driver wilc_spi_driver = { 207 .driver = { 208 .name = MODALIAS, 209 .of_match_table = wilc_of_match, 210 }, 211 .probe = wilc_bus_probe, 212 .remove = wilc_bus_remove, 213 }; 214 module_spi_driver(wilc_spi_driver); 215 MODULE_LICENSE("GPL"); 216 217 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 218 { 219 struct spi_device *spi = to_spi_device(wilc->dev); 220 int ret; 221 struct spi_message msg; 222 223 if (len > 0 && b) { 224 struct spi_transfer tr = { 225 .tx_buf = b, 226 .len = len, 227 .delay = { 228 .value = 0, 229 .unit = SPI_DELAY_UNIT_USECS 230 }, 231 }; 232 char *r_buffer = kzalloc(len, GFP_KERNEL); 233 234 if (!r_buffer) 235 return -ENOMEM; 236 237 tr.rx_buf = r_buffer; 238 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 239 240 memset(&msg, 0, sizeof(msg)); 241 spi_message_init(&msg); 242 msg.spi = spi; 243 msg.is_dma_mapped = USE_SPI_DMA; 244 spi_message_add_tail(&tr, &msg); 245 246 ret = spi_sync(spi, &msg); 247 if (ret < 0) 248 dev_err(&spi->dev, "SPI transaction failed\n"); 249 250 kfree(r_buffer); 251 } else { 252 dev_err(&spi->dev, 253 "can't write data with the following length: %d\n", 254 len); 255 ret = -EINVAL; 256 } 257 258 return ret; 259 } 260 261 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 262 { 263 struct spi_device *spi = to_spi_device(wilc->dev); 264 int ret; 265 266 if (rlen > 0) { 267 struct spi_message msg; 268 struct spi_transfer tr = { 269 .rx_buf = rb, 270 .len = rlen, 271 .delay = { 272 .value = 0, 273 .unit = SPI_DELAY_UNIT_USECS 274 }, 275 276 }; 277 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 278 279 if (!t_buffer) 280 return -ENOMEM; 281 282 tr.tx_buf = t_buffer; 283 284 memset(&msg, 0, sizeof(msg)); 285 spi_message_init(&msg); 286 msg.spi = spi; 287 msg.is_dma_mapped = USE_SPI_DMA; 288 spi_message_add_tail(&tr, &msg); 289 290 ret = spi_sync(spi, &msg); 291 if (ret < 0) 292 dev_err(&spi->dev, "SPI transaction failed\n"); 293 kfree(t_buffer); 294 } else { 295 dev_err(&spi->dev, 296 "can't read data with the following length: %u\n", 297 rlen); 298 ret = -EINVAL; 299 } 300 301 return ret; 302 } 303 304 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 305 { 306 struct spi_device *spi = to_spi_device(wilc->dev); 307 int ret; 308 309 if (rlen > 0) { 310 struct spi_message msg; 311 struct spi_transfer tr = { 312 .rx_buf = rb, 313 .tx_buf = wb, 314 .len = rlen, 315 .bits_per_word = 8, 316 .delay = { 317 .value = 0, 318 .unit = SPI_DELAY_UNIT_USECS 319 }, 320 321 }; 322 323 memset(&msg, 0, sizeof(msg)); 324 spi_message_init(&msg); 325 msg.spi = spi; 326 msg.is_dma_mapped = USE_SPI_DMA; 327 328 spi_message_add_tail(&tr, &msg); 329 ret = spi_sync(spi, &msg); 330 if (ret < 0) 331 dev_err(&spi->dev, "SPI transaction failed\n"); 332 } else { 333 dev_err(&spi->dev, 334 "can't read data with the following length: %u\n", 335 rlen); 336 ret = -EINVAL; 337 } 338 339 return ret; 340 } 341 342 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 343 { 344 struct spi_device *spi = to_spi_device(wilc->dev); 345 struct wilc_spi *spi_priv = wilc->bus_data; 346 int ix, nbytes; 347 int result = 0; 348 u8 cmd, order, crc[2]; 349 u16 crc_calc; 350 351 /* 352 * Data 353 */ 354 ix = 0; 355 do { 356 if (sz <= DATA_PKT_SZ) { 357 nbytes = sz; 358 order = 0x3; 359 } else { 360 nbytes = DATA_PKT_SZ; 361 if (ix == 0) 362 order = 0x1; 363 else 364 order = 0x02; 365 } 366 367 /* 368 * Write command 369 */ 370 cmd = 0xf0; 371 cmd |= order; 372 373 if (wilc_spi_tx(wilc, &cmd, 1)) { 374 dev_err(&spi->dev, 375 "Failed data block cmd write, bus error...\n"); 376 result = -EINVAL; 377 break; 378 } 379 380 /* 381 * Write data 382 */ 383 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 384 dev_err(&spi->dev, 385 "Failed data block write, bus error...\n"); 386 result = -EINVAL; 387 break; 388 } 389 390 /* 391 * Write CRC 392 */ 393 if (spi_priv->crc16_enabled) { 394 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 395 crc[0] = crc_calc >> 8; 396 crc[1] = crc_calc; 397 if (wilc_spi_tx(wilc, crc, 2)) { 398 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 399 result = -EINVAL; 400 break; 401 } 402 } 403 404 /* 405 * No need to wait for response 406 */ 407 ix += nbytes; 408 sz -= nbytes; 409 } while (sz); 410 411 return result; 412 } 413 414 /******************************************** 415 * 416 * Spi Internal Read/Write Function 417 * 418 ********************************************/ 419 static u8 wilc_get_crc7(u8 *buffer, u32 len) 420 { 421 return crc7_be(0xfe, buffer, len); 422 } 423 424 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 425 u8 clockless) 426 { 427 struct spi_device *spi = to_spi_device(wilc->dev); 428 struct wilc_spi *spi_priv = wilc->bus_data; 429 u8 wb[32], rb[32]; 430 int cmd_len, resp_len, i; 431 u16 crc_calc, crc_recv; 432 struct wilc_spi_cmd *c; 433 struct wilc_spi_rsp_data *r; 434 struct wilc_spi_read_rsp_data *r_data; 435 436 memset(wb, 0x0, sizeof(wb)); 437 memset(rb, 0x0, sizeof(rb)); 438 c = (struct wilc_spi_cmd *)wb; 439 c->cmd_type = cmd; 440 if (cmd == CMD_SINGLE_READ) { 441 c->u.simple_cmd.addr[0] = adr >> 16; 442 c->u.simple_cmd.addr[1] = adr >> 8; 443 c->u.simple_cmd.addr[2] = adr; 444 } else if (cmd == CMD_INTERNAL_READ) { 445 c->u.simple_cmd.addr[0] = adr >> 8; 446 if (clockless == 1) 447 c->u.simple_cmd.addr[0] |= BIT(7); 448 c->u.simple_cmd.addr[1] = adr; 449 c->u.simple_cmd.addr[2] = 0x0; 450 } else { 451 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 452 return -EINVAL; 453 } 454 455 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 456 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 457 458 if (spi_priv->crc7_enabled) { 459 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 460 cmd_len += 1; 461 resp_len += 2; 462 } 463 464 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 465 dev_err(&spi->dev, 466 "spi buffer size too small (%d) (%d) (%zu)\n", 467 cmd_len, resp_len, ARRAY_SIZE(wb)); 468 return -EINVAL; 469 } 470 471 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 472 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 473 return -EINVAL; 474 } 475 476 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 477 if (r->rsp_cmd_type != cmd && !clockless) { 478 if (!spi_priv->probing_crc) 479 dev_err(&spi->dev, 480 "Failed cmd, cmd (%02x), resp (%02x)\n", 481 cmd, r->rsp_cmd_type); 482 return -EINVAL; 483 } 484 485 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 486 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 487 r->status); 488 return -EINVAL; 489 } 490 491 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 492 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 493 break; 494 495 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 496 dev_err(&spi->dev, "Error, data start missing\n"); 497 return -EINVAL; 498 } 499 500 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 501 502 if (b) 503 memcpy(b, r_data->data, 4); 504 505 if (!clockless && spi_priv->crc16_enabled) { 506 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 507 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 508 if (crc_recv != crc_calc) { 509 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 510 "(calculated 0x%04x)\n", __func__, 511 crc_recv, crc_calc); 512 return -EINVAL; 513 } 514 } 515 516 return 0; 517 } 518 519 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 520 u8 clockless) 521 { 522 struct spi_device *spi = to_spi_device(wilc->dev); 523 struct wilc_spi *spi_priv = wilc->bus_data; 524 u8 wb[32], rb[32]; 525 int cmd_len, resp_len; 526 struct wilc_spi_cmd *c; 527 struct wilc_spi_rsp_data *r; 528 529 memset(wb, 0x0, sizeof(wb)); 530 memset(rb, 0x0, sizeof(rb)); 531 c = (struct wilc_spi_cmd *)wb; 532 c->cmd_type = cmd; 533 if (cmd == CMD_INTERNAL_WRITE) { 534 c->u.internal_w_cmd.addr[0] = adr >> 8; 535 if (clockless == 1) 536 c->u.internal_w_cmd.addr[0] |= BIT(7); 537 538 c->u.internal_w_cmd.addr[1] = adr; 539 c->u.internal_w_cmd.data = cpu_to_be32(data); 540 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 541 if (spi_priv->crc7_enabled) 542 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 543 } else if (cmd == CMD_SINGLE_WRITE) { 544 c->u.w_cmd.addr[0] = adr >> 16; 545 c->u.w_cmd.addr[1] = adr >> 8; 546 c->u.w_cmd.addr[2] = adr; 547 c->u.w_cmd.data = cpu_to_be32(data); 548 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 549 if (spi_priv->crc7_enabled) 550 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 551 } else { 552 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 553 return -EINVAL; 554 } 555 556 if (spi_priv->crc7_enabled) 557 cmd_len += 1; 558 559 resp_len = sizeof(*r); 560 561 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 562 dev_err(&spi->dev, 563 "spi buffer size too small (%d) (%d) (%zu)\n", 564 cmd_len, resp_len, ARRAY_SIZE(wb)); 565 return -EINVAL; 566 } 567 568 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 569 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 570 return -EINVAL; 571 } 572 573 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 574 /* 575 * Clockless registers operations might return unexptected responses, 576 * even if successful. 577 */ 578 if (r->rsp_cmd_type != cmd && !clockless) { 579 dev_err(&spi->dev, 580 "Failed cmd response, cmd (%02x), resp (%02x)\n", 581 cmd, r->rsp_cmd_type); 582 return -EINVAL; 583 } 584 585 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 586 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 587 r->status); 588 return -EINVAL; 589 } 590 591 return 0; 592 } 593 594 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 595 { 596 struct spi_device *spi = to_spi_device(wilc->dev); 597 struct wilc_spi *spi_priv = wilc->bus_data; 598 u16 crc_recv, crc_calc; 599 u8 wb[32], rb[32]; 600 int cmd_len, resp_len; 601 int retry, ix = 0; 602 u8 crc[2]; 603 struct wilc_spi_cmd *c; 604 struct wilc_spi_rsp_data *r; 605 606 memset(wb, 0x0, sizeof(wb)); 607 memset(rb, 0x0, sizeof(rb)); 608 c = (struct wilc_spi_cmd *)wb; 609 c->cmd_type = cmd; 610 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 611 c->u.dma_cmd.addr[0] = adr >> 16; 612 c->u.dma_cmd.addr[1] = adr >> 8; 613 c->u.dma_cmd.addr[2] = adr; 614 c->u.dma_cmd.size[0] = sz >> 8; 615 c->u.dma_cmd.size[1] = sz; 616 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 617 if (spi_priv->crc7_enabled) 618 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 619 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 620 c->u.dma_cmd_ext.addr[0] = adr >> 16; 621 c->u.dma_cmd_ext.addr[1] = adr >> 8; 622 c->u.dma_cmd_ext.addr[2] = adr; 623 c->u.dma_cmd_ext.size[0] = sz >> 16; 624 c->u.dma_cmd_ext.size[1] = sz >> 8; 625 c->u.dma_cmd_ext.size[2] = sz; 626 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 627 if (spi_priv->crc7_enabled) 628 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 629 } else { 630 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 631 cmd); 632 return -EINVAL; 633 } 634 if (spi_priv->crc7_enabled) 635 cmd_len += 1; 636 637 resp_len = sizeof(*r); 638 639 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 640 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 641 cmd_len, resp_len, ARRAY_SIZE(wb)); 642 return -EINVAL; 643 } 644 645 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 646 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 647 return -EINVAL; 648 } 649 650 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 651 if (r->rsp_cmd_type != cmd) { 652 dev_err(&spi->dev, 653 "Failed cmd response, cmd (%02x), resp (%02x)\n", 654 cmd, r->rsp_cmd_type); 655 return -EINVAL; 656 } 657 658 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 659 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 660 r->status); 661 return -EINVAL; 662 } 663 664 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 665 return 0; 666 667 while (sz > 0) { 668 int nbytes; 669 u8 rsp; 670 671 if (sz <= DATA_PKT_SZ) 672 nbytes = sz; 673 else 674 nbytes = DATA_PKT_SZ; 675 676 /* 677 * Data Response header 678 */ 679 retry = 100; 680 do { 681 if (wilc_spi_rx(wilc, &rsp, 1)) { 682 dev_err(&spi->dev, 683 "Failed resp read, bus err\n"); 684 return -EINVAL; 685 } 686 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 687 break; 688 } while (retry--); 689 690 /* 691 * Read bytes 692 */ 693 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 694 dev_err(&spi->dev, 695 "Failed block read, bus err\n"); 696 return -EINVAL; 697 } 698 699 /* 700 * Read CRC 701 */ 702 if (spi_priv->crc16_enabled) { 703 if (wilc_spi_rx(wilc, crc, 2)) { 704 dev_err(&spi->dev, 705 "Failed block CRC read, bus err\n"); 706 return -EINVAL; 707 } 708 crc_recv = (crc[0] << 8) | crc[1]; 709 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 710 if (crc_recv != crc_calc) { 711 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 712 "(calculated 0x%04x)\n", __func__, 713 crc_recv, crc_calc); 714 return -EINVAL; 715 } 716 } 717 718 ix += nbytes; 719 sz -= nbytes; 720 } 721 return 0; 722 } 723 724 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) 725 { 726 struct spi_device *spi = to_spi_device(wilc->dev); 727 struct wilc_spi *spi_priv = wilc->bus_data; 728 u8 wb[32], rb[32]; 729 int cmd_len, resp_len = 0; 730 struct wilc_spi_cmd *c; 731 struct wilc_spi_special_cmd_rsp *r; 732 733 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) 734 return -EINVAL; 735 736 memset(wb, 0x0, sizeof(wb)); 737 memset(rb, 0x0, sizeof(rb)); 738 c = (struct wilc_spi_cmd *)wb; 739 c->cmd_type = cmd; 740 741 if (cmd == CMD_RESET) 742 memset(c->u.simple_cmd.addr, 0xFF, 3); 743 744 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 745 resp_len = sizeof(*r); 746 747 if (spi_priv->crc7_enabled) { 748 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 749 cmd_len += 1; 750 } 751 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 752 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", 753 cmd_len, resp_len, ARRAY_SIZE(wb)); 754 return -EINVAL; 755 } 756 757 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 758 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 759 return -EINVAL; 760 } 761 762 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len]; 763 if (r->rsp_cmd_type != cmd) { 764 if (!spi_priv->probing_crc) 765 dev_err(&spi->dev, 766 "Failed cmd response, cmd (%02x), resp (%02x)\n", 767 cmd, r->rsp_cmd_type); 768 return -EINVAL; 769 } 770 771 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 772 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 773 r->status); 774 return -EINVAL; 775 } 776 return 0; 777 } 778 779 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 780 { 781 struct spi_device *spi = to_spi_device(wilc->dev); 782 int result; 783 u8 cmd = CMD_SINGLE_READ; 784 u8 clockless = 0; 785 786 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 787 /* Clockless register */ 788 cmd = CMD_INTERNAL_READ; 789 clockless = 1; 790 } 791 792 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 793 if (result) { 794 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 795 return result; 796 } 797 798 le32_to_cpus(data); 799 800 return 0; 801 } 802 803 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 804 { 805 struct spi_device *spi = to_spi_device(wilc->dev); 806 int result; 807 808 if (size <= 4) 809 return -EINVAL; 810 811 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); 812 if (result) { 813 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 814 return result; 815 } 816 817 return 0; 818 } 819 820 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 821 { 822 struct spi_device *spi = to_spi_device(wilc->dev); 823 int result; 824 825 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); 826 if (result) { 827 dev_err(&spi->dev, "Failed internal write cmd...\n"); 828 return result; 829 } 830 831 return 0; 832 } 833 834 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 835 { 836 struct spi_device *spi = to_spi_device(wilc->dev); 837 struct wilc_spi *spi_priv = wilc->bus_data; 838 int result; 839 840 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); 841 if (result) { 842 if (!spi_priv->probing_crc) 843 dev_err(&spi->dev, "Failed internal read cmd...\n"); 844 return result; 845 } 846 847 le32_to_cpus(data); 848 849 return 0; 850 } 851 852 /******************************************** 853 * 854 * Spi interfaces 855 * 856 ********************************************/ 857 858 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 859 { 860 struct spi_device *spi = to_spi_device(wilc->dev); 861 int result; 862 u8 cmd = CMD_SINGLE_WRITE; 863 u8 clockless = 0; 864 865 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 866 /* Clockless register */ 867 cmd = CMD_INTERNAL_WRITE; 868 clockless = 1; 869 } 870 871 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 872 if (result) { 873 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 874 return result; 875 } 876 877 return 0; 878 } 879 880 static int spi_data_rsp(struct wilc *wilc, u8 cmd) 881 { 882 struct spi_device *spi = to_spi_device(wilc->dev); 883 int result, i; 884 u8 rsp[4]; 885 886 /* 887 * The response to data packets is two bytes long. For 888 * efficiency's sake, wilc_spi_write() wisely ignores the 889 * responses for all packets but the final one. The downside 890 * of that optimization is that when the final data packet is 891 * short, we may receive (part of) the response to the 892 * second-to-last packet before the one for the final packet. 893 * To handle this, we always read 4 bytes and then search for 894 * the last byte that contains the "Response Start" code (0xc 895 * in the top 4 bits). We then know that this byte is the 896 * first response byte of the final data packet. 897 */ 898 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 899 if (result) { 900 dev_err(&spi->dev, "Failed bus error...\n"); 901 return result; 902 } 903 904 for (i = sizeof(rsp) - 2; i >= 0; --i) 905 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 906 break; 907 908 if (i < 0) { 909 dev_err(&spi->dev, 910 "Data packet response missing (%02x %02x %02x %02x)\n", 911 rsp[0], rsp[1], rsp[2], rsp[3]); 912 return -1; 913 } 914 915 /* rsp[i] is the last response start byte */ 916 917 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 918 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 919 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 920 rsp[i], rsp[i + 1]); 921 return -1; 922 } 923 return 0; 924 } 925 926 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 927 { 928 struct spi_device *spi = to_spi_device(wilc->dev); 929 int result; 930 931 /* 932 * has to be greated than 4 933 */ 934 if (size <= 4) 935 return -EINVAL; 936 937 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); 938 if (result) { 939 dev_err(&spi->dev, 940 "Failed cmd, write block (%08x)...\n", addr); 941 return result; 942 } 943 944 /* 945 * Data 946 */ 947 result = spi_data_write(wilc, buf, size); 948 if (result) { 949 dev_err(&spi->dev, "Failed block data write...\n"); 950 return result; 951 } 952 953 /* 954 * Data response 955 */ 956 return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 957 } 958 959 /******************************************** 960 * 961 * Bus interfaces 962 * 963 ********************************************/ 964 965 static int wilc_spi_reset(struct wilc *wilc) 966 { 967 struct spi_device *spi = to_spi_device(wilc->dev); 968 struct wilc_spi *spi_priv = wilc->bus_data; 969 int result; 970 971 result = wilc_spi_special_cmd(wilc, CMD_RESET); 972 if (result && !spi_priv->probing_crc) 973 dev_err(&spi->dev, "Failed cmd reset\n"); 974 975 return result; 976 } 977 978 static int wilc_spi_deinit(struct wilc *wilc) 979 { 980 /* 981 * TODO: 982 */ 983 return 0; 984 } 985 986 static int wilc_spi_init(struct wilc *wilc, bool resume) 987 { 988 struct spi_device *spi = to_spi_device(wilc->dev); 989 struct wilc_spi *spi_priv = wilc->bus_data; 990 u32 reg; 991 u32 chipid; 992 int ret, i; 993 994 if (spi_priv->isinit) { 995 /* Confirm we can read chipid register without error: */ 996 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 997 if (ret == 0) 998 return 0; 999 1000 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1001 } 1002 1003 /* 1004 * configure protocol 1005 */ 1006 1007 /* 1008 * Infer the CRC settings that are currently in effect. This 1009 * is necessary because we can't be sure that the chip has 1010 * been RESET (e.g, after module unload and reload). 1011 */ 1012 spi_priv->probing_crc = true; 1013 spi_priv->crc7_enabled = enable_crc7; 1014 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 1015 for (i = 0; i < 2; ++i) { 1016 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1017 if (ret == 0) 1018 break; 1019 spi_priv->crc7_enabled = !enable_crc7; 1020 } 1021 if (ret) { 1022 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 1023 return ret; 1024 } 1025 1026 /* set up the desired CRC configuration: */ 1027 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 1028 if (enable_crc7) 1029 reg |= PROTOCOL_REG_CRC7_MASK; 1030 if (enable_crc16) 1031 reg |= PROTOCOL_REG_CRC16_MASK; 1032 1033 /* set up the data packet size: */ 1034 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 1035 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 1036 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 1037 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 1038 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 1039 1040 /* establish the new setup: */ 1041 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 1042 if (ret) { 1043 dev_err(&spi->dev, 1044 "[wilc spi %d]: Failed internal write reg\n", 1045 __LINE__); 1046 return ret; 1047 } 1048 /* update our state to match new protocol settings: */ 1049 spi_priv->crc7_enabled = enable_crc7; 1050 spi_priv->crc16_enabled = enable_crc16; 1051 1052 /* re-read to make sure new settings are in effect: */ 1053 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1054 1055 spi_priv->probing_crc = false; 1056 1057 /* 1058 * make sure can read chip id without protocol error 1059 */ 1060 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1061 if (ret) { 1062 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1063 return ret; 1064 } 1065 1066 spi_priv->isinit = true; 1067 1068 return 0; 1069 } 1070 1071 static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 1072 { 1073 int ret; 1074 1075 ret = spi_internal_read(wilc, 1076 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 1077 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 1078 1079 return ret; 1080 } 1081 1082 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 1083 { 1084 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1085 int_status); 1086 } 1087 1088 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1089 { 1090 int ret; 1091 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1092 u32 check; 1093 1094 while (retry) { 1095 ret = spi_internal_write(wilc, 1096 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1097 val); 1098 if (ret) 1099 break; 1100 1101 ret = spi_internal_read(wilc, 1102 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1103 &check); 1104 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1105 break; 1106 1107 retry--; 1108 } 1109 return ret; 1110 } 1111 1112 static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1113 { 1114 struct spi_device *spi = to_spi_device(wilc->dev); 1115 u32 reg; 1116 int ret, i; 1117 1118 if (nint > MAX_NUM_INT) { 1119 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1120 return -EINVAL; 1121 } 1122 1123 /* 1124 * interrupt pin mux select 1125 */ 1126 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1127 if (ret) { 1128 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1129 WILC_PIN_MUX_0); 1130 return ret; 1131 } 1132 reg |= BIT(8); 1133 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1134 if (ret) { 1135 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1136 WILC_PIN_MUX_0); 1137 return ret; 1138 } 1139 1140 /* 1141 * interrupt enable 1142 */ 1143 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1144 if (ret) { 1145 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1146 WILC_INTR_ENABLE); 1147 return ret; 1148 } 1149 1150 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1151 reg |= (BIT((27 + i))); 1152 1153 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1154 if (ret) { 1155 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1156 WILC_INTR_ENABLE); 1157 return ret; 1158 } 1159 if (nint) { 1160 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1161 if (ret) { 1162 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1163 WILC_INTR2_ENABLE); 1164 return ret; 1165 } 1166 1167 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1168 reg |= BIT(i); 1169 1170 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg); 1171 if (ret) { 1172 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1173 WILC_INTR2_ENABLE); 1174 return ret; 1175 } 1176 } 1177 1178 return 0; 1179 } 1180 1181 /* Global spi HIF function table */ 1182 static const struct wilc_hif_func wilc_hif_spi = { 1183 .hif_init = wilc_spi_init, 1184 .hif_deinit = wilc_spi_deinit, 1185 .hif_read_reg = wilc_spi_read_reg, 1186 .hif_write_reg = wilc_spi_write_reg, 1187 .hif_block_rx = wilc_spi_read, 1188 .hif_block_tx = wilc_spi_write, 1189 .hif_read_int = wilc_spi_read_int, 1190 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1191 .hif_read_size = wilc_spi_read_size, 1192 .hif_block_tx_ext = wilc_spi_write, 1193 .hif_block_rx_ext = wilc_spi_read, 1194 .hif_sync_ext = wilc_spi_sync_ext, 1195 .hif_reset = wilc_spi_reset, 1196 }; 1197