1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/mmc/sdio_func.h> 9 #include <linux/mmc/sdio_ids.h> 10 #include <linux/mmc/host.h> 11 #include <linux/mmc/sdio.h> 12 #include <linux/of_irq.h> 13 14 #include "netdev.h" 15 #include "cfg80211.h" 16 17 #define SDIO_MODALIAS "wilc1000_sdio" 18 19 static const struct sdio_device_id wilc_sdio_ids[] = { 20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) }, 21 { }, 22 }; 23 24 #define WILC_SDIO_BLOCK_SIZE 512 25 26 struct wilc_sdio { 27 bool irq_gpio; 28 u32 block_size; 29 bool isinit; 30 int has_thrpt_enh3; 31 }; 32 33 struct sdio_cmd52 { 34 u32 read_write: 1; 35 u32 function: 3; 36 u32 raw: 1; 37 u32 address: 17; 38 u32 data: 8; 39 }; 40 41 struct sdio_cmd53 { 42 u32 read_write: 1; 43 u32 function: 3; 44 u32 block_mode: 1; 45 u32 increment: 1; 46 u32 address: 17; 47 u32 count: 9; 48 u8 *buffer; 49 u32 block_size; 50 }; 51 52 static const struct wilc_hif_func wilc_hif_sdio; 53 54 static void wilc_sdio_interrupt(struct sdio_func *func) 55 { 56 sdio_release_host(func); 57 wilc_handle_isr(sdio_get_drvdata(func)); 58 sdio_claim_host(func); 59 } 60 61 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd) 62 { 63 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 64 int ret; 65 u8 data; 66 67 sdio_claim_host(func); 68 69 func->num = cmd->function; 70 if (cmd->read_write) { /* write */ 71 if (cmd->raw) { 72 sdio_writeb(func, cmd->data, cmd->address, &ret); 73 data = sdio_readb(func, cmd->address, &ret); 74 cmd->data = data; 75 } else { 76 sdio_writeb(func, cmd->data, cmd->address, &ret); 77 } 78 } else { /* read */ 79 data = sdio_readb(func, cmd->address, &ret); 80 cmd->data = data; 81 } 82 83 sdio_release_host(func); 84 85 if (ret) 86 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 87 return ret; 88 } 89 90 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd) 91 { 92 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 93 int size, ret; 94 95 sdio_claim_host(func); 96 97 func->num = cmd->function; 98 func->cur_blksize = cmd->block_size; 99 if (cmd->block_mode) 100 size = cmd->count * cmd->block_size; 101 else 102 size = cmd->count; 103 104 if (cmd->read_write) { /* write */ 105 ret = sdio_memcpy_toio(func, cmd->address, 106 (void *)cmd->buffer, size); 107 } else { /* read */ 108 ret = sdio_memcpy_fromio(func, (void *)cmd->buffer, 109 cmd->address, size); 110 } 111 112 sdio_release_host(func); 113 114 if (ret) 115 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 116 117 return ret; 118 } 119 120 static int wilc_sdio_probe(struct sdio_func *func, 121 const struct sdio_device_id *id) 122 { 123 struct wilc *wilc; 124 int ret; 125 struct wilc_sdio *sdio_priv; 126 127 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL); 128 if (!sdio_priv) 129 return -ENOMEM; 130 131 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO, 132 &wilc_hif_sdio); 133 if (ret) 134 goto free; 135 136 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) { 137 struct device_node *np = func->card->dev.of_node; 138 int irq_num = of_irq_get(np, 0); 139 140 if (irq_num > 0) { 141 wilc->dev_irq_num = irq_num; 142 sdio_priv->irq_gpio = true; 143 } 144 } 145 146 sdio_set_drvdata(func, wilc); 147 wilc->bus_data = sdio_priv; 148 wilc->dev = &func->dev; 149 150 wilc->rtc_clk = devm_clk_get_optional(&func->card->dev, "rtc"); 151 if (IS_ERR(wilc->rtc_clk)) { 152 ret = PTR_ERR(wilc->rtc_clk); 153 goto dispose_irq; 154 } 155 clk_prepare_enable(wilc->rtc_clk); 156 157 dev_info(&func->dev, "Driver Initializing success\n"); 158 return 0; 159 160 dispose_irq: 161 irq_dispose_mapping(wilc->dev_irq_num); 162 wilc_netdev_cleanup(wilc); 163 free: 164 kfree(sdio_priv); 165 return ret; 166 } 167 168 static void wilc_sdio_remove(struct sdio_func *func) 169 { 170 struct wilc *wilc = sdio_get_drvdata(func); 171 struct wilc_sdio *sdio_priv = wilc->bus_data; 172 173 clk_disable_unprepare(wilc->rtc_clk); 174 wilc_netdev_cleanup(wilc); 175 kfree(sdio_priv); 176 } 177 178 static int wilc_sdio_reset(struct wilc *wilc) 179 { 180 struct sdio_cmd52 cmd; 181 int ret; 182 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 183 184 cmd.read_write = 1; 185 cmd.function = 0; 186 cmd.raw = 0; 187 cmd.address = SDIO_CCCR_ABORT; 188 cmd.data = WILC_SDIO_CCCR_ABORT_RESET; 189 ret = wilc_sdio_cmd52(wilc, &cmd); 190 if (ret) { 191 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n"); 192 return ret; 193 } 194 return 0; 195 } 196 197 static bool wilc_sdio_is_init(struct wilc *wilc) 198 { 199 struct wilc_sdio *sdio_priv = wilc->bus_data; 200 201 return sdio_priv->isinit; 202 } 203 204 static int wilc_sdio_suspend(struct device *dev) 205 { 206 struct sdio_func *func = dev_to_sdio_func(dev); 207 struct wilc *wilc = sdio_get_drvdata(func); 208 int ret; 209 210 dev_info(dev, "sdio suspend\n"); 211 chip_wakeup(wilc); 212 213 if (!IS_ERR(wilc->rtc_clk)) 214 clk_disable_unprepare(wilc->rtc_clk); 215 216 if (wilc->suspend_event) { 217 host_sleep_notify(wilc); 218 chip_allow_sleep(wilc); 219 } 220 221 ret = wilc_sdio_reset(wilc); 222 if (ret) { 223 dev_err(&func->dev, "Fail reset sdio\n"); 224 return ret; 225 } 226 sdio_claim_host(func); 227 228 return 0; 229 } 230 231 static int wilc_sdio_enable_interrupt(struct wilc *dev) 232 { 233 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 234 int ret = 0; 235 236 sdio_claim_host(func); 237 ret = sdio_claim_irq(func, wilc_sdio_interrupt); 238 sdio_release_host(func); 239 240 if (ret < 0) { 241 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret); 242 ret = -EIO; 243 } 244 return ret; 245 } 246 247 static void wilc_sdio_disable_interrupt(struct wilc *dev) 248 { 249 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 250 int ret; 251 252 sdio_claim_host(func); 253 ret = sdio_release_irq(func); 254 if (ret < 0) 255 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret); 256 sdio_release_host(func); 257 } 258 259 /******************************************** 260 * 261 * Function 0 262 * 263 ********************************************/ 264 265 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr) 266 { 267 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 268 struct sdio_cmd52 cmd; 269 int ret; 270 271 /** 272 * Review: BIG ENDIAN 273 **/ 274 cmd.read_write = 1; 275 cmd.function = 0; 276 cmd.raw = 0; 277 cmd.address = WILC_SDIO_FBR_CSA_REG; 278 cmd.data = (u8)adr; 279 ret = wilc_sdio_cmd52(wilc, &cmd); 280 if (ret) { 281 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 282 cmd.address); 283 return ret; 284 } 285 286 cmd.address = WILC_SDIO_FBR_CSA_REG + 1; 287 cmd.data = (u8)(adr >> 8); 288 ret = wilc_sdio_cmd52(wilc, &cmd); 289 if (ret) { 290 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 291 cmd.address); 292 return ret; 293 } 294 295 cmd.address = WILC_SDIO_FBR_CSA_REG + 2; 296 cmd.data = (u8)(adr >> 16); 297 ret = wilc_sdio_cmd52(wilc, &cmd); 298 if (ret) { 299 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 300 cmd.address); 301 return ret; 302 } 303 304 return 0; 305 } 306 307 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num, 308 u32 block_size) 309 { 310 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 311 struct sdio_cmd52 cmd; 312 int ret; 313 314 cmd.read_write = 1; 315 cmd.function = 0; 316 cmd.raw = 0; 317 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE; 318 cmd.data = (u8)block_size; 319 ret = wilc_sdio_cmd52(wilc, &cmd); 320 if (ret) { 321 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 322 cmd.address); 323 return ret; 324 } 325 326 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1; 327 cmd.data = (u8)(block_size >> 8); 328 ret = wilc_sdio_cmd52(wilc, &cmd); 329 if (ret) { 330 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 331 cmd.address); 332 return ret; 333 } 334 335 return 0; 336 } 337 338 /******************************************** 339 * 340 * Sdio interfaces 341 * 342 ********************************************/ 343 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data) 344 { 345 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 346 struct wilc_sdio *sdio_priv = wilc->bus_data; 347 int ret; 348 349 cpu_to_le32s(&data); 350 351 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 352 struct sdio_cmd52 cmd; 353 354 cmd.read_write = 1; 355 cmd.function = 0; 356 cmd.raw = 0; 357 cmd.address = addr; 358 cmd.data = data; 359 ret = wilc_sdio_cmd52(wilc, &cmd); 360 if (ret) 361 dev_err(&func->dev, 362 "Failed cmd 52, read reg (%08x) ...\n", addr); 363 } else { 364 struct sdio_cmd53 cmd; 365 366 /** 367 * set the AHB address 368 **/ 369 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 370 if (ret) 371 return ret; 372 373 cmd.read_write = 1; 374 cmd.function = 0; 375 cmd.address = WILC_SDIO_FBR_DATA_REG; 376 cmd.block_mode = 0; 377 cmd.increment = 1; 378 cmd.count = 4; 379 cmd.buffer = (u8 *)&data; 380 cmd.block_size = sdio_priv->block_size; 381 ret = wilc_sdio_cmd53(wilc, &cmd); 382 if (ret) 383 dev_err(&func->dev, 384 "Failed cmd53, write reg (%08x)...\n", addr); 385 } 386 387 return ret; 388 } 389 390 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 391 { 392 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 393 struct wilc_sdio *sdio_priv = wilc->bus_data; 394 u32 block_size = sdio_priv->block_size; 395 struct sdio_cmd53 cmd; 396 int nblk, nleft, ret; 397 398 cmd.read_write = 1; 399 if (addr > 0) { 400 /** 401 * func 0 access 402 **/ 403 cmd.function = 0; 404 cmd.address = WILC_SDIO_FBR_DATA_REG; 405 } else { 406 /** 407 * func 1 access 408 **/ 409 cmd.function = 1; 410 cmd.address = WILC_SDIO_F1_DATA_REG; 411 } 412 413 size = ALIGN(size, 4); 414 nblk = size / block_size; 415 nleft = size % block_size; 416 417 if (nblk > 0) { 418 cmd.block_mode = 1; 419 cmd.increment = 1; 420 cmd.count = nblk; 421 cmd.buffer = buf; 422 cmd.block_size = block_size; 423 if (addr > 0) { 424 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 425 if (ret) 426 return ret; 427 } 428 ret = wilc_sdio_cmd53(wilc, &cmd); 429 if (ret) { 430 dev_err(&func->dev, 431 "Failed cmd53 [%x], block send...\n", addr); 432 return ret; 433 } 434 if (addr > 0) 435 addr += nblk * block_size; 436 buf += nblk * block_size; 437 } 438 439 if (nleft > 0) { 440 cmd.block_mode = 0; 441 cmd.increment = 1; 442 cmd.count = nleft; 443 cmd.buffer = buf; 444 445 cmd.block_size = block_size; 446 447 if (addr > 0) { 448 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 449 if (ret) 450 return ret; 451 } 452 ret = wilc_sdio_cmd53(wilc, &cmd); 453 if (ret) { 454 dev_err(&func->dev, 455 "Failed cmd53 [%x], bytes send...\n", addr); 456 return ret; 457 } 458 } 459 460 return 0; 461 } 462 463 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data) 464 { 465 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 466 struct wilc_sdio *sdio_priv = wilc->bus_data; 467 int ret; 468 469 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 470 struct sdio_cmd52 cmd; 471 472 cmd.read_write = 0; 473 cmd.function = 0; 474 cmd.raw = 0; 475 cmd.address = addr; 476 ret = wilc_sdio_cmd52(wilc, &cmd); 477 if (ret) { 478 dev_err(&func->dev, 479 "Failed cmd 52, read reg (%08x) ...\n", addr); 480 return ret; 481 } 482 *data = cmd.data; 483 } else { 484 struct sdio_cmd53 cmd; 485 486 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 487 if (ret) 488 return ret; 489 490 cmd.read_write = 0; 491 cmd.function = 0; 492 cmd.address = WILC_SDIO_FBR_DATA_REG; 493 cmd.block_mode = 0; 494 cmd.increment = 1; 495 cmd.count = 4; 496 cmd.buffer = (u8 *)data; 497 498 cmd.block_size = sdio_priv->block_size; 499 ret = wilc_sdio_cmd53(wilc, &cmd); 500 if (ret) { 501 dev_err(&func->dev, 502 "Failed cmd53, read reg (%08x)...\n", addr); 503 return ret; 504 } 505 } 506 507 le32_to_cpus(data); 508 return 0; 509 } 510 511 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 512 { 513 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 514 struct wilc_sdio *sdio_priv = wilc->bus_data; 515 u32 block_size = sdio_priv->block_size; 516 struct sdio_cmd53 cmd; 517 int nblk, nleft, ret; 518 519 cmd.read_write = 0; 520 if (addr > 0) { 521 /** 522 * func 0 access 523 **/ 524 cmd.function = 0; 525 cmd.address = WILC_SDIO_FBR_DATA_REG; 526 } else { 527 /** 528 * func 1 access 529 **/ 530 cmd.function = 1; 531 cmd.address = WILC_SDIO_F1_DATA_REG; 532 } 533 534 size = ALIGN(size, 4); 535 nblk = size / block_size; 536 nleft = size % block_size; 537 538 if (nblk > 0) { 539 cmd.block_mode = 1; 540 cmd.increment = 1; 541 cmd.count = nblk; 542 cmd.buffer = buf; 543 cmd.block_size = block_size; 544 if (addr > 0) { 545 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 546 if (ret) 547 return ret; 548 } 549 ret = wilc_sdio_cmd53(wilc, &cmd); 550 if (ret) { 551 dev_err(&func->dev, 552 "Failed cmd53 [%x], block read...\n", addr); 553 return ret; 554 } 555 if (addr > 0) 556 addr += nblk * block_size; 557 buf += nblk * block_size; 558 } /* if (nblk > 0) */ 559 560 if (nleft > 0) { 561 cmd.block_mode = 0; 562 cmd.increment = 1; 563 cmd.count = nleft; 564 cmd.buffer = buf; 565 566 cmd.block_size = block_size; 567 568 if (addr > 0) { 569 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 570 if (ret) 571 return ret; 572 } 573 ret = wilc_sdio_cmd53(wilc, &cmd); 574 if (ret) { 575 dev_err(&func->dev, 576 "Failed cmd53 [%x], bytes read...\n", addr); 577 return ret; 578 } 579 } 580 581 return 0; 582 } 583 584 /******************************************** 585 * 586 * Bus interfaces 587 * 588 ********************************************/ 589 590 static int wilc_sdio_deinit(struct wilc *wilc) 591 { 592 struct wilc_sdio *sdio_priv = wilc->bus_data; 593 594 sdio_priv->isinit = false; 595 return 0; 596 } 597 598 static int wilc_sdio_init(struct wilc *wilc, bool resume) 599 { 600 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 601 struct wilc_sdio *sdio_priv = wilc->bus_data; 602 struct sdio_cmd52 cmd; 603 int loop, ret; 604 u32 chipid; 605 606 /** 607 * function 0 csa enable 608 **/ 609 cmd.read_write = 1; 610 cmd.function = 0; 611 cmd.raw = 1; 612 cmd.address = SDIO_FBR_BASE(1); 613 cmd.data = SDIO_FBR_ENABLE_CSA; 614 ret = wilc_sdio_cmd52(wilc, &cmd); 615 if (ret) { 616 dev_err(&func->dev, "Fail cmd 52, enable csa...\n"); 617 return ret; 618 } 619 620 /** 621 * function 0 block size 622 **/ 623 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE); 624 if (ret) { 625 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n"); 626 return ret; 627 } 628 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE; 629 630 /** 631 * enable func1 IO 632 **/ 633 cmd.read_write = 1; 634 cmd.function = 0; 635 cmd.raw = 1; 636 cmd.address = SDIO_CCCR_IOEx; 637 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1; 638 ret = wilc_sdio_cmd52(wilc, &cmd); 639 if (ret) { 640 dev_err(&func->dev, 641 "Fail cmd 52, set IOE register...\n"); 642 return ret; 643 } 644 645 /** 646 * make sure func 1 is up 647 **/ 648 cmd.read_write = 0; 649 cmd.function = 0; 650 cmd.raw = 0; 651 cmd.address = SDIO_CCCR_IORx; 652 loop = 3; 653 do { 654 cmd.data = 0; 655 ret = wilc_sdio_cmd52(wilc, &cmd); 656 if (ret) { 657 dev_err(&func->dev, 658 "Fail cmd 52, get IOR register...\n"); 659 return ret; 660 } 661 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1) 662 break; 663 } while (loop--); 664 665 if (loop <= 0) { 666 dev_err(&func->dev, "Fail func 1 is not ready...\n"); 667 return -EINVAL; 668 } 669 670 /** 671 * func 1 is ready, set func 1 block size 672 **/ 673 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE); 674 if (ret) { 675 dev_err(&func->dev, "Fail set func 1 block size...\n"); 676 return ret; 677 } 678 679 /** 680 * func 1 interrupt enable 681 **/ 682 cmd.read_write = 1; 683 cmd.function = 0; 684 cmd.raw = 1; 685 cmd.address = SDIO_CCCR_IENx; 686 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1; 687 ret = wilc_sdio_cmd52(wilc, &cmd); 688 if (ret) { 689 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n"); 690 return ret; 691 } 692 693 /** 694 * make sure can read back chip id correctly 695 **/ 696 if (!resume) { 697 int rev; 698 699 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid); 700 if (ret) { 701 dev_err(&func->dev, "Fail cmd read chip id...\n"); 702 return ret; 703 } 704 dev_err(&func->dev, "chipid (%08x)\n", chipid); 705 rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid); 706 if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A)) 707 sdio_priv->has_thrpt_enh3 = 1; 708 else 709 sdio_priv->has_thrpt_enh3 = 0; 710 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n", 711 sdio_priv->has_thrpt_enh3); 712 } 713 714 sdio_priv->isinit = true; 715 return 0; 716 } 717 718 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size) 719 { 720 u32 tmp; 721 struct sdio_cmd52 cmd; 722 723 /** 724 * Read DMA count in words 725 **/ 726 cmd.read_write = 0; 727 cmd.function = 0; 728 cmd.raw = 0; 729 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG; 730 cmd.data = 0; 731 wilc_sdio_cmd52(wilc, &cmd); 732 tmp = cmd.data; 733 734 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1; 735 cmd.data = 0; 736 wilc_sdio_cmd52(wilc, &cmd); 737 tmp |= (cmd.data << 8); 738 739 *size = tmp; 740 return 0; 741 } 742 743 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status) 744 { 745 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 746 struct wilc_sdio *sdio_priv = wilc->bus_data; 747 u32 tmp; 748 u8 irq_flags; 749 struct sdio_cmd52 cmd; 750 751 wilc_sdio_read_size(wilc, &tmp); 752 753 /** 754 * Read IRQ flags 755 **/ 756 if (!sdio_priv->irq_gpio) { 757 cmd.function = 1; 758 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG; 759 } else { 760 cmd.function = 0; 761 cmd.address = WILC_SDIO_IRQ_FLAG_REG; 762 } 763 cmd.raw = 0; 764 cmd.read_write = 0; 765 cmd.data = 0; 766 wilc_sdio_cmd52(wilc, &cmd); 767 irq_flags = cmd.data; 768 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data); 769 770 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)) 771 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n", 772 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)); 773 774 *int_status = tmp; 775 776 return 0; 777 } 778 779 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val) 780 { 781 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 782 struct wilc_sdio *sdio_priv = wilc->bus_data; 783 int ret; 784 int vmm_ctl; 785 786 if (sdio_priv->has_thrpt_enh3) { 787 u32 reg = 0; 788 789 if (sdio_priv->irq_gpio) 790 reg = val & (BIT(MAX_NUM_INT) - 1); 791 792 /* select VMM table 0 */ 793 if (val & SEL_VMM_TBL0) 794 reg |= BIT(5); 795 /* select VMM table 1 */ 796 if (val & SEL_VMM_TBL1) 797 reg |= BIT(6); 798 /* enable VMM */ 799 if (val & EN_VMM) 800 reg |= BIT(7); 801 if (reg) { 802 struct sdio_cmd52 cmd; 803 804 cmd.read_write = 1; 805 cmd.function = 0; 806 cmd.raw = 0; 807 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 808 cmd.data = reg; 809 810 ret = wilc_sdio_cmd52(wilc, &cmd); 811 if (ret) { 812 dev_err(&func->dev, 813 "Failed cmd52, set (%02x) data (%d) ...\n", 814 cmd.address, __LINE__); 815 return ret; 816 } 817 } 818 return 0; 819 } 820 if (sdio_priv->irq_gpio) { 821 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */ 822 /* 823 * Cannot clear multiple interrupts. 824 * Must clear each interrupt individually. 825 */ 826 u32 flags; 827 int i; 828 829 flags = val & (BIT(MAX_NUM_INT) - 1); 830 for (i = 0; i < NUM_INT_EXT && flags; i++) { 831 if (flags & BIT(i)) { 832 struct sdio_cmd52 cmd; 833 834 cmd.read_write = 1; 835 cmd.function = 0; 836 cmd.raw = 0; 837 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 838 cmd.data = BIT(i); 839 840 ret = wilc_sdio_cmd52(wilc, &cmd); 841 if (ret) { 842 dev_err(&func->dev, 843 "Failed cmd52, set (%02x) data (%d) ...\n", 844 cmd.address, __LINE__); 845 return ret; 846 } 847 flags &= ~BIT(i); 848 } 849 } 850 851 for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) { 852 if (flags & BIT(i)) { 853 dev_err(&func->dev, 854 "Unexpected interrupt cleared %d...\n", 855 i); 856 flags &= ~BIT(i); 857 } 858 } 859 } 860 861 vmm_ctl = 0; 862 /* select VMM table 0 */ 863 if (val & SEL_VMM_TBL0) 864 vmm_ctl |= BIT(0); 865 /* select VMM table 1 */ 866 if (val & SEL_VMM_TBL1) 867 vmm_ctl |= BIT(1); 868 /* enable VMM */ 869 if (val & EN_VMM) 870 vmm_ctl |= BIT(2); 871 872 if (vmm_ctl) { 873 struct sdio_cmd52 cmd; 874 875 cmd.read_write = 1; 876 cmd.function = 0; 877 cmd.raw = 0; 878 cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG; 879 cmd.data = vmm_ctl; 880 ret = wilc_sdio_cmd52(wilc, &cmd); 881 if (ret) { 882 dev_err(&func->dev, 883 "Failed cmd52, set (%02x) data (%d) ...\n", 884 cmd.address, __LINE__); 885 return ret; 886 } 887 } 888 return 0; 889 } 890 891 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint) 892 { 893 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 894 struct wilc_sdio *sdio_priv = wilc->bus_data; 895 u32 reg; 896 897 if (nint > MAX_NUM_INT) { 898 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint); 899 return -EINVAL; 900 } 901 902 /** 903 * Disable power sequencer 904 **/ 905 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) { 906 dev_err(&func->dev, "Failed read misc reg...\n"); 907 return -EINVAL; 908 } 909 910 reg &= ~BIT(8); 911 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) { 912 dev_err(&func->dev, "Failed write misc reg...\n"); 913 return -EINVAL; 914 } 915 916 if (sdio_priv->irq_gpio) { 917 u32 reg; 918 int ret, i; 919 920 /** 921 * interrupt pin mux select 922 **/ 923 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); 924 if (ret) { 925 dev_err(&func->dev, "Failed read reg (%08x)...\n", 926 WILC_PIN_MUX_0); 927 return ret; 928 } 929 reg |= BIT(8); 930 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); 931 if (ret) { 932 dev_err(&func->dev, "Failed write reg (%08x)...\n", 933 WILC_PIN_MUX_0); 934 return ret; 935 } 936 937 /** 938 * interrupt enable 939 **/ 940 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); 941 if (ret) { 942 dev_err(&func->dev, "Failed read reg (%08x)...\n", 943 WILC_INTR_ENABLE); 944 return ret; 945 } 946 947 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 948 reg |= BIT((27 + i)); 949 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); 950 if (ret) { 951 dev_err(&func->dev, "Failed write reg (%08x)...\n", 952 WILC_INTR_ENABLE); 953 return ret; 954 } 955 if (nint) { 956 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); 957 if (ret) { 958 dev_err(&func->dev, 959 "Failed read reg (%08x)...\n", 960 WILC_INTR2_ENABLE); 961 return ret; 962 } 963 964 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 965 reg |= BIT(i); 966 967 ret = wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg); 968 if (ret) { 969 dev_err(&func->dev, 970 "Failed write reg (%08x)...\n", 971 WILC_INTR2_ENABLE); 972 return ret; 973 } 974 } 975 } 976 return 0; 977 } 978 979 /* Global sdio HIF function table */ 980 static const struct wilc_hif_func wilc_hif_sdio = { 981 .hif_init = wilc_sdio_init, 982 .hif_deinit = wilc_sdio_deinit, 983 .hif_read_reg = wilc_sdio_read_reg, 984 .hif_write_reg = wilc_sdio_write_reg, 985 .hif_block_rx = wilc_sdio_read, 986 .hif_block_tx = wilc_sdio_write, 987 .hif_read_int = wilc_sdio_read_int, 988 .hif_clear_int_ext = wilc_sdio_clear_int_ext, 989 .hif_read_size = wilc_sdio_read_size, 990 .hif_block_tx_ext = wilc_sdio_write, 991 .hif_block_rx_ext = wilc_sdio_read, 992 .hif_sync_ext = wilc_sdio_sync_ext, 993 .enable_interrupt = wilc_sdio_enable_interrupt, 994 .disable_interrupt = wilc_sdio_disable_interrupt, 995 .hif_reset = wilc_sdio_reset, 996 .hif_is_init = wilc_sdio_is_init, 997 }; 998 999 static int wilc_sdio_resume(struct device *dev) 1000 { 1001 struct sdio_func *func = dev_to_sdio_func(dev); 1002 struct wilc *wilc = sdio_get_drvdata(func); 1003 1004 dev_info(dev, "sdio resume\n"); 1005 sdio_release_host(func); 1006 chip_wakeup(wilc); 1007 wilc_sdio_init(wilc, true); 1008 1009 if (wilc->suspend_event) 1010 host_wakeup_notify(wilc); 1011 1012 chip_allow_sleep(wilc); 1013 1014 return 0; 1015 } 1016 1017 static const struct of_device_id wilc_of_match[] = { 1018 { .compatible = "microchip,wilc1000", }, 1019 { /* sentinel */ } 1020 }; 1021 MODULE_DEVICE_TABLE(of, wilc_of_match); 1022 1023 static const struct dev_pm_ops wilc_sdio_pm_ops = { 1024 .suspend = wilc_sdio_suspend, 1025 .resume = wilc_sdio_resume, 1026 }; 1027 1028 static struct sdio_driver wilc_sdio_driver = { 1029 .name = SDIO_MODALIAS, 1030 .id_table = wilc_sdio_ids, 1031 .probe = wilc_sdio_probe, 1032 .remove = wilc_sdio_remove, 1033 .drv = { 1034 .pm = &wilc_sdio_pm_ops, 1035 .of_match_table = wilc_of_match, 1036 } 1037 }; 1038 module_driver(wilc_sdio_driver, 1039 sdio_register_driver, 1040 sdio_unregister_driver); 1041 MODULE_LICENSE("GPL"); 1042