1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/mmc/sdio_func.h> 9 #include <linux/mmc/sdio_ids.h> 10 #include <linux/mmc/host.h> 11 #include <linux/mmc/sdio.h> 12 #include <linux/of_irq.h> 13 14 #include "netdev.h" 15 #include "cfg80211.h" 16 17 #define SDIO_MODALIAS "wilc1000_sdio" 18 19 static const struct sdio_device_id wilc_sdio_ids[] = { 20 { SDIO_DEVICE(SDIO_VENDOR_ID_MICROCHIP_WILC, SDIO_DEVICE_ID_MICROCHIP_WILC1000) }, 21 { }, 22 }; 23 24 #define WILC_SDIO_BLOCK_SIZE 512 25 26 struct wilc_sdio { 27 bool irq_gpio; 28 u32 block_size; 29 int has_thrpt_enh3; 30 }; 31 32 struct sdio_cmd52 { 33 u32 read_write: 1; 34 u32 function: 3; 35 u32 raw: 1; 36 u32 address: 17; 37 u32 data: 8; 38 }; 39 40 struct sdio_cmd53 { 41 u32 read_write: 1; 42 u32 function: 3; 43 u32 block_mode: 1; 44 u32 increment: 1; 45 u32 address: 17; 46 u32 count: 9; 47 u8 *buffer; 48 u32 block_size; 49 }; 50 51 static const struct wilc_hif_func wilc_hif_sdio; 52 53 static void wilc_sdio_interrupt(struct sdio_func *func) 54 { 55 sdio_release_host(func); 56 wilc_handle_isr(sdio_get_drvdata(func)); 57 sdio_claim_host(func); 58 } 59 60 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd) 61 { 62 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 63 int ret; 64 u8 data; 65 66 sdio_claim_host(func); 67 68 func->num = cmd->function; 69 if (cmd->read_write) { /* write */ 70 if (cmd->raw) { 71 sdio_writeb(func, cmd->data, cmd->address, &ret); 72 data = sdio_readb(func, cmd->address, &ret); 73 cmd->data = data; 74 } else { 75 sdio_writeb(func, cmd->data, cmd->address, &ret); 76 } 77 } else { /* read */ 78 data = sdio_readb(func, cmd->address, &ret); 79 cmd->data = data; 80 } 81 82 sdio_release_host(func); 83 84 if (ret) 85 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 86 return ret; 87 } 88 89 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd) 90 { 91 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); 92 int size, ret; 93 94 sdio_claim_host(func); 95 96 func->num = cmd->function; 97 func->cur_blksize = cmd->block_size; 98 if (cmd->block_mode) 99 size = cmd->count * cmd->block_size; 100 else 101 size = cmd->count; 102 103 if (cmd->read_write) { /* write */ 104 ret = sdio_memcpy_toio(func, cmd->address, 105 (void *)cmd->buffer, size); 106 } else { /* read */ 107 ret = sdio_memcpy_fromio(func, (void *)cmd->buffer, 108 cmd->address, size); 109 } 110 111 sdio_release_host(func); 112 113 if (ret) 114 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); 115 116 return ret; 117 } 118 119 static int wilc_sdio_probe(struct sdio_func *func, 120 const struct sdio_device_id *id) 121 { 122 struct wilc *wilc; 123 int ret; 124 struct wilc_sdio *sdio_priv; 125 126 sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL); 127 if (!sdio_priv) 128 return -ENOMEM; 129 130 ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO, 131 &wilc_hif_sdio); 132 if (ret) { 133 kfree(sdio_priv); 134 return ret; 135 } 136 137 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) { 138 struct device_node *np = func->card->dev.of_node; 139 int irq_num = of_irq_get(np, 0); 140 141 if (irq_num > 0) { 142 wilc->dev_irq_num = irq_num; 143 sdio_priv->irq_gpio = true; 144 } 145 } 146 147 sdio_set_drvdata(func, wilc); 148 wilc->bus_data = sdio_priv; 149 wilc->dev = &func->dev; 150 151 wilc->rtc_clk = devm_clk_get(&func->card->dev, "rtc"); 152 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) 153 return -EPROBE_DEFER; 154 else if (!IS_ERR(wilc->rtc_clk)) 155 clk_prepare_enable(wilc->rtc_clk); 156 157 dev_info(&func->dev, "Driver Initializing success\n"); 158 return 0; 159 } 160 161 static void wilc_sdio_remove(struct sdio_func *func) 162 { 163 struct wilc *wilc = sdio_get_drvdata(func); 164 165 if (!IS_ERR(wilc->rtc_clk)) 166 clk_disable_unprepare(wilc->rtc_clk); 167 168 wilc_netdev_cleanup(wilc); 169 } 170 171 static int wilc_sdio_reset(struct wilc *wilc) 172 { 173 struct sdio_cmd52 cmd; 174 int ret; 175 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 176 177 cmd.read_write = 1; 178 cmd.function = 0; 179 cmd.raw = 0; 180 cmd.address = SDIO_CCCR_ABORT; 181 cmd.data = WILC_SDIO_CCCR_ABORT_RESET; 182 ret = wilc_sdio_cmd52(wilc, &cmd); 183 if (ret) { 184 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n"); 185 return ret; 186 } 187 return 0; 188 } 189 190 static int wilc_sdio_suspend(struct device *dev) 191 { 192 struct sdio_func *func = dev_to_sdio_func(dev); 193 struct wilc *wilc = sdio_get_drvdata(func); 194 int ret; 195 196 dev_info(dev, "sdio suspend\n"); 197 chip_wakeup(wilc); 198 199 if (!IS_ERR(wilc->rtc_clk)) 200 clk_disable_unprepare(wilc->rtc_clk); 201 202 if (wilc->suspend_event) { 203 host_sleep_notify(wilc); 204 chip_allow_sleep(wilc); 205 } 206 207 ret = wilc_sdio_reset(wilc); 208 if (ret) { 209 dev_err(&func->dev, "Fail reset sdio\n"); 210 return ret; 211 } 212 sdio_claim_host(func); 213 214 return 0; 215 } 216 217 static int wilc_sdio_enable_interrupt(struct wilc *dev) 218 { 219 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 220 int ret = 0; 221 222 sdio_claim_host(func); 223 ret = sdio_claim_irq(func, wilc_sdio_interrupt); 224 sdio_release_host(func); 225 226 if (ret < 0) { 227 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret); 228 ret = -EIO; 229 } 230 return ret; 231 } 232 233 static void wilc_sdio_disable_interrupt(struct wilc *dev) 234 { 235 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); 236 int ret; 237 238 sdio_claim_host(func); 239 ret = sdio_release_irq(func); 240 if (ret < 0) 241 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret); 242 sdio_release_host(func); 243 } 244 245 /******************************************** 246 * 247 * Function 0 248 * 249 ********************************************/ 250 251 static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr) 252 { 253 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 254 struct sdio_cmd52 cmd; 255 int ret; 256 257 /** 258 * Review: BIG ENDIAN 259 **/ 260 cmd.read_write = 1; 261 cmd.function = 0; 262 cmd.raw = 0; 263 cmd.address = WILC_SDIO_FBR_CSA_REG; 264 cmd.data = (u8)adr; 265 ret = wilc_sdio_cmd52(wilc, &cmd); 266 if (ret) { 267 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 268 cmd.address); 269 return ret; 270 } 271 272 cmd.address = WILC_SDIO_FBR_CSA_REG + 1; 273 cmd.data = (u8)(adr >> 8); 274 ret = wilc_sdio_cmd52(wilc, &cmd); 275 if (ret) { 276 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 277 cmd.address); 278 return ret; 279 } 280 281 cmd.address = WILC_SDIO_FBR_CSA_REG + 2; 282 cmd.data = (u8)(adr >> 16); 283 ret = wilc_sdio_cmd52(wilc, &cmd); 284 if (ret) { 285 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 286 cmd.address); 287 return ret; 288 } 289 290 return 0; 291 } 292 293 static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num, 294 u32 block_size) 295 { 296 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 297 struct sdio_cmd52 cmd; 298 int ret; 299 300 cmd.read_write = 1; 301 cmd.function = 0; 302 cmd.raw = 0; 303 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE; 304 cmd.data = (u8)block_size; 305 ret = wilc_sdio_cmd52(wilc, &cmd); 306 if (ret) { 307 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 308 cmd.address); 309 return ret; 310 } 311 312 cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1; 313 cmd.data = (u8)(block_size >> 8); 314 ret = wilc_sdio_cmd52(wilc, &cmd); 315 if (ret) { 316 dev_err(&func->dev, "Failed cmd52, set %04x data...\n", 317 cmd.address); 318 return ret; 319 } 320 321 return 0; 322 } 323 324 /******************************************** 325 * 326 * Sdio interfaces 327 * 328 ********************************************/ 329 static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data) 330 { 331 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 332 struct wilc_sdio *sdio_priv = wilc->bus_data; 333 int ret; 334 335 cpu_to_le32s(&data); 336 337 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 338 struct sdio_cmd52 cmd; 339 340 cmd.read_write = 1; 341 cmd.function = 0; 342 cmd.raw = 0; 343 cmd.address = addr; 344 cmd.data = data; 345 ret = wilc_sdio_cmd52(wilc, &cmd); 346 if (ret) 347 dev_err(&func->dev, 348 "Failed cmd 52, read reg (%08x) ...\n", addr); 349 } else { 350 struct sdio_cmd53 cmd; 351 352 /** 353 * set the AHB address 354 **/ 355 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 356 if (ret) 357 return ret; 358 359 cmd.read_write = 1; 360 cmd.function = 0; 361 cmd.address = WILC_SDIO_FBR_DATA_REG; 362 cmd.block_mode = 0; 363 cmd.increment = 1; 364 cmd.count = 4; 365 cmd.buffer = (u8 *)&data; 366 cmd.block_size = sdio_priv->block_size; 367 ret = wilc_sdio_cmd53(wilc, &cmd); 368 if (ret) 369 dev_err(&func->dev, 370 "Failed cmd53, write reg (%08x)...\n", addr); 371 } 372 373 return ret; 374 } 375 376 static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 377 { 378 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 379 struct wilc_sdio *sdio_priv = wilc->bus_data; 380 u32 block_size = sdio_priv->block_size; 381 struct sdio_cmd53 cmd; 382 int nblk, nleft, ret; 383 384 cmd.read_write = 1; 385 if (addr > 0) { 386 /** 387 * func 0 access 388 **/ 389 cmd.function = 0; 390 cmd.address = WILC_SDIO_FBR_DATA_REG; 391 } else { 392 /** 393 * func 1 access 394 **/ 395 cmd.function = 1; 396 cmd.address = WILC_SDIO_F1_DATA_REG; 397 } 398 399 size = ALIGN(size, 4); 400 nblk = size / block_size; 401 nleft = size % block_size; 402 403 if (nblk > 0) { 404 cmd.block_mode = 1; 405 cmd.increment = 1; 406 cmd.count = nblk; 407 cmd.buffer = buf; 408 cmd.block_size = block_size; 409 if (addr > 0) { 410 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 411 if (ret) 412 return ret; 413 } 414 ret = wilc_sdio_cmd53(wilc, &cmd); 415 if (ret) { 416 dev_err(&func->dev, 417 "Failed cmd53 [%x], block send...\n", addr); 418 return ret; 419 } 420 if (addr > 0) 421 addr += nblk * block_size; 422 buf += nblk * block_size; 423 } 424 425 if (nleft > 0) { 426 cmd.block_mode = 0; 427 cmd.increment = 1; 428 cmd.count = nleft; 429 cmd.buffer = buf; 430 431 cmd.block_size = block_size; 432 433 if (addr > 0) { 434 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 435 if (ret) 436 return ret; 437 } 438 ret = wilc_sdio_cmd53(wilc, &cmd); 439 if (ret) { 440 dev_err(&func->dev, 441 "Failed cmd53 [%x], bytes send...\n", addr); 442 return ret; 443 } 444 } 445 446 return 0; 447 } 448 449 static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data) 450 { 451 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 452 struct wilc_sdio *sdio_priv = wilc->bus_data; 453 int ret; 454 455 if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ 456 struct sdio_cmd52 cmd; 457 458 cmd.read_write = 0; 459 cmd.function = 0; 460 cmd.raw = 0; 461 cmd.address = addr; 462 ret = wilc_sdio_cmd52(wilc, &cmd); 463 if (ret) { 464 dev_err(&func->dev, 465 "Failed cmd 52, read reg (%08x) ...\n", addr); 466 return ret; 467 } 468 *data = cmd.data; 469 } else { 470 struct sdio_cmd53 cmd; 471 472 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 473 if (ret) 474 return ret; 475 476 cmd.read_write = 0; 477 cmd.function = 0; 478 cmd.address = WILC_SDIO_FBR_DATA_REG; 479 cmd.block_mode = 0; 480 cmd.increment = 1; 481 cmd.count = 4; 482 cmd.buffer = (u8 *)data; 483 484 cmd.block_size = sdio_priv->block_size; 485 ret = wilc_sdio_cmd53(wilc, &cmd); 486 if (ret) { 487 dev_err(&func->dev, 488 "Failed cmd53, read reg (%08x)...\n", addr); 489 return ret; 490 } 491 } 492 493 le32_to_cpus(data); 494 return 0; 495 } 496 497 static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 498 { 499 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 500 struct wilc_sdio *sdio_priv = wilc->bus_data; 501 u32 block_size = sdio_priv->block_size; 502 struct sdio_cmd53 cmd; 503 int nblk, nleft, ret; 504 505 cmd.read_write = 0; 506 if (addr > 0) { 507 /** 508 * func 0 access 509 **/ 510 cmd.function = 0; 511 cmd.address = WILC_SDIO_FBR_DATA_REG; 512 } else { 513 /** 514 * func 1 access 515 **/ 516 cmd.function = 1; 517 cmd.address = WILC_SDIO_F1_DATA_REG; 518 } 519 520 size = ALIGN(size, 4); 521 nblk = size / block_size; 522 nleft = size % block_size; 523 524 if (nblk > 0) { 525 cmd.block_mode = 1; 526 cmd.increment = 1; 527 cmd.count = nblk; 528 cmd.buffer = buf; 529 cmd.block_size = block_size; 530 if (addr > 0) { 531 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 532 if (ret) 533 return ret; 534 } 535 ret = wilc_sdio_cmd53(wilc, &cmd); 536 if (ret) { 537 dev_err(&func->dev, 538 "Failed cmd53 [%x], block read...\n", addr); 539 return ret; 540 } 541 if (addr > 0) 542 addr += nblk * block_size; 543 buf += nblk * block_size; 544 } /* if (nblk > 0) */ 545 546 if (nleft > 0) { 547 cmd.block_mode = 0; 548 cmd.increment = 1; 549 cmd.count = nleft; 550 cmd.buffer = buf; 551 552 cmd.block_size = block_size; 553 554 if (addr > 0) { 555 ret = wilc_sdio_set_func0_csa_address(wilc, addr); 556 if (ret) 557 return ret; 558 } 559 ret = wilc_sdio_cmd53(wilc, &cmd); 560 if (ret) { 561 dev_err(&func->dev, 562 "Failed cmd53 [%x], bytes read...\n", addr); 563 return ret; 564 } 565 } 566 567 return 0; 568 } 569 570 /******************************************** 571 * 572 * Bus interfaces 573 * 574 ********************************************/ 575 576 static int wilc_sdio_deinit(struct wilc *wilc) 577 { 578 return 0; 579 } 580 581 static int wilc_sdio_init(struct wilc *wilc, bool resume) 582 { 583 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 584 struct wilc_sdio *sdio_priv = wilc->bus_data; 585 struct sdio_cmd52 cmd; 586 int loop, ret; 587 u32 chipid; 588 589 /** 590 * function 0 csa enable 591 **/ 592 cmd.read_write = 1; 593 cmd.function = 0; 594 cmd.raw = 1; 595 cmd.address = SDIO_FBR_BASE(func->num); 596 cmd.data = SDIO_FBR_ENABLE_CSA; 597 ret = wilc_sdio_cmd52(wilc, &cmd); 598 if (ret) { 599 dev_err(&func->dev, "Fail cmd 52, enable csa...\n"); 600 return ret; 601 } 602 603 /** 604 * function 0 block size 605 **/ 606 ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE); 607 if (ret) { 608 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n"); 609 return ret; 610 } 611 sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE; 612 613 /** 614 * enable func1 IO 615 **/ 616 cmd.read_write = 1; 617 cmd.function = 0; 618 cmd.raw = 1; 619 cmd.address = SDIO_CCCR_IOEx; 620 cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1; 621 ret = wilc_sdio_cmd52(wilc, &cmd); 622 if (ret) { 623 dev_err(&func->dev, 624 "Fail cmd 52, set IOE register...\n"); 625 return ret; 626 } 627 628 /** 629 * make sure func 1 is up 630 **/ 631 cmd.read_write = 0; 632 cmd.function = 0; 633 cmd.raw = 0; 634 cmd.address = SDIO_CCCR_IORx; 635 loop = 3; 636 do { 637 cmd.data = 0; 638 ret = wilc_sdio_cmd52(wilc, &cmd); 639 if (ret) { 640 dev_err(&func->dev, 641 "Fail cmd 52, get IOR register...\n"); 642 return ret; 643 } 644 if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1) 645 break; 646 } while (loop--); 647 648 if (loop <= 0) { 649 dev_err(&func->dev, "Fail func 1 is not ready...\n"); 650 return -EINVAL; 651 } 652 653 /** 654 * func 1 is ready, set func 1 block size 655 **/ 656 ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE); 657 if (ret) { 658 dev_err(&func->dev, "Fail set func 1 block size...\n"); 659 return ret; 660 } 661 662 /** 663 * func 1 interrupt enable 664 **/ 665 cmd.read_write = 1; 666 cmd.function = 0; 667 cmd.raw = 1; 668 cmd.address = SDIO_CCCR_IENx; 669 cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1; 670 ret = wilc_sdio_cmd52(wilc, &cmd); 671 if (ret) { 672 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n"); 673 return ret; 674 } 675 676 /** 677 * make sure can read back chip id correctly 678 **/ 679 if (!resume) { 680 int rev; 681 682 ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid); 683 if (ret) { 684 dev_err(&func->dev, "Fail cmd read chip id...\n"); 685 return ret; 686 } 687 dev_err(&func->dev, "chipid (%08x)\n", chipid); 688 rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid); 689 if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A)) 690 sdio_priv->has_thrpt_enh3 = 1; 691 else 692 sdio_priv->has_thrpt_enh3 = 0; 693 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n", 694 sdio_priv->has_thrpt_enh3); 695 } 696 697 return 0; 698 } 699 700 static int wilc_sdio_read_size(struct wilc *wilc, u32 *size) 701 { 702 u32 tmp; 703 struct sdio_cmd52 cmd; 704 705 /** 706 * Read DMA count in words 707 **/ 708 cmd.read_write = 0; 709 cmd.function = 0; 710 cmd.raw = 0; 711 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG; 712 cmd.data = 0; 713 wilc_sdio_cmd52(wilc, &cmd); 714 tmp = cmd.data; 715 716 cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1; 717 cmd.data = 0; 718 wilc_sdio_cmd52(wilc, &cmd); 719 tmp |= (cmd.data << 8); 720 721 *size = tmp; 722 return 0; 723 } 724 725 static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status) 726 { 727 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 728 struct wilc_sdio *sdio_priv = wilc->bus_data; 729 u32 tmp; 730 u8 irq_flags; 731 struct sdio_cmd52 cmd; 732 733 wilc_sdio_read_size(wilc, &tmp); 734 735 /** 736 * Read IRQ flags 737 **/ 738 if (!sdio_priv->irq_gpio) { 739 cmd.function = 1; 740 cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG; 741 } else { 742 cmd.function = 0; 743 cmd.address = WILC_SDIO_IRQ_FLAG_REG; 744 } 745 cmd.raw = 0; 746 cmd.read_write = 0; 747 cmd.data = 0; 748 wilc_sdio_cmd52(wilc, &cmd); 749 irq_flags = cmd.data; 750 tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data); 751 752 if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)) 753 dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n", 754 FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)); 755 756 *int_status = tmp; 757 758 return 0; 759 } 760 761 static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val) 762 { 763 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 764 struct wilc_sdio *sdio_priv = wilc->bus_data; 765 int ret; 766 int vmm_ctl; 767 768 if (sdio_priv->has_thrpt_enh3) { 769 u32 reg = 0; 770 771 if (sdio_priv->irq_gpio) 772 reg = val & (BIT(MAX_NUM_INT) - 1); 773 774 /* select VMM table 0 */ 775 if (val & SEL_VMM_TBL0) 776 reg |= BIT(5); 777 /* select VMM table 1 */ 778 if (val & SEL_VMM_TBL1) 779 reg |= BIT(6); 780 /* enable VMM */ 781 if (val & EN_VMM) 782 reg |= BIT(7); 783 if (reg) { 784 struct sdio_cmd52 cmd; 785 786 cmd.read_write = 1; 787 cmd.function = 0; 788 cmd.raw = 0; 789 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 790 cmd.data = reg; 791 792 ret = wilc_sdio_cmd52(wilc, &cmd); 793 if (ret) { 794 dev_err(&func->dev, 795 "Failed cmd52, set (%02x) data (%d) ...\n", 796 cmd.address, __LINE__); 797 return ret; 798 } 799 } 800 return 0; 801 } 802 if (sdio_priv->irq_gpio) { 803 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */ 804 /* 805 * Cannot clear multiple interrupts. 806 * Must clear each interrupt individually. 807 */ 808 u32 flags; 809 int i; 810 811 flags = val & (BIT(MAX_NUM_INT) - 1); 812 for (i = 0; i < NUM_INT_EXT && flags; i++) { 813 if (flags & BIT(i)) { 814 struct sdio_cmd52 cmd; 815 816 cmd.read_write = 1; 817 cmd.function = 0; 818 cmd.raw = 0; 819 cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; 820 cmd.data = BIT(i); 821 822 ret = wilc_sdio_cmd52(wilc, &cmd); 823 if (ret) { 824 dev_err(&func->dev, 825 "Failed cmd52, set (%02x) data (%d) ...\n", 826 cmd.address, __LINE__); 827 return ret; 828 } 829 flags &= ~BIT(i); 830 } 831 } 832 833 for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) { 834 if (flags & BIT(i)) { 835 dev_err(&func->dev, 836 "Unexpected interrupt cleared %d...\n", 837 i); 838 flags &= ~BIT(i); 839 } 840 } 841 } 842 843 vmm_ctl = 0; 844 /* select VMM table 0 */ 845 if (val & SEL_VMM_TBL0) 846 vmm_ctl |= BIT(0); 847 /* select VMM table 1 */ 848 if (val & SEL_VMM_TBL1) 849 vmm_ctl |= BIT(1); 850 /* enable VMM */ 851 if (val & EN_VMM) 852 vmm_ctl |= BIT(2); 853 854 if (vmm_ctl) { 855 struct sdio_cmd52 cmd; 856 857 cmd.read_write = 1; 858 cmd.function = 0; 859 cmd.raw = 0; 860 cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG; 861 cmd.data = vmm_ctl; 862 ret = wilc_sdio_cmd52(wilc, &cmd); 863 if (ret) { 864 dev_err(&func->dev, 865 "Failed cmd52, set (%02x) data (%d) ...\n", 866 cmd.address, __LINE__); 867 return ret; 868 } 869 } 870 return 0; 871 } 872 873 static int wilc_sdio_sync_ext(struct wilc *wilc, int nint) 874 { 875 struct sdio_func *func = dev_to_sdio_func(wilc->dev); 876 struct wilc_sdio *sdio_priv = wilc->bus_data; 877 u32 reg; 878 879 if (nint > MAX_NUM_INT) { 880 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint); 881 return -EINVAL; 882 } 883 884 /** 885 * Disable power sequencer 886 **/ 887 if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) { 888 dev_err(&func->dev, "Failed read misc reg...\n"); 889 return -EINVAL; 890 } 891 892 reg &= ~BIT(8); 893 if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) { 894 dev_err(&func->dev, "Failed write misc reg...\n"); 895 return -EINVAL; 896 } 897 898 if (sdio_priv->irq_gpio) { 899 u32 reg; 900 int ret, i; 901 902 /** 903 * interrupt pin mux select 904 **/ 905 ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); 906 if (ret) { 907 dev_err(&func->dev, "Failed read reg (%08x)...\n", 908 WILC_PIN_MUX_0); 909 return ret; 910 } 911 reg |= BIT(8); 912 ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); 913 if (ret) { 914 dev_err(&func->dev, "Failed write reg (%08x)...\n", 915 WILC_PIN_MUX_0); 916 return ret; 917 } 918 919 /** 920 * interrupt enable 921 **/ 922 ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); 923 if (ret) { 924 dev_err(&func->dev, "Failed read reg (%08x)...\n", 925 WILC_INTR_ENABLE); 926 return ret; 927 } 928 929 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 930 reg |= BIT((27 + i)); 931 ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); 932 if (ret) { 933 dev_err(&func->dev, "Failed write reg (%08x)...\n", 934 WILC_INTR_ENABLE); 935 return ret; 936 } 937 if (nint) { 938 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); 939 if (ret) { 940 dev_err(&func->dev, 941 "Failed read reg (%08x)...\n", 942 WILC_INTR2_ENABLE); 943 return ret; 944 } 945 946 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 947 reg |= BIT(i); 948 949 ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); 950 if (ret) { 951 dev_err(&func->dev, 952 "Failed write reg (%08x)...\n", 953 WILC_INTR2_ENABLE); 954 return ret; 955 } 956 } 957 } 958 return 0; 959 } 960 961 /* Global sdio HIF function table */ 962 static const struct wilc_hif_func wilc_hif_sdio = { 963 .hif_init = wilc_sdio_init, 964 .hif_deinit = wilc_sdio_deinit, 965 .hif_read_reg = wilc_sdio_read_reg, 966 .hif_write_reg = wilc_sdio_write_reg, 967 .hif_block_rx = wilc_sdio_read, 968 .hif_block_tx = wilc_sdio_write, 969 .hif_read_int = wilc_sdio_read_int, 970 .hif_clear_int_ext = wilc_sdio_clear_int_ext, 971 .hif_read_size = wilc_sdio_read_size, 972 .hif_block_tx_ext = wilc_sdio_write, 973 .hif_block_rx_ext = wilc_sdio_read, 974 .hif_sync_ext = wilc_sdio_sync_ext, 975 .enable_interrupt = wilc_sdio_enable_interrupt, 976 .disable_interrupt = wilc_sdio_disable_interrupt, 977 }; 978 979 static int wilc_sdio_resume(struct device *dev) 980 { 981 struct sdio_func *func = dev_to_sdio_func(dev); 982 struct wilc *wilc = sdio_get_drvdata(func); 983 984 dev_info(dev, "sdio resume\n"); 985 sdio_release_host(func); 986 chip_wakeup(wilc); 987 wilc_sdio_init(wilc, true); 988 989 if (wilc->suspend_event) 990 host_wakeup_notify(wilc); 991 992 chip_allow_sleep(wilc); 993 994 return 0; 995 } 996 997 static const struct of_device_id wilc_of_match[] = { 998 { .compatible = "microchip,wilc1000", }, 999 { /* sentinel */ } 1000 }; 1001 MODULE_DEVICE_TABLE(of, wilc_of_match); 1002 1003 static const struct dev_pm_ops wilc_sdio_pm_ops = { 1004 .suspend = wilc_sdio_suspend, 1005 .resume = wilc_sdio_resume, 1006 }; 1007 1008 static struct sdio_driver wilc_sdio_driver = { 1009 .name = SDIO_MODALIAS, 1010 .id_table = wilc_sdio_ids, 1011 .probe = wilc_sdio_probe, 1012 .remove = wilc_sdio_remove, 1013 .drv = { 1014 .pm = &wilc_sdio_pm_ops, 1015 .of_match_table = wilc_of_match, 1016 } 1017 }; 1018 module_driver(wilc_sdio_driver, 1019 sdio_register_driver, 1020 sdio_unregister_driver); 1021 MODULE_LICENSE("GPL"); 1022