1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef MT7601U_H 16 #define MT7601U_H 17 18 #include <linux/bitfield.h> 19 #include <linux/kernel.h> 20 #include <linux/device.h> 21 #include <linux/mutex.h> 22 #include <linux/usb.h> 23 #include <linux/completion.h> 24 #include <net/mac80211.h> 25 #include <linux/debugfs.h> 26 #include <linux/average.h> 27 28 #include "regs.h" 29 30 #define MT_CALIBRATE_INTERVAL (4 * HZ) 31 32 #define MT_FREQ_CAL_INIT_DELAY (30 * HZ) 33 #define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) 34 #define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) 35 36 #define MT_BBP_REG_VERSION 0x00 37 38 #define MT_USB_AGGR_SIZE_LIMIT 28 /* * 1024B */ 39 #define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ 40 #define MT_RX_ORDER 3 41 #define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) 42 43 struct mt7601u_dma_buf { 44 struct urb *urb; 45 void *buf; 46 dma_addr_t dma; 47 size_t len; 48 }; 49 50 struct mt7601u_mcu { 51 struct mutex mutex; 52 53 u8 msg_seq; 54 55 struct mt7601u_dma_buf resp; 56 struct completion resp_cmpl; 57 }; 58 59 struct mt7601u_freq_cal { 60 struct delayed_work work; 61 u8 freq; 62 bool enabled; 63 bool adjusting; 64 }; 65 66 struct mac_stats { 67 u64 rx_stat[6]; 68 u64 tx_stat[6]; 69 u64 aggr_stat[2]; 70 u64 aggr_n[32]; 71 u64 zero_len_del[2]; 72 }; 73 74 #define N_RX_ENTRIES 16 75 struct mt7601u_rx_queue { 76 struct mt7601u_dev *dev; 77 78 struct mt7601u_dma_buf_rx { 79 struct urb *urb; 80 struct page *p; 81 } e[N_RX_ENTRIES]; 82 83 unsigned int start; 84 unsigned int end; 85 unsigned int entries; 86 unsigned int pending; 87 }; 88 89 #define N_TX_ENTRIES 64 90 91 struct mt7601u_tx_queue { 92 struct mt7601u_dev *dev; 93 94 struct mt7601u_dma_buf_tx { 95 struct urb *urb; 96 struct sk_buff *skb; 97 } e[N_TX_ENTRIES]; 98 99 unsigned int start; 100 unsigned int end; 101 unsigned int entries; 102 unsigned int used; 103 unsigned int fifo_seq; 104 }; 105 106 /* WCID allocation: 107 * 0: mcast wcid 108 * 1: bssid wcid 109 * 1...: STAs 110 * ...7e: group wcids 111 * 7f: reserved 112 */ 113 #define N_WCIDS 128 114 #define GROUP_WCID(idx) (N_WCIDS - 2 - idx) 115 116 struct mt7601u_eeprom_params; 117 118 #define MT_EE_TEMPERATURE_SLOPE 39 119 #define MT_FREQ_OFFSET_INVALID -128 120 121 enum mt_temp_mode { 122 MT_TEMP_MODE_NORMAL, 123 MT_TEMP_MODE_HIGH, 124 MT_TEMP_MODE_LOW, 125 }; 126 127 enum mt_bw { 128 MT_BW_20, 129 MT_BW_40, 130 }; 131 132 enum { 133 MT7601U_STATE_INITIALIZED, 134 MT7601U_STATE_REMOVED, 135 MT7601U_STATE_WLAN_RUNNING, 136 MT7601U_STATE_MCU_RUNNING, 137 MT7601U_STATE_SCANNING, 138 MT7601U_STATE_READING_STATS, 139 MT7601U_STATE_MORE_STATS, 140 }; 141 142 DECLARE_EWMA(rssi, 10, 4); 143 144 /** 145 * struct mt7601u_dev - adapter structure 146 * @lock: protects @wcid->tx_rate. 147 * @mac_lock: locks out mac80211's tx status and rx paths. 148 * @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS 149 * flags in @state. 150 * @rx_lock: protects @rx_q. 151 * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. 152 * @mutex: ensures exclusive access from mac80211 callbacks. 153 * @vendor_req_mutex: protects @vend_buf, ensures atomicity of read/write 154 * accesses 155 * @reg_atomic_mutex: ensures atomicity of indirect register accesses 156 * (accesses to RF and BBP). 157 * @hw_atomic_mutex: ensures exclusive access to HW during critical 158 * operations (power management, channel switch). 159 */ 160 struct mt7601u_dev { 161 struct ieee80211_hw *hw; 162 struct device *dev; 163 164 unsigned long state; 165 166 struct mutex mutex; 167 168 unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG]; 169 170 struct cfg80211_chan_def chandef; 171 struct ieee80211_supported_band *sband_2g; 172 173 struct mt7601u_mcu mcu; 174 175 struct delayed_work cal_work; 176 struct delayed_work mac_work; 177 178 struct workqueue_struct *stat_wq; 179 struct delayed_work stat_work; 180 181 struct mt76_wcid *mon_wcid; 182 struct mt76_wcid __rcu *wcid[N_WCIDS]; 183 184 spinlock_t lock; 185 spinlock_t mac_lock; 186 187 const u16 *beacon_offsets; 188 189 u8 macaddr[ETH_ALEN]; 190 struct mt7601u_eeprom_params *ee; 191 192 struct mutex vendor_req_mutex; 193 void *vend_buf; 194 195 struct mutex reg_atomic_mutex; 196 struct mutex hw_atomic_mutex; 197 198 u32 rxfilter; 199 u32 debugfs_reg; 200 201 u8 out_eps[8]; 202 u8 in_eps[8]; 203 u16 out_max_packet; 204 u16 in_max_packet; 205 206 /* TX */ 207 spinlock_t tx_lock; 208 struct tasklet_struct tx_tasklet; 209 struct mt7601u_tx_queue *tx_q; 210 struct sk_buff_head tx_skb_done; 211 212 atomic_t avg_ampdu_len; 213 214 /* RX */ 215 spinlock_t rx_lock; 216 struct tasklet_struct rx_tasklet; 217 struct mt7601u_rx_queue rx_q; 218 219 /* Connection monitoring things */ 220 spinlock_t con_mon_lock; 221 u8 ap_bssid[ETH_ALEN]; 222 223 s8 bcn_freq_off; 224 u8 bcn_phy_mode; 225 226 struct ewma_rssi avg_rssi; 227 228 u8 agc_save; 229 230 struct mt7601u_freq_cal freq_cal; 231 232 bool tssi_read_trig; 233 234 s8 tssi_init; 235 s8 tssi_init_hvga; 236 s16 tssi_init_hvga_offset_db; 237 238 int prev_pwr_diff; 239 240 enum mt_temp_mode temp_mode; 241 int curr_temp; 242 int dpd_temp; 243 s8 raw_temp; 244 bool pll_lock_protect; 245 246 u8 bw; 247 bool chan_ext_below; 248 249 /* PA mode */ 250 u32 rf_pa_mode[2]; 251 252 struct mac_stats stats; 253 }; 254 255 struct mt7601u_tssi_params { 256 char tssi0; 257 int trgt_power; 258 }; 259 260 struct mt76_wcid { 261 u8 idx; 262 u8 hw_key_idx; 263 264 u16 tx_rate; 265 bool tx_rate_set; 266 u8 tx_rate_nss; 267 }; 268 269 struct mt76_vif { 270 u8 idx; 271 272 struct mt76_wcid group_wcid; 273 }; 274 275 struct mt76_sta { 276 struct mt76_wcid wcid; 277 u16 agg_ssn[IEEE80211_NUM_TIDS]; 278 }; 279 280 struct mt76_reg_pair { 281 u32 reg; 282 u32 value; 283 }; 284 285 struct mt7601u_rxwi; 286 287 extern const struct ieee80211_ops mt7601u_ops; 288 289 void mt7601u_init_debugfs(struct mt7601u_dev *dev); 290 291 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset); 292 void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val); 293 u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); 294 u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); 295 void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, 296 const void *data, int len); 297 298 int mt7601u_wait_asic_ready(struct mt7601u_dev *dev); 299 bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, 300 int timeout); 301 bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, 302 int timeout); 303 304 /* Compatibility with mt76 */ 305 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 306 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 307 308 static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset) 309 { 310 return mt7601u_rr(dev, offset); 311 } 312 313 static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val) 314 { 315 return mt7601u_wr(dev, offset, val); 316 } 317 318 static inline u32 319 mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) 320 { 321 return mt7601u_rmw(dev, offset, mask, val); 322 } 323 324 static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val) 325 { 326 return mt76_rmw(dev, offset, 0, val); 327 } 328 329 static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) 330 { 331 return mt76_rmw(dev, offset, val, 0); 332 } 333 334 int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, 335 const struct mt76_reg_pair *data, int len); 336 int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, 337 const u32 *data, int n); 338 void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr); 339 340 /* Init */ 341 struct mt7601u_dev *mt7601u_alloc_device(struct device *dev); 342 int mt7601u_init_hardware(struct mt7601u_dev *dev); 343 int mt7601u_register_device(struct mt7601u_dev *dev); 344 void mt7601u_cleanup(struct mt7601u_dev *dev); 345 346 int mt7601u_mac_start(struct mt7601u_dev *dev); 347 void mt7601u_mac_stop(struct mt7601u_dev *dev); 348 349 /* PHY */ 350 int mt7601u_phy_init(struct mt7601u_dev *dev); 351 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev); 352 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path); 353 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path); 354 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw); 355 void mt7601u_agc_save(struct mt7601u_dev *dev); 356 void mt7601u_agc_restore(struct mt7601u_dev *dev); 357 int mt7601u_phy_set_channel(struct mt7601u_dev *dev, 358 struct cfg80211_chan_def *chandef); 359 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev); 360 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, 361 struct mt7601u_rxwi *rxwi, u16 rate); 362 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, 363 struct ieee80211_bss_conf *info); 364 365 /* MAC */ 366 void mt7601u_mac_work(struct work_struct *work); 367 void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, 368 int ht_mode); 369 void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb); 370 void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval); 371 void 372 mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac); 373 void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev); 374 375 /* TX */ 376 void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, 377 struct sk_buff *skb); 378 int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 379 u16 queue, const struct ieee80211_tx_queue_params *params); 380 void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb); 381 void mt7601u_tx_stat(struct work_struct *work); 382 383 /* util */ 384 void mt76_remove_hdr_pad(struct sk_buff *skb); 385 int mt76_insert_hdr_pad(struct sk_buff *skb); 386 387 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below); 388 389 static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below) 390 { 391 return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below); 392 } 393 394 int mt7601u_dma_init(struct mt7601u_dev *dev); 395 void mt7601u_dma_cleanup(struct mt7601u_dev *dev); 396 397 int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, 398 struct mt76_wcid *wcid, int hw_q); 399 400 #endif 401