1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef MT7601U_H 16 #define MT7601U_H 17 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/mutex.h> 21 #include <linux/usb.h> 22 #include <linux/completion.h> 23 #include <net/mac80211.h> 24 #include <linux/debugfs.h> 25 26 #include "regs.h" 27 #include "util.h" 28 29 #define MT_CALIBRATE_INTERVAL (4 * HZ) 30 31 #define MT_FREQ_CAL_INIT_DELAY (30 * HZ) 32 #define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) 33 #define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) 34 35 #define MT_BBP_REG_VERSION 0x00 36 37 #define MT_USB_AGGR_SIZE_LIMIT 28 /* * 1024B */ 38 #define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ 39 #define MT_RX_ORDER 3 40 #define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) 41 42 struct mt7601u_dma_buf { 43 struct urb *urb; 44 void *buf; 45 dma_addr_t dma; 46 size_t len; 47 }; 48 49 struct mt7601u_mcu { 50 struct mutex mutex; 51 52 u8 msg_seq; 53 54 struct mt7601u_dma_buf resp; 55 struct completion resp_cmpl; 56 }; 57 58 struct mt7601u_freq_cal { 59 struct delayed_work work; 60 u8 freq; 61 bool enabled; 62 bool adjusting; 63 }; 64 65 struct mac_stats { 66 u64 rx_stat[6]; 67 u64 tx_stat[6]; 68 u64 aggr_stat[2]; 69 u64 aggr_n[32]; 70 u64 zero_len_del[2]; 71 }; 72 73 #define N_RX_ENTRIES 16 74 struct mt7601u_rx_queue { 75 struct mt7601u_dev *dev; 76 77 struct mt7601u_dma_buf_rx { 78 struct urb *urb; 79 struct page *p; 80 } e[N_RX_ENTRIES]; 81 82 unsigned int start; 83 unsigned int end; 84 unsigned int entries; 85 unsigned int pending; 86 }; 87 88 #define N_TX_ENTRIES 64 89 90 struct mt7601u_tx_queue { 91 struct mt7601u_dev *dev; 92 93 struct mt7601u_dma_buf_tx { 94 struct urb *urb; 95 struct sk_buff *skb; 96 } e[N_TX_ENTRIES]; 97 98 unsigned int start; 99 unsigned int end; 100 unsigned int entries; 101 unsigned int used; 102 unsigned int fifo_seq; 103 }; 104 105 /* WCID allocation: 106 * 0: mcast wcid 107 * 1: bssid wcid 108 * 1...: STAs 109 * ...7e: group wcids 110 * 7f: reserved 111 */ 112 #define N_WCIDS 128 113 #define GROUP_WCID(idx) (N_WCIDS - 2 - idx) 114 115 struct mt7601u_eeprom_params; 116 117 #define MT_EE_TEMPERATURE_SLOPE 39 118 #define MT_FREQ_OFFSET_INVALID -128 119 120 enum mt_temp_mode { 121 MT_TEMP_MODE_NORMAL, 122 MT_TEMP_MODE_HIGH, 123 MT_TEMP_MODE_LOW, 124 }; 125 126 enum mt_bw { 127 MT_BW_20, 128 MT_BW_40, 129 }; 130 131 enum { 132 MT7601U_STATE_INITIALIZED, 133 MT7601U_STATE_REMOVED, 134 MT7601U_STATE_WLAN_RUNNING, 135 MT7601U_STATE_MCU_RUNNING, 136 MT7601U_STATE_SCANNING, 137 MT7601U_STATE_READING_STATS, 138 MT7601U_STATE_MORE_STATS, 139 }; 140 141 /** 142 * struct mt7601u_dev - adapter structure 143 * @lock: protects @wcid->tx_rate. 144 * @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS 145 flags in @state. 146 * @rx_lock: protects @rx_q. 147 * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. 148 * @mutex: ensures exclusive access from mac80211 callbacks. 149 * @vendor_req_mutex: ensures atomicity of vendor requests. 150 * @reg_atomic_mutex: ensures atomicity of indirect register accesses 151 * (accesses to RF and BBP). 152 * @hw_atomic_mutex: ensures exclusive access to HW during critical 153 * operations (power management, channel switch). 154 */ 155 struct mt7601u_dev { 156 struct ieee80211_hw *hw; 157 struct device *dev; 158 159 unsigned long state; 160 161 struct mutex mutex; 162 163 unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG]; 164 165 struct cfg80211_chan_def chandef; 166 struct ieee80211_supported_band *sband_2g; 167 168 struct mt7601u_mcu mcu; 169 170 struct delayed_work cal_work; 171 struct delayed_work mac_work; 172 173 struct workqueue_struct *stat_wq; 174 struct delayed_work stat_work; 175 176 struct mt76_wcid *mon_wcid; 177 struct mt76_wcid __rcu *wcid[N_WCIDS]; 178 179 spinlock_t lock; 180 181 const u16 *beacon_offsets; 182 183 u8 macaddr[ETH_ALEN]; 184 struct mt7601u_eeprom_params *ee; 185 186 struct mutex vendor_req_mutex; 187 struct mutex reg_atomic_mutex; 188 struct mutex hw_atomic_mutex; 189 190 u32 rxfilter; 191 u32 debugfs_reg; 192 193 u8 out_eps[8]; 194 u8 in_eps[8]; 195 u16 out_max_packet; 196 u16 in_max_packet; 197 198 /* TX */ 199 spinlock_t tx_lock; 200 struct mt7601u_tx_queue *tx_q; 201 202 atomic_t avg_ampdu_len; 203 204 /* RX */ 205 spinlock_t rx_lock; 206 struct tasklet_struct rx_tasklet; 207 struct mt7601u_rx_queue rx_q; 208 209 /* Connection monitoring things */ 210 spinlock_t con_mon_lock; 211 u8 ap_bssid[ETH_ALEN]; 212 213 s8 bcn_freq_off; 214 u8 bcn_phy_mode; 215 216 int avg_rssi; /* starts at 0 and converges */ 217 218 u8 agc_save; 219 220 struct mt7601u_freq_cal freq_cal; 221 222 bool tssi_read_trig; 223 224 s8 tssi_init; 225 s8 tssi_init_hvga; 226 s16 tssi_init_hvga_offset_db; 227 228 int prev_pwr_diff; 229 230 enum mt_temp_mode temp_mode; 231 int curr_temp; 232 int dpd_temp; 233 s8 raw_temp; 234 bool pll_lock_protect; 235 236 u8 bw; 237 bool chan_ext_below; 238 239 /* PA mode */ 240 u32 rf_pa_mode[2]; 241 242 struct mac_stats stats; 243 }; 244 245 struct mt7601u_tssi_params { 246 char tssi0; 247 int trgt_power; 248 }; 249 250 struct mt76_wcid { 251 u8 idx; 252 u8 hw_key_idx; 253 254 u16 tx_rate; 255 bool tx_rate_set; 256 u8 tx_rate_nss; 257 }; 258 259 struct mt76_vif { 260 u8 idx; 261 262 struct mt76_wcid group_wcid; 263 }; 264 265 struct mt76_sta { 266 struct mt76_wcid wcid; 267 u16 agg_ssn[IEEE80211_NUM_TIDS]; 268 }; 269 270 struct mt76_reg_pair { 271 u32 reg; 272 u32 value; 273 }; 274 275 struct mt7601u_rxwi; 276 277 extern const struct ieee80211_ops mt7601u_ops; 278 279 void mt7601u_init_debugfs(struct mt7601u_dev *dev); 280 281 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset); 282 void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val); 283 u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); 284 u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); 285 void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, 286 const void *data, int len); 287 288 int mt7601u_wait_asic_ready(struct mt7601u_dev *dev); 289 bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, 290 int timeout); 291 bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, 292 int timeout); 293 294 /* Compatibility with mt76 */ 295 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 296 mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val)) 297 298 static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset) 299 { 300 return mt7601u_rr(dev, offset); 301 } 302 303 static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val) 304 { 305 return mt7601u_wr(dev, offset, val); 306 } 307 308 static inline u32 309 mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) 310 { 311 return mt7601u_rmw(dev, offset, mask, val); 312 } 313 314 static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val) 315 { 316 return mt76_rmw(dev, offset, 0, val); 317 } 318 319 static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) 320 { 321 return mt76_rmw(dev, offset, val, 0); 322 } 323 324 int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, 325 const struct mt76_reg_pair *data, int len); 326 int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, 327 const u32 *data, int n); 328 void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr); 329 330 /* Init */ 331 struct mt7601u_dev *mt7601u_alloc_device(struct device *dev); 332 int mt7601u_init_hardware(struct mt7601u_dev *dev); 333 int mt7601u_register_device(struct mt7601u_dev *dev); 334 void mt7601u_cleanup(struct mt7601u_dev *dev); 335 336 int mt7601u_mac_start(struct mt7601u_dev *dev); 337 void mt7601u_mac_stop(struct mt7601u_dev *dev); 338 339 /* PHY */ 340 int mt7601u_phy_init(struct mt7601u_dev *dev); 341 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev); 342 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path); 343 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path); 344 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw); 345 void mt7601u_agc_save(struct mt7601u_dev *dev); 346 void mt7601u_agc_restore(struct mt7601u_dev *dev); 347 int mt7601u_phy_set_channel(struct mt7601u_dev *dev, 348 struct cfg80211_chan_def *chandef); 349 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev); 350 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, 351 struct mt7601u_rxwi *rxwi, u16 rate); 352 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, 353 struct ieee80211_bss_conf *info); 354 355 /* MAC */ 356 void mt7601u_mac_work(struct work_struct *work); 357 void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, 358 int ht_mode); 359 void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb); 360 void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval); 361 void 362 mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac); 363 void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev); 364 365 /* TX */ 366 void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, 367 struct sk_buff *skb); 368 int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 369 u16 queue, const struct ieee80211_tx_queue_params *params); 370 void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb); 371 void mt7601u_tx_stat(struct work_struct *work); 372 373 /* util */ 374 void mt76_remove_hdr_pad(struct sk_buff *skb); 375 int mt76_insert_hdr_pad(struct sk_buff *skb); 376 377 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below); 378 379 static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below) 380 { 381 return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below); 382 } 383 384 int mt7601u_dma_init(struct mt7601u_dev *dev); 385 void mt7601u_dma_cleanup(struct mt7601u_dev *dev); 386 387 int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, 388 struct mt76_wcid *wcid, int hw_q); 389 390 #endif 391