1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __MT76_MAC_H 16 #define __MT76_MAC_H 17 18 struct mt76_tx_status { 19 u8 valid:1; 20 u8 success:1; 21 u8 aggr:1; 22 u8 ack_req:1; 23 u8 is_probe:1; 24 u8 wcid; 25 u8 pktid; 26 u8 retry; 27 u16 rate; 28 } __packed __aligned(2); 29 30 /* Note: values in original "RSSI" and "SNR" fields are not actually what they 31 * are called for MT7601U, names used by this driver are educated guesses 32 * (see vendor mac/ral_omac.c). 33 */ 34 struct mt7601u_rxwi { 35 __le32 rxinfo; 36 37 __le32 ctl; 38 39 __le16 frag_sn; 40 __le16 rate; 41 42 u8 unknown; 43 u8 zero[3]; 44 45 u8 snr; 46 u8 ant; 47 u8 gain; 48 u8 freq_off; 49 50 __le32 resv2; 51 __le32 expert_ant; 52 } __packed __aligned(4); 53 54 #define MT_RXINFO_BA BIT(0) 55 #define MT_RXINFO_DATA BIT(1) 56 #define MT_RXINFO_NULL BIT(2) 57 #define MT_RXINFO_FRAG BIT(3) 58 #define MT_RXINFO_U2M BIT(4) 59 #define MT_RXINFO_MULTICAST BIT(5) 60 #define MT_RXINFO_BROADCAST BIT(6) 61 #define MT_RXINFO_MYBSS BIT(7) 62 #define MT_RXINFO_CRCERR BIT(8) 63 #define MT_RXINFO_ICVERR BIT(9) 64 #define MT_RXINFO_MICERR BIT(10) 65 #define MT_RXINFO_AMSDU BIT(11) 66 #define MT_RXINFO_HTC BIT(12) 67 #define MT_RXINFO_RSSI BIT(13) 68 #define MT_RXINFO_L2PAD BIT(14) 69 #define MT_RXINFO_AMPDU BIT(15) 70 #define MT_RXINFO_DECRYPT BIT(16) 71 #define MT_RXINFO_BSSIDX3 BIT(17) 72 #define MT_RXINFO_WAPI_KEY BIT(18) 73 #define MT_RXINFO_PN_LEN GENMASK(21, 19) 74 #define MT_RXINFO_SW_PKT_80211 BIT(22) 75 #define MT_RXINFO_TCP_SUM_BYPASS BIT(28) 76 #define MT_RXINFO_IP_SUM_BYPASS BIT(29) 77 #define MT_RXINFO_TCP_SUM_ERR BIT(30) 78 #define MT_RXINFO_IP_SUM_ERR BIT(31) 79 80 #define MT_RXWI_CTL_WCID GENMASK(7, 0) 81 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) 82 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) 83 #define MT_RXWI_CTL_UDF GENMASK(15, 13) 84 #define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16) 85 #define MT_RXWI_CTL_TID GENMASK(31, 28) 86 87 #define MT_RXWI_FRAG GENMASK(3, 0) 88 #define MT_RXWI_SN GENMASK(15, 4) 89 90 #define MT_RXWI_RATE_MCS GENMASK(6, 0) 91 #define MT_RXWI_RATE_BW BIT(7) 92 #define MT_RXWI_RATE_SGI BIT(8) 93 #define MT_RXWI_RATE_STBC GENMASK(10, 9) 94 #define MT_RXWI_RATE_ETXBF BIT(11) 95 #define MT_RXWI_RATE_SND BIT(12) 96 #define MT_RXWI_RATE_ITXBF BIT(13) 97 #define MT_RXWI_RATE_PHY GENMASK(15, 14) 98 99 #define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0) 100 #define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6) 101 #define MT_RXWI_ANT_AUX_LNA BIT(7) 102 103 #define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0) 104 105 enum mt76_phy_type { 106 MT_PHY_TYPE_CCK, 107 MT_PHY_TYPE_OFDM, 108 MT_PHY_TYPE_HT, 109 MT_PHY_TYPE_HT_GF, 110 }; 111 112 enum mt76_phy_bandwidth { 113 MT_PHY_BW_20, 114 MT_PHY_BW_40, 115 }; 116 117 struct mt76_txwi { 118 __le16 flags; 119 __le16 rate_ctl; 120 121 u8 ack_ctl; 122 u8 wcid; 123 __le16 len_ctl; 124 125 __le32 iv; 126 127 __le32 eiv; 128 129 u8 aid; 130 u8 txstream; 131 __le16 ctl; 132 } __packed __aligned(4); 133 134 #define MT_TXWI_FLAGS_FRAG BIT(0) 135 #define MT_TXWI_FLAGS_MMPS BIT(1) 136 #define MT_TXWI_FLAGS_CFACK BIT(2) 137 #define MT_TXWI_FLAGS_TS BIT(3) 138 #define MT_TXWI_FLAGS_AMPDU BIT(4) 139 #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) 140 #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) 141 #define MT_TXWI_FLAGS_CWMIN GENMASK(12, 10) 142 #define MT_TXWI_FLAGS_NO_RATE_FALLBACK BIT(13) 143 #define MT_TXWI_FLAGS_TX_RPT BIT(14) 144 #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) 145 146 #define MT_TXWI_RATE_MCS GENMASK(6, 0) 147 #define MT_TXWI_RATE_BW BIT(7) 148 #define MT_TXWI_RATE_SGI BIT(8) 149 #define MT_TXWI_RATE_STBC GENMASK(10, 9) 150 #define MT_TXWI_RATE_PHY_MODE GENMASK(15, 14) 151 152 #define MT_TXWI_ACK_CTL_REQ BIT(0) 153 #define MT_TXWI_ACK_CTL_NSEQ BIT(1) 154 #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) 155 156 #define MT_TXWI_LEN_BYTE_CNT GENMASK(11, 0) 157 #define MT_TXWI_LEN_PKTID GENMASK(15, 12) 158 159 #define MT_TXWI_CTL_TX_POWER_ADJ GENMASK(3, 0) 160 #define MT_TXWI_CTL_CHAN_CHECK_PKT BIT(4) 161 #define MT_TXWI_CTL_PIFS_REV BIT(6) 162 163 u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, 164 u8 *data, void *rxi); 165 int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, 166 struct ieee80211_key_conf *key); 167 void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid, 168 const struct ieee80211_tx_rate *rate); 169 170 int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx, 171 struct ieee80211_key_conf *key); 172 u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, 173 const struct ieee80211_tx_rate *rate, u8 *nss_val); 174 struct mt76_tx_status 175 mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev); 176 void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat); 177 void mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *addr); 178 179 #endif 180