1 /*
2  * (c) Copyright 2002-2010, Ralink Technology, Inc.
3  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #ifndef __MT7601U_PHY_INITVALS_H
16 #define __MT7601U_PHY_INITVALS_H
17 
18 #define RF_REG_PAIR(bank, reg, value)				\
19 	{ MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value }
20 
21 static const struct mt76_reg_pair rf_central[] = {
22 	/* Bank 0 - for central blocks: BG, PLL, XTAL, LO, ADC/DAC */
23 	RF_REG_PAIR(0,	 0, 0x02),
24 	RF_REG_PAIR(0,	 1, 0x01),
25 	RF_REG_PAIR(0,	 2, 0x11),
26 	RF_REG_PAIR(0,	 3, 0xff),
27 	RF_REG_PAIR(0,	 4, 0x0a),
28 	RF_REG_PAIR(0,	 5, 0x20),
29 	RF_REG_PAIR(0,	 6, 0x00),
30 	/* B/G */
31 	RF_REG_PAIR(0,	 7, 0x00),
32 	RF_REG_PAIR(0,	 8, 0x00),
33 	RF_REG_PAIR(0,	 9, 0x00),
34 	RF_REG_PAIR(0,	10, 0x00),
35 	RF_REG_PAIR(0,	11, 0x21),
36 	/* XO */
37 	RF_REG_PAIR(0,	13, 0x00),		/* 40mhz xtal */
38 	/* RF_REG_PAIR(0,	13, 0x13), */	/* 20mhz xtal */
39 	RF_REG_PAIR(0,	14, 0x7c),
40 	RF_REG_PAIR(0,	15, 0x22),
41 	RF_REG_PAIR(0,	16, 0x80),
42 	/* PLL */
43 	RF_REG_PAIR(0,	17, 0x99),
44 	RF_REG_PAIR(0,	18, 0x99),
45 	RF_REG_PAIR(0,	19, 0x09),
46 	RF_REG_PAIR(0,	20, 0x50),
47 	RF_REG_PAIR(0,	21, 0xb0),
48 	RF_REG_PAIR(0,	22, 0x00),
49 	RF_REG_PAIR(0,	23, 0xc5),
50 	RF_REG_PAIR(0,	24, 0xfc),
51 	RF_REG_PAIR(0,	25, 0x40),
52 	RF_REG_PAIR(0,	26, 0x4d),
53 	RF_REG_PAIR(0,	27, 0x02),
54 	RF_REG_PAIR(0,	28, 0x72),
55 	RF_REG_PAIR(0,	29, 0x01),
56 	RF_REG_PAIR(0,	30, 0x00),
57 	RF_REG_PAIR(0,	31, 0x00),
58 	/* test ports */
59 	RF_REG_PAIR(0,	32, 0x00),
60 	RF_REG_PAIR(0,	33, 0x00),
61 	RF_REG_PAIR(0,	34, 0x23),
62 	RF_REG_PAIR(0,	35, 0x01), /* change setting to reduce spurs */
63 	RF_REG_PAIR(0,	36, 0x00),
64 	RF_REG_PAIR(0,	37, 0x00),
65 	/* ADC/DAC */
66 	RF_REG_PAIR(0,	38, 0x00),
67 	RF_REG_PAIR(0,	39, 0x20),
68 	RF_REG_PAIR(0,	40, 0x00),
69 	RF_REG_PAIR(0,	41, 0xd0),
70 	RF_REG_PAIR(0,	42, 0x1b),
71 	RF_REG_PAIR(0,	43, 0x02),
72 	RF_REG_PAIR(0,	44, 0x00),
73 };
74 
75 static const struct mt76_reg_pair rf_channel[] = {
76 	RF_REG_PAIR(4,	 0, 0x01),
77 	RF_REG_PAIR(4,	 1, 0x00),
78 	RF_REG_PAIR(4,	 2, 0x00),
79 	RF_REG_PAIR(4,	 3, 0x00),
80 	/* LDO */
81 	RF_REG_PAIR(4,	 4, 0x00),
82 	RF_REG_PAIR(4,	 5, 0x08),
83 	RF_REG_PAIR(4,	 6, 0x00),
84 	/* RX */
85 	RF_REG_PAIR(4,	 7, 0x5b),
86 	RF_REG_PAIR(4,	 8, 0x52),
87 	RF_REG_PAIR(4,	 9, 0xb6),
88 	RF_REG_PAIR(4,	10, 0x57),
89 	RF_REG_PAIR(4,	11, 0x33),
90 	RF_REG_PAIR(4,	12, 0x22),
91 	RF_REG_PAIR(4,	13, 0x3d),
92 	RF_REG_PAIR(4,	14, 0x3e),
93 	RF_REG_PAIR(4,	15, 0x13),
94 	RF_REG_PAIR(4,	16, 0x22),
95 	RF_REG_PAIR(4,	17, 0x23),
96 	RF_REG_PAIR(4,	18, 0x02),
97 	RF_REG_PAIR(4,	19, 0xa4),
98 	RF_REG_PAIR(4,	20, 0x01),
99 	RF_REG_PAIR(4,	21, 0x12),
100 	RF_REG_PAIR(4,	22, 0x80),
101 	RF_REG_PAIR(4,	23, 0xb3),
102 	RF_REG_PAIR(4,	24, 0x00), /* reserved */
103 	RF_REG_PAIR(4,	25, 0x00), /* reserved */
104 	RF_REG_PAIR(4,	26, 0x00), /* reserved */
105 	RF_REG_PAIR(4,	27, 0x00), /* reserved */
106 	/* LOGEN */
107 	RF_REG_PAIR(4,	28, 0x18),
108 	RF_REG_PAIR(4,	29, 0xee),
109 	RF_REG_PAIR(4,	30, 0x6b),
110 	RF_REG_PAIR(4,	31, 0x31),
111 	RF_REG_PAIR(4,	32, 0x5d),
112 	RF_REG_PAIR(4,	33, 0x00), /* reserved */
113 	/* TX */
114 	RF_REG_PAIR(4,	34, 0x96),
115 	RF_REG_PAIR(4,	35, 0x55),
116 	RF_REG_PAIR(4,	36, 0x08),
117 	RF_REG_PAIR(4,	37, 0xbb),
118 	RF_REG_PAIR(4,	38, 0xb3),
119 	RF_REG_PAIR(4,	39, 0xb3),
120 	RF_REG_PAIR(4,	40, 0x03),
121 	RF_REG_PAIR(4,	41, 0x00), /* reserved */
122 	RF_REG_PAIR(4,	42, 0x00), /* reserved */
123 	RF_REG_PAIR(4,	43, 0xc5),
124 	RF_REG_PAIR(4,	44, 0xc5),
125 	RF_REG_PAIR(4,	45, 0xc5),
126 	RF_REG_PAIR(4,	46, 0x07),
127 	RF_REG_PAIR(4,	47, 0xa8),
128 	RF_REG_PAIR(4,	48, 0xef),
129 	RF_REG_PAIR(4,	49, 0x1a),
130 	/* PA */
131 	RF_REG_PAIR(4,	54, 0x07),
132 	RF_REG_PAIR(4,	55, 0xa7),
133 	RF_REG_PAIR(4,	56, 0xcc),
134 	RF_REG_PAIR(4,	57, 0x14),
135 	RF_REG_PAIR(4,	58, 0x07),
136 	RF_REG_PAIR(4,	59, 0xa8),
137 	RF_REG_PAIR(4,	60, 0xd7),
138 	RF_REG_PAIR(4,	61, 0x10),
139 	RF_REG_PAIR(4,	62, 0x1c),
140 	RF_REG_PAIR(4,	63, 0x00), /* reserved */
141 };
142 
143 static const struct mt76_reg_pair rf_vga[] = {
144 	RF_REG_PAIR(5,	 0, 0x47),
145 	RF_REG_PAIR(5,	 1, 0x00),
146 	RF_REG_PAIR(5,	 2, 0x00),
147 	RF_REG_PAIR(5,	 3, 0x08),
148 	RF_REG_PAIR(5,	 4, 0x04),
149 	RF_REG_PAIR(5,	 5, 0x20),
150 	RF_REG_PAIR(5,	 6, 0x3a),
151 	RF_REG_PAIR(5,	 7, 0x3a),
152 	RF_REG_PAIR(5,	 8, 0x00),
153 	RF_REG_PAIR(5,	 9, 0x00),
154 	RF_REG_PAIR(5,	10, 0x10),
155 	RF_REG_PAIR(5,	11, 0x10),
156 	RF_REG_PAIR(5,	12, 0x10),
157 	RF_REG_PAIR(5,	13, 0x10),
158 	RF_REG_PAIR(5,	14, 0x10),
159 	RF_REG_PAIR(5,	15, 0x20),
160 	RF_REG_PAIR(5,	16, 0x22),
161 	RF_REG_PAIR(5,	17, 0x7c),
162 	RF_REG_PAIR(5,	18, 0x00),
163 	RF_REG_PAIR(5,	19, 0x00),
164 	RF_REG_PAIR(5,	20, 0x00),
165 	RF_REG_PAIR(5,	21, 0xf1),
166 	RF_REG_PAIR(5,	22, 0x11),
167 	RF_REG_PAIR(5,	23, 0x02),
168 	RF_REG_PAIR(5,	24, 0x41),
169 	RF_REG_PAIR(5,	25, 0x20),
170 	RF_REG_PAIR(5,	26, 0x00),
171 	RF_REG_PAIR(5,	27, 0xd7),
172 	RF_REG_PAIR(5,	28, 0xa2),
173 	RF_REG_PAIR(5,	29, 0x20),
174 	RF_REG_PAIR(5,	30, 0x49),
175 	RF_REG_PAIR(5,	31, 0x20),
176 	RF_REG_PAIR(5,	32, 0x04),
177 	RF_REG_PAIR(5,	33, 0xf1),
178 	RF_REG_PAIR(5,	34, 0xa1),
179 	RF_REG_PAIR(5,	35, 0x01),
180 	RF_REG_PAIR(5,	41, 0x00),
181 	RF_REG_PAIR(5,	42, 0x00),
182 	RF_REG_PAIR(5,	43, 0x00),
183 	RF_REG_PAIR(5,	44, 0x00),
184 	RF_REG_PAIR(5,	45, 0x00),
185 	RF_REG_PAIR(5,	46, 0x00),
186 	RF_REG_PAIR(5,	47, 0x00),
187 	RF_REG_PAIR(5,	48, 0x00),
188 	RF_REG_PAIR(5,	49, 0x00),
189 	RF_REG_PAIR(5,	50, 0x00),
190 	RF_REG_PAIR(5,	51, 0x00),
191 	RF_REG_PAIR(5,	52, 0x00),
192 	RF_REG_PAIR(5,	53, 0x00),
193 	RF_REG_PAIR(5,	54, 0x00),
194 	RF_REG_PAIR(5,	55, 0x00),
195 	RF_REG_PAIR(5,	56, 0x00),
196 	RF_REG_PAIR(5,	57, 0x00),
197 	RF_REG_PAIR(5,	58, 0x31),
198 	RF_REG_PAIR(5,	59, 0x31),
199 	RF_REG_PAIR(5,	60, 0x0a),
200 	RF_REG_PAIR(5,	61, 0x02),
201 	RF_REG_PAIR(5,	62, 0x00),
202 	RF_REG_PAIR(5,	63, 0x00),
203 };
204 
205 /* TODO: BBP178 is set to 0xff for "CCK CH14 OBW" which overrides the settings
206  *	 from channel switching. Seems stupid at best.
207  */
208 static const struct mt76_reg_pair bbp_high_temp[] = {
209 	{  75, 0x60 },
210 	{  92, 0x02 },
211 	{ 178, 0xff }, /* For CCK CH14 OBW */
212 	{ 195, 0x88 }, { 196, 0x60 },
213 }, bbp_high_temp_bw20[] = {
214 	{  69, 0x12 },
215 	{  91, 0x07 },
216 	{ 195, 0x23 }, { 196, 0x17 },
217 	{ 195, 0x24 }, { 196, 0x06 },
218 	{ 195, 0x81 }, { 196, 0x12 },
219 	{ 195, 0x83 }, { 196, 0x17 },
220 }, bbp_high_temp_bw40[] = {
221 	{  69, 0x15 },
222 	{  91, 0x04 },
223 	{ 195, 0x23 }, { 196, 0x12 },
224 	{ 195, 0x24 }, { 196, 0x08 },
225 	{ 195, 0x81 }, { 196, 0x15 },
226 	{ 195, 0x83 }, { 196, 0x16 },
227 }, bbp_low_temp[] = {
228 	{ 178, 0xff }, /* For CCK CH14 OBW */
229 }, bbp_low_temp_bw20[] = {
230 	{  69, 0x12 },
231 	{  75, 0x5e },
232 	{  91, 0x07 },
233 	{  92, 0x02 },
234 	{ 195, 0x23 }, { 196, 0x17 },
235 	{ 195, 0x24 }, { 196, 0x06 },
236 	{ 195, 0x81 }, { 196, 0x12 },
237 	{ 195, 0x83 }, { 196, 0x17 },
238 	{ 195, 0x88 }, { 196, 0x5e },
239 }, bbp_low_temp_bw40[] = {
240 	{  69, 0x15 },
241 	{  75, 0x5c },
242 	{  91, 0x04 },
243 	{  92, 0x03 },
244 	{ 195, 0x23 }, { 196, 0x10 },
245 	{ 195, 0x24 }, { 196, 0x08 },
246 	{ 195, 0x81 }, { 196, 0x15 },
247 	{ 195, 0x83 }, { 196, 0x16 },
248 	{ 195, 0x88 }, { 196, 0x5b },
249 }, bbp_normal_temp[] = {
250 	{  75, 0x60 },
251 	{  92, 0x02 },
252 	{ 178, 0xff }, /* For CCK CH14 OBW */
253 	{ 195, 0x88 }, { 196, 0x60 },
254 }, bbp_normal_temp_bw20[] = {
255 	{  69, 0x12 },
256 	{  91, 0x07 },
257 	{ 195, 0x23 }, { 196, 0x17 },
258 	{ 195, 0x24 }, { 196, 0x06 },
259 	{ 195, 0x81 }, { 196, 0x12 },
260 	{ 195, 0x83 }, { 196, 0x17 },
261 }, bbp_normal_temp_bw40[] = {
262 	{  69, 0x15 },
263 	{  91, 0x04 },
264 	{ 195, 0x23 }, { 196, 0x12 },
265 	{ 195, 0x24 }, { 196, 0x08 },
266 	{ 195, 0x81 }, { 196, 0x15 },
267 	{ 195, 0x83 }, { 196, 0x16 },
268 };
269 
270 #define BBP_TABLE(arr) { arr, ARRAY_SIZE(arr), }
271 
272 static const struct reg_table {
273 	const struct mt76_reg_pair *regs;
274 	size_t n;
275 } bbp_mode_table[3][3] = {
276 	{
277 		BBP_TABLE(bbp_normal_temp_bw20),
278 		BBP_TABLE(bbp_normal_temp_bw40),
279 		BBP_TABLE(bbp_normal_temp),
280 	}, {
281 		BBP_TABLE(bbp_high_temp_bw20),
282 		BBP_TABLE(bbp_high_temp_bw40),
283 		BBP_TABLE(bbp_high_temp),
284 	}, {
285 		BBP_TABLE(bbp_low_temp_bw20),
286 		BBP_TABLE(bbp_low_temp_bw40),
287 		BBP_TABLE(bbp_low_temp),
288 	}
289 };
290 
291 #endif
292