1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * (c) Copyright 2002-2010, Ralink Technology, Inc.
4  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
5  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
6  */
7 
8 #include "mt7601u.h"
9 #include "eeprom.h"
10 #include "trace.h"
11 #include "mcu.h"
12 
13 #include "initvals.h"
14 
15 static void
16 mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable)
17 {
18 	int i;
19 
20 	/* Note: we don't turn off WLAN_CLK because that makes the device
21 	 *	 not respond properly on the probe path.
22 	 *	 In case anyone (PSM?) wants to use this function we can
23 	 *	 bring the clock stuff back and fixup the probe path.
24 	 */
25 
26 	if (enable)
27 		val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
28 			MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
29 	else
30 		val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
31 
32 	mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
33 	udelay(20);
34 
35 	if (enable) {
36 		set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
37 	} else {
38 		clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
39 		return;
40 	}
41 
42 	for (i = 200; i; i--) {
43 		val = mt7601u_rr(dev, MT_CMB_CTRL);
44 
45 		if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD)
46 			break;
47 
48 		udelay(20);
49 	}
50 
51 	/* Note: vendor driver tries to disable/enable wlan here and retry
52 	 *       but the code which does it is so buggy it must have never
53 	 *       triggered, so don't bother.
54 	 */
55 	if (!i)
56 		dev_err(dev->dev, "Error: PLL and XTAL check failed!\n");
57 }
58 
59 static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset)
60 {
61 	u32 val;
62 
63 	mutex_lock(&dev->hw_atomic_mutex);
64 
65 	val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL);
66 
67 	if (reset) {
68 		val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
69 		val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
70 
71 		if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
72 			val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
73 				MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
74 			mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
75 			udelay(20);
76 
77 			val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
78 				 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
79 		}
80 	}
81 
82 	mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
83 	udelay(20);
84 
85 	mt7601u_set_wlan_state(dev, val, enable);
86 
87 	mutex_unlock(&dev->hw_atomic_mutex);
88 }
89 
90 static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev)
91 {
92 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR |
93 					  MT_MAC_SYS_CTRL_RESET_BBP));
94 	mt7601u_wr(dev, MT_USB_DMA_CFG, 0);
95 	msleep(1);
96 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
97 }
98 
99 static void mt7601u_init_usb_dma(struct mt7601u_dev *dev)
100 {
101 	u32 val;
102 
103 	val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |
104 	      FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT,
105 			 MT_USB_AGGR_SIZE_LIMIT) |
106 	      MT_USB_DMA_CFG_RX_BULK_EN |
107 	      MT_USB_DMA_CFG_TX_BULK_EN;
108 	if (dev->in_max_packet == 512)
109 		val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN;
110 	mt7601u_wr(dev, MT_USB_DMA_CFG, val);
111 
112 	val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
113 	mt7601u_wr(dev, MT_USB_DMA_CFG, val);
114 	val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
115 	mt7601u_wr(dev, MT_USB_DMA_CFG, val);
116 }
117 
118 static int mt7601u_init_bbp(struct mt7601u_dev *dev)
119 {
120 	int ret;
121 
122 	ret = mt7601u_wait_bbp_ready(dev);
123 	if (ret)
124 		return ret;
125 
126 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals,
127 				      ARRAY_SIZE(bbp_common_vals));
128 	if (ret)
129 		return ret;
130 
131 	return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals,
132 				       ARRAY_SIZE(bbp_chip_vals));
133 }
134 
135 static void
136 mt76_init_beacon_offsets(struct mt7601u_dev *dev)
137 {
138 	u16 base = MT_BEACON_BASE;
139 	u32 regs[4] = {};
140 	int i;
141 
142 	for (i = 0; i < 16; i++) {
143 		u16 addr = dev->beacon_offsets[i];
144 
145 		regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
146 	}
147 
148 	for (i = 0; i < 4; i++)
149 		mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]);
150 }
151 
152 static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev)
153 {
154 	int ret;
155 
156 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals,
157 				      ARRAY_SIZE(mac_common_vals));
158 	if (ret)
159 		return ret;
160 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN,
161 				      mac_chip_vals, ARRAY_SIZE(mac_chip_vals));
162 	if (ret)
163 		return ret;
164 
165 	mt76_init_beacon_offsets(dev);
166 
167 	mt7601u_wr(dev, MT_AUX_CLK_CFG, 0);
168 
169 	return 0;
170 }
171 
172 static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev)
173 {
174 	u32 *vals;
175 	int i, ret;
176 
177 	vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
178 	if (!vals)
179 		return -ENOMEM;
180 
181 	for (i = 0; i < N_WCIDS; i++)  {
182 		vals[i * 2] = 0xffffffff;
183 		vals[i * 2 + 1] = 0x00ffffff;
184 	}
185 
186 	ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE,
187 				       vals, N_WCIDS * 2);
188 	kfree(vals);
189 
190 	return ret;
191 }
192 
193 static int mt7601u_init_key_mem(struct mt7601u_dev *dev)
194 {
195 	u32 vals[4] = {};
196 
197 	return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
198 					vals, ARRAY_SIZE(vals));
199 }
200 
201 static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev)
202 {
203 	u32 *vals;
204 	int i, ret;
205 
206 	vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
207 	if (!vals)
208 		return -ENOMEM;
209 
210 	for (i = 0; i < N_WCIDS * 2; i++)
211 		vals[i] = 1;
212 
213 	ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE,
214 				       vals, N_WCIDS * 2);
215 	kfree(vals);
216 
217 	return ret;
218 }
219 
220 static void mt7601u_reset_counters(struct mt7601u_dev *dev)
221 {
222 	mt7601u_rr(dev, MT_RX_STA_CNT0);
223 	mt7601u_rr(dev, MT_RX_STA_CNT1);
224 	mt7601u_rr(dev, MT_RX_STA_CNT2);
225 	mt7601u_rr(dev, MT_TX_STA_CNT0);
226 	mt7601u_rr(dev, MT_TX_STA_CNT1);
227 	mt7601u_rr(dev, MT_TX_STA_CNT2);
228 }
229 
230 int mt7601u_mac_start(struct mt7601u_dev *dev)
231 {
232 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
233 
234 	if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
235 		       MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000))
236 		return -ETIMEDOUT;
237 
238 	dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR |
239 		MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC |
240 		MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP |
241 		MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND |
242 		MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS |
243 		MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL |
244 		MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV;
245 	mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
246 
247 	mt7601u_wr(dev, MT_MAC_SYS_CTRL,
248 		   MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
249 
250 	if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
251 		       MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50))
252 		return -ETIMEDOUT;
253 
254 	return 0;
255 }
256 
257 static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev)
258 {
259 	int i, ok;
260 
261 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
262 		return;
263 
264 	mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN |
265 		   MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN |
266 		   MT_BEACON_TIME_CFG_BEACON_TX);
267 
268 	if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000))
269 		dev_warn(dev->dev, "Warning: TX DMA did not stop!\n");
270 
271 	/* Page count on TxQ */
272 	i = 200;
273 	while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
274 		       (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
275 		       (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
276 		msleep(10);
277 
278 	if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
279 		dev_warn(dev->dev, "Warning: MAC TX did not stop!\n");
280 
281 	mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
282 					 MT_MAC_SYS_CTRL_ENABLE_TX);
283 
284 	/* Page count on RxQ */
285 	ok = 0;
286 	i = 200;
287 	while (i--) {
288 		if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
289 		    !mt76_rr(dev, 0x0a30) &&
290 		    !mt76_rr(dev, 0x0a34)) {
291 			if (ok++ > 5)
292 				break;
293 			continue;
294 		}
295 		msleep(1);
296 	}
297 
298 	if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
299 		dev_warn(dev->dev, "Warning: MAC RX did not stop!\n");
300 
301 	if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000))
302 		dev_warn(dev->dev, "Warning: RX DMA did not stop!\n");
303 }
304 
305 void mt7601u_mac_stop(struct mt7601u_dev *dev)
306 {
307 	mt7601u_mac_stop_hw(dev);
308 	flush_delayed_work(&dev->stat_work);
309 	cancel_delayed_work_sync(&dev->stat_work);
310 }
311 
312 static void mt7601u_stop_hardware(struct mt7601u_dev *dev)
313 {
314 	mt7601u_chip_onoff(dev, false, false);
315 }
316 
317 int mt7601u_init_hardware(struct mt7601u_dev *dev)
318 {
319 	static const u16 beacon_offsets[16] = {
320 		/* 512 byte per beacon */
321 		0xc000,	0xc200,	0xc400,	0xc600,
322 		0xc800,	0xca00,	0xcc00,	0xce00,
323 		0xd000,	0xd200,	0xd400,	0xd600,
324 		0xd800,	0xda00,	0xdc00,	0xde00
325 	};
326 	int ret;
327 
328 	dev->beacon_offsets = beacon_offsets;
329 
330 	mt7601u_chip_onoff(dev, true, false);
331 
332 	ret = mt7601u_wait_asic_ready(dev);
333 	if (ret)
334 		goto err;
335 	ret = mt7601u_mcu_init(dev);
336 	if (ret)
337 		goto err;
338 
339 	if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
340 			    MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
341 			    MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) {
342 		ret = -EIO;
343 		goto err;
344 	}
345 
346 	/* Wait for ASIC ready after FW load. */
347 	ret = mt7601u_wait_asic_ready(dev);
348 	if (ret)
349 		goto err;
350 
351 	mt7601u_reset_csr_bbp(dev);
352 	mt7601u_init_usb_dma(dev);
353 
354 	ret = mt7601u_mcu_cmd_init(dev);
355 	if (ret)
356 		goto err;
357 	ret = mt7601u_dma_init(dev);
358 	if (ret)
359 		goto err_mcu;
360 	ret = mt7601u_write_mac_initvals(dev);
361 	if (ret)
362 		goto err_rx;
363 
364 	if (!mt76_poll_msec(dev, MT_MAC_STATUS,
365 			    MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) {
366 		ret = -EIO;
367 		goto err_rx;
368 	}
369 
370 	ret = mt7601u_init_bbp(dev);
371 	if (ret)
372 		goto err_rx;
373 	ret = mt7601u_init_wcid_mem(dev);
374 	if (ret)
375 		goto err_rx;
376 	ret = mt7601u_init_key_mem(dev);
377 	if (ret)
378 		goto err_rx;
379 	ret = mt7601u_init_wcid_attr_mem(dev);
380 	if (ret)
381 		goto err_rx;
382 
383 	mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
384 					     MT_BEACON_TIME_CFG_SYNC_MODE |
385 					     MT_BEACON_TIME_CFG_TBTT_EN |
386 					     MT_BEACON_TIME_CFG_BEACON_TX));
387 
388 	mt7601u_reset_counters(dev);
389 
390 	mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
391 
392 	mt7601u_wr(dev, MT_TXOP_CTRL_CFG,
393 		   FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) |
394 		   FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));
395 
396 	ret = mt7601u_eeprom_init(dev);
397 	if (ret)
398 		goto err_rx;
399 
400 	ret = mt7601u_phy_init(dev);
401 	if (ret)
402 		goto err_rx;
403 
404 	mt7601u_set_rx_path(dev, 0);
405 	mt7601u_set_tx_dac(dev, 0);
406 
407 	mt7601u_mac_set_ctrlch(dev, false);
408 	mt7601u_bbp_set_ctrlch(dev, false);
409 	mt7601u_bbp_set_bw(dev, MT_BW_20);
410 
411 	return 0;
412 
413 err_rx:
414 	mt7601u_dma_cleanup(dev);
415 err_mcu:
416 	mt7601u_mcu_cmd_deinit(dev);
417 err:
418 	mt7601u_chip_onoff(dev, false, false);
419 	return ret;
420 }
421 
422 void mt7601u_cleanup(struct mt7601u_dev *dev)
423 {
424 	if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state))
425 		return;
426 
427 	mt7601u_stop_hardware(dev);
428 	mt7601u_dma_cleanup(dev);
429 	mt7601u_mcu_cmd_deinit(dev);
430 }
431 
432 struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev)
433 {
434 	struct ieee80211_hw *hw;
435 	struct mt7601u_dev *dev;
436 
437 	hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops);
438 	if (!hw)
439 		return NULL;
440 
441 	dev = hw->priv;
442 	dev->dev = pdev;
443 	dev->hw = hw;
444 	mutex_init(&dev->vendor_req_mutex);
445 	mutex_init(&dev->reg_atomic_mutex);
446 	mutex_init(&dev->hw_atomic_mutex);
447 	mutex_init(&dev->mutex);
448 	spin_lock_init(&dev->tx_lock);
449 	spin_lock_init(&dev->rx_lock);
450 	spin_lock_init(&dev->lock);
451 	spin_lock_init(&dev->mac_lock);
452 	spin_lock_init(&dev->con_mon_lock);
453 	atomic_set(&dev->avg_ampdu_len, 1);
454 	skb_queue_head_init(&dev->tx_skb_done);
455 
456 	dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0);
457 	if (!dev->stat_wq) {
458 		ieee80211_free_hw(hw);
459 		return NULL;
460 	}
461 
462 	return dev;
463 }
464 
465 #define CHAN2G(_idx, _freq) {			\
466 	.band = NL80211_BAND_2GHZ,		\
467 	.center_freq = (_freq),			\
468 	.hw_value = (_idx),			\
469 	.max_power = 30,			\
470 }
471 
472 static const struct ieee80211_channel mt76_channels_2ghz[] = {
473 	CHAN2G(1, 2412),
474 	CHAN2G(2, 2417),
475 	CHAN2G(3, 2422),
476 	CHAN2G(4, 2427),
477 	CHAN2G(5, 2432),
478 	CHAN2G(6, 2437),
479 	CHAN2G(7, 2442),
480 	CHAN2G(8, 2447),
481 	CHAN2G(9, 2452),
482 	CHAN2G(10, 2457),
483 	CHAN2G(11, 2462),
484 	CHAN2G(12, 2467),
485 	CHAN2G(13, 2472),
486 	CHAN2G(14, 2484),
487 };
488 
489 #define CCK_RATE(_idx, _rate) {					\
490 	.bitrate = _rate,					\
491 	.flags = IEEE80211_RATE_SHORT_PREAMBLE,			\
492 	.hw_value = (MT_PHY_TYPE_CCK << 8) | _idx,		\
493 	.hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx),	\
494 }
495 
496 #define OFDM_RATE(_idx, _rate) {				\
497 	.bitrate = _rate,					\
498 	.hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx,		\
499 	.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx,	\
500 }
501 
502 static struct ieee80211_rate mt76_rates[] = {
503 	CCK_RATE(0, 10),
504 	CCK_RATE(1, 20),
505 	CCK_RATE(2, 55),
506 	CCK_RATE(3, 110),
507 	OFDM_RATE(0, 60),
508 	OFDM_RATE(1, 90),
509 	OFDM_RATE(2, 120),
510 	OFDM_RATE(3, 180),
511 	OFDM_RATE(4, 240),
512 	OFDM_RATE(5, 360),
513 	OFDM_RATE(6, 480),
514 	OFDM_RATE(7, 540),
515 };
516 
517 static int
518 mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband,
519 		const struct ieee80211_channel *chan, int n_chan,
520 		struct ieee80211_rate *rates, int n_rates)
521 {
522 	struct ieee80211_sta_ht_cap *ht_cap;
523 	void *chanlist;
524 	int size;
525 
526 	size = n_chan * sizeof(*chan);
527 	chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL);
528 	if (!chanlist)
529 		return -ENOMEM;
530 
531 	sband->channels = chanlist;
532 	sband->n_channels = n_chan;
533 	sband->bitrates = rates;
534 	sband->n_bitrates = n_rates;
535 
536 	ht_cap = &sband->ht_cap;
537 	ht_cap->ht_supported = true;
538 	ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
539 		      IEEE80211_HT_CAP_GRN_FLD |
540 		      IEEE80211_HT_CAP_SGI_20 |
541 		      IEEE80211_HT_CAP_SGI_40 |
542 		      (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
543 
544 	ht_cap->mcs.rx_mask[0] = 0xff;
545 	ht_cap->mcs.rx_mask[4] = 0x1;
546 	ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
547 	ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
548 	ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
549 
550 	dev->chandef.chan = &sband->channels[0];
551 
552 	return 0;
553 }
554 
555 static int
556 mt76_init_sband_2g(struct mt7601u_dev *dev)
557 {
558 	dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g),
559 				     GFP_KERNEL);
560 	if (!dev->sband_2g)
561 		return -ENOMEM;
562 
563 	dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g;
564 
565 	WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >
566 		ARRAY_SIZE(mt76_channels_2ghz));
567 
568 	return mt76_init_sband(dev, dev->sband_2g,
569 			       &mt76_channels_2ghz[dev->ee->reg.start - 1],
570 			       dev->ee->reg.num,
571 			       mt76_rates, ARRAY_SIZE(mt76_rates));
572 }
573 
574 int mt7601u_register_device(struct mt7601u_dev *dev)
575 {
576 	struct ieee80211_hw *hw = dev->hw;
577 	struct wiphy *wiphy = hw->wiphy;
578 	int ret;
579 
580 	/* Reserve WCID 0 for mcast - thanks to this APs WCID will go to
581 	 * entry no. 1 like it does in the vendor driver.
582 	 */
583 	dev->wcid_mask[0] |= 1;
584 
585 	/* init fake wcid for monitor interfaces */
586 	dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid),
587 				     GFP_KERNEL);
588 	if (!dev->mon_wcid)
589 		return -ENOMEM;
590 	dev->mon_wcid->idx = 0xff;
591 	dev->mon_wcid->hw_key_idx = -1;
592 
593 	SET_IEEE80211_DEV(hw, dev->dev);
594 
595 	hw->queues = 4;
596 	ieee80211_hw_set(hw, SIGNAL_DBM);
597 	ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
598 	ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
599 	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
600 	ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
601 	ieee80211_hw_set(hw, MFP_CAPABLE);
602 	hw->max_rates = 1;
603 	hw->max_report_rates = 7;
604 	hw->max_rate_tries = 1;
605 
606 	hw->sta_data_size = sizeof(struct mt76_sta);
607 	hw->vif_data_size = sizeof(struct mt76_vif);
608 
609 	SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
610 
611 	wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
612 	wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
613 
614 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
615 
616 	ret = mt76_init_sband_2g(dev);
617 	if (ret)
618 		return ret;
619 
620 	INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work);
621 	INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat);
622 
623 	ret = ieee80211_register_hw(hw);
624 	if (ret)
625 		return ret;
626 
627 	mt7601u_init_debugfs(dev);
628 
629 	return 0;
630 }
631