1 /*
2  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include "mt76.h"
18 
19 static struct mt76_txwi_cache *
20 mt76_alloc_txwi(struct mt76_dev *dev)
21 {
22 	struct mt76_txwi_cache *t;
23 	dma_addr_t addr;
24 	int size;
25 
26 	size = (sizeof(*t) + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1);
27 	t = devm_kzalloc(dev->dev, size, GFP_ATOMIC);
28 	if (!t)
29 		return NULL;
30 
31 	addr = dma_map_single(dev->dev, &t->txwi, sizeof(t->txwi),
32 			      DMA_TO_DEVICE);
33 	t->dma_addr = addr;
34 
35 	return t;
36 }
37 
38 static struct mt76_txwi_cache *
39 __mt76_get_txwi(struct mt76_dev *dev)
40 {
41 	struct mt76_txwi_cache *t = NULL;
42 
43 	spin_lock_bh(&dev->lock);
44 	if (!list_empty(&dev->txwi_cache)) {
45 		t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
46 				     list);
47 		list_del(&t->list);
48 	}
49 	spin_unlock_bh(&dev->lock);
50 
51 	return t;
52 }
53 
54 struct mt76_txwi_cache *
55 mt76_get_txwi(struct mt76_dev *dev)
56 {
57 	struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
58 
59 	if (t)
60 		return t;
61 
62 	return mt76_alloc_txwi(dev);
63 }
64 
65 void
66 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
67 {
68 	if (!t)
69 		return;
70 
71 	spin_lock_bh(&dev->lock);
72 	list_add(&t->list, &dev->txwi_cache);
73 	spin_unlock_bh(&dev->lock);
74 }
75 
76 void mt76_tx_free(struct mt76_dev *dev)
77 {
78 	struct mt76_txwi_cache *t;
79 
80 	while ((t = __mt76_get_txwi(dev)) != NULL)
81 		dma_unmap_single(dev->dev, t->dma_addr, sizeof(t->txwi),
82 				 DMA_TO_DEVICE);
83 }
84 
85 static int
86 mt76_txq_get_qid(struct ieee80211_txq *txq)
87 {
88 	if (!txq->sta)
89 		return MT_TXQ_BE;
90 
91 	return txq->ac;
92 }
93 
94 void
95 mt76_tx(struct mt76_dev *dev, struct ieee80211_sta *sta,
96 	struct mt76_wcid *wcid, struct sk_buff *skb)
97 {
98 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
99 	struct mt76_queue *q;
100 	int qid = skb_get_queue_mapping(skb);
101 
102 	if (WARN_ON(qid >= MT_TXQ_PSD)) {
103 		qid = MT_TXQ_BE;
104 		skb_set_queue_mapping(skb, qid);
105 	}
106 
107 	if (!wcid->tx_rate_set)
108 		ieee80211_get_tx_rates(info->control.vif, sta, skb,
109 				       info->control.rates, 1);
110 
111 	q = &dev->q_tx[qid];
112 
113 	spin_lock_bh(&q->lock);
114 	dev->queue_ops->tx_queue_skb(dev, q, skb, wcid, sta);
115 	dev->queue_ops->kick(dev, q);
116 
117 	if (q->queued > q->ndesc - 8)
118 		ieee80211_stop_queue(dev->hw, skb_get_queue_mapping(skb));
119 	spin_unlock_bh(&q->lock);
120 }
121 EXPORT_SYMBOL_GPL(mt76_tx);
122 
123 static struct sk_buff *
124 mt76_txq_dequeue(struct mt76_dev *dev, struct mt76_txq *mtxq, bool ps)
125 {
126 	struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
127 	struct sk_buff *skb;
128 
129 	skb = skb_dequeue(&mtxq->retry_q);
130 	if (skb) {
131 		u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
132 
133 		if (ps && skb_queue_empty(&mtxq->retry_q))
134 			ieee80211_sta_set_buffered(txq->sta, tid, false);
135 
136 		return skb;
137 	}
138 
139 	skb = ieee80211_tx_dequeue(dev->hw, txq);
140 	if (!skb)
141 		return NULL;
142 
143 	return skb;
144 }
145 
146 static void
147 mt76_check_agg_ssn(struct mt76_txq *mtxq, struct sk_buff *skb)
148 {
149 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
150 
151 	if (!ieee80211_is_data_qos(hdr->frame_control))
152 		return;
153 
154 	mtxq->agg_ssn = le16_to_cpu(hdr->seq_ctrl) + 0x10;
155 }
156 
157 static void
158 mt76_queue_ps_skb(struct mt76_dev *dev, struct ieee80211_sta *sta,
159 		  struct sk_buff *skb, bool last)
160 {
161 	struct mt76_wcid *wcid = (struct mt76_wcid *) sta->drv_priv;
162 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
163 	struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD];
164 
165 	info->control.flags |= IEEE80211_TX_CTRL_PS_RESPONSE;
166 	if (last)
167 		info->flags |= IEEE80211_TX_STATUS_EOSP;
168 
169 	mt76_skb_set_moredata(skb, !last);
170 	dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, sta);
171 }
172 
173 void
174 mt76_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
175 			     u16 tids, int nframes,
176 			     enum ieee80211_frame_release_type reason,
177 			     bool more_data)
178 {
179 	struct mt76_dev *dev = hw->priv;
180 	struct sk_buff *last_skb = NULL;
181 	struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD];
182 	int i;
183 
184 	spin_lock_bh(&hwq->lock);
185 	for (i = 0; tids && nframes; i++, tids >>= 1) {
186 		struct ieee80211_txq *txq = sta->txq[i];
187 		struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
188 		struct sk_buff *skb;
189 
190 		if (!(tids & 1))
191 			continue;
192 
193 		do {
194 			skb = mt76_txq_dequeue(dev, mtxq, true);
195 			if (!skb)
196 				break;
197 
198 			if (mtxq->aggr)
199 				mt76_check_agg_ssn(mtxq, skb);
200 
201 			nframes--;
202 			if (last_skb)
203 				mt76_queue_ps_skb(dev, sta, last_skb, false);
204 
205 			last_skb = skb;
206 		} while (nframes);
207 	}
208 
209 	if (last_skb) {
210 		mt76_queue_ps_skb(dev, sta, last_skb, true);
211 		dev->queue_ops->kick(dev, hwq);
212 	}
213 	spin_unlock_bh(&hwq->lock);
214 }
215 EXPORT_SYMBOL_GPL(mt76_release_buffered_frames);
216 
217 static int
218 mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
219 		    struct mt76_txq *mtxq, bool *empty)
220 {
221 	struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
222 	struct ieee80211_tx_info *info;
223 	struct mt76_wcid *wcid = mtxq->wcid;
224 	struct sk_buff *skb;
225 	int n_frames = 1, limit;
226 	struct ieee80211_tx_rate tx_rate;
227 	bool ampdu;
228 	bool probe;
229 	int idx;
230 
231 	skb = mt76_txq_dequeue(dev, mtxq, false);
232 	if (!skb) {
233 		*empty = true;
234 		return 0;
235 	}
236 
237 	info = IEEE80211_SKB_CB(skb);
238 	if (!wcid->tx_rate_set)
239 		ieee80211_get_tx_rates(txq->vif, txq->sta, skb,
240 				       info->control.rates, 1);
241 	tx_rate = info->control.rates[0];
242 
243 	probe = (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
244 	ampdu = IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU;
245 	limit = ampdu ? 16 : 3;
246 
247 	if (ampdu)
248 		mt76_check_agg_ssn(mtxq, skb);
249 
250 	idx = dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid, txq->sta);
251 
252 	if (idx < 0)
253 		return idx;
254 
255 	do {
256 		bool cur_ampdu;
257 
258 		if (probe)
259 			break;
260 
261 		if (test_bit(MT76_OFFCHANNEL, &dev->state) ||
262 		    test_bit(MT76_RESET, &dev->state))
263 			return -EBUSY;
264 
265 		skb = mt76_txq_dequeue(dev, mtxq, false);
266 		if (!skb) {
267 			*empty = true;
268 			break;
269 		}
270 
271 		info = IEEE80211_SKB_CB(skb);
272 		cur_ampdu = info->flags & IEEE80211_TX_CTL_AMPDU;
273 
274 		if (ampdu != cur_ampdu ||
275 		    (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
276 			skb_queue_tail(&mtxq->retry_q, skb);
277 			break;
278 		}
279 
280 		info->control.rates[0] = tx_rate;
281 
282 		if (cur_ampdu)
283 			mt76_check_agg_ssn(mtxq, skb);
284 
285 		idx = dev->queue_ops->tx_queue_skb(dev, hwq, skb, wcid,
286 						   txq->sta);
287 		if (idx < 0)
288 			return idx;
289 
290 		n_frames++;
291 	} while (n_frames < limit);
292 
293 	if (!probe) {
294 		hwq->swq_queued++;
295 		hwq->entry[idx].schedule = true;
296 	}
297 
298 	dev->queue_ops->kick(dev, hwq);
299 
300 	return n_frames;
301 }
302 
303 static int
304 mt76_txq_schedule_list(struct mt76_dev *dev, struct mt76_queue *hwq)
305 {
306 	struct mt76_txq *mtxq, *mtxq_last;
307 	int len = 0;
308 
309 restart:
310 	mtxq_last = list_last_entry(&hwq->swq, struct mt76_txq, list);
311 	while (!list_empty(&hwq->swq)) {
312 		bool empty = false;
313 		int cur;
314 
315 		if (test_bit(MT76_OFFCHANNEL, &dev->state) ||
316 		    test_bit(MT76_RESET, &dev->state))
317 			return -EBUSY;
318 
319 		mtxq = list_first_entry(&hwq->swq, struct mt76_txq, list);
320 		if (mtxq->send_bar && mtxq->aggr) {
321 			struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
322 			struct ieee80211_sta *sta = txq->sta;
323 			struct ieee80211_vif *vif = txq->vif;
324 			u16 agg_ssn = mtxq->agg_ssn;
325 			u8 tid = txq->tid;
326 
327 			mtxq->send_bar = false;
328 			spin_unlock_bh(&hwq->lock);
329 			ieee80211_send_bar(vif, sta->addr, tid, agg_ssn);
330 			spin_lock_bh(&hwq->lock);
331 			goto restart;
332 		}
333 
334 		list_del_init(&mtxq->list);
335 
336 		cur = mt76_txq_send_burst(dev, hwq, mtxq, &empty);
337 		if (!empty)
338 			list_add_tail(&mtxq->list, &hwq->swq);
339 
340 		if (cur < 0)
341 			return cur;
342 
343 		len += cur;
344 
345 		if (mtxq == mtxq_last)
346 			break;
347 	}
348 
349 	return len;
350 }
351 
352 void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq)
353 {
354 	int len;
355 
356 	rcu_read_lock();
357 	do {
358 		if (hwq->swq_queued >= 4 || list_empty(&hwq->swq))
359 			break;
360 
361 		len = mt76_txq_schedule_list(dev, hwq);
362 	} while (len > 0);
363 	rcu_read_unlock();
364 }
365 EXPORT_SYMBOL_GPL(mt76_txq_schedule);
366 
367 void mt76_txq_schedule_all(struct mt76_dev *dev)
368 {
369 	int i;
370 
371 	for (i = 0; i <= MT_TXQ_BK; i++) {
372 		struct mt76_queue *q = &dev->q_tx[i];
373 
374 		spin_lock_bh(&q->lock);
375 		mt76_txq_schedule(dev, q);
376 		spin_unlock_bh(&q->lock);
377 	}
378 }
379 EXPORT_SYMBOL_GPL(mt76_txq_schedule_all);
380 
381 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta,
382 			 bool send_bar)
383 {
384 	int i;
385 
386 	for (i = 0; i < ARRAY_SIZE(sta->txq); i++) {
387 		struct ieee80211_txq *txq = sta->txq[i];
388 		struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
389 
390 		spin_lock_bh(&mtxq->hwq->lock);
391 		mtxq->send_bar = mtxq->aggr && send_bar;
392 		if (!list_empty(&mtxq->list))
393 			list_del_init(&mtxq->list);
394 		spin_unlock_bh(&mtxq->hwq->lock);
395 	}
396 }
397 EXPORT_SYMBOL_GPL(mt76_stop_tx_queues);
398 
399 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq)
400 {
401 	struct mt76_dev *dev = hw->priv;
402 	struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
403 	struct mt76_queue *hwq = mtxq->hwq;
404 
405 	spin_lock_bh(&hwq->lock);
406 	if (list_empty(&mtxq->list))
407 		list_add_tail(&mtxq->list, &hwq->swq);
408 	mt76_txq_schedule(dev, hwq);
409 	spin_unlock_bh(&hwq->lock);
410 }
411 EXPORT_SYMBOL_GPL(mt76_wake_tx_queue);
412 
413 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq)
414 {
415 	struct mt76_txq *mtxq;
416 	struct mt76_queue *hwq;
417 	struct sk_buff *skb;
418 
419 	if (!txq)
420 		return;
421 
422 	mtxq = (struct mt76_txq *) txq->drv_priv;
423 	hwq = mtxq->hwq;
424 
425 	spin_lock_bh(&hwq->lock);
426 	if (!list_empty(&mtxq->list))
427 		list_del(&mtxq->list);
428 	spin_unlock_bh(&hwq->lock);
429 
430 	while ((skb = skb_dequeue(&mtxq->retry_q)) != NULL)
431 		ieee80211_free_txskb(dev->hw, skb);
432 }
433 EXPORT_SYMBOL_GPL(mt76_txq_remove);
434 
435 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq)
436 {
437 	struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
438 
439 	INIT_LIST_HEAD(&mtxq->list);
440 	skb_queue_head_init(&mtxq->retry_q);
441 
442 	mtxq->hwq = &dev->q_tx[mt76_txq_get_qid(txq)];
443 }
444 EXPORT_SYMBOL_GPL(mt76_txq_init);
445