1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (C) 2022 MediaTek Inc.
4  */
5 
6 #ifndef __MT7996_REGS_H
7 #define __MT7996_REGS_H
8 
9 struct __map {
10 	u32 phys;
11 	u32 mapped;
12 	u32 size;
13 };
14 
15 struct __base {
16 	u32 band_base[__MT_MAX_BAND];
17 };
18 
19 /* used to differentiate between generations */
20 struct mt7996_reg_desc {
21 	const struct __base *base;
22 	const struct __map *map;
23 	u32 map_size;
24 };
25 
26 enum base_rev {
27 	WF_AGG_BASE,
28 	WF_ARB_BASE,
29 	WF_TMAC_BASE,
30 	WF_RMAC_BASE,
31 	WF_DMA_BASE,
32 	WF_WTBLOFF_BASE,
33 	WF_ETBF_BASE,
34 	WF_LPON_BASE,
35 	WF_MIB_BASE,
36 	WF_RATE_BASE,
37 	__MT_REG_BASE_MAX,
38 };
39 
40 #define __BASE(_id, _band)			(dev->reg.base[(_id)].band_base[(_band)])
41 
42 #define MT_MCU_INT_EVENT			0x2108
43 #define MT_MCU_INT_EVENT_DMA_STOPPED		BIT(0)
44 #define MT_MCU_INT_EVENT_DMA_INIT		BIT(1)
45 #define MT_MCU_INT_EVENT_RESET_DONE		BIT(3)
46 
47 /* PLE */
48 #define MT_PLE_BASE				0x820c0000
49 #define MT_PLE(ofs)				(MT_PLE_BASE + (ofs))
50 
51 #define MT_FL_Q_EMPTY				MT_PLE(0x360)
52 #define MT_FL_Q0_CTRL				MT_PLE(0x3e0)
53 #define MT_FL_Q2_CTRL				MT_PLE(0x3e8)
54 #define MT_FL_Q3_CTRL				MT_PLE(0x3ec)
55 
56 #define MT_PLE_FREEPG_CNT			MT_PLE(0x380)
57 #define MT_PLE_FREEPG_HEAD_TAIL			MT_PLE(0x384)
58 #define MT_PLE_PG_HIF_GROUP			MT_PLE(0x00c)
59 #define MT_PLE_HIF_PG_INFO			MT_PLE(0x388)
60 
61 #define MT_PLE_AC_QEMPTY(ac, n)			MT_PLE(0x600 +	0x80 * (ac) + ((n) << 2))
62 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n)		MT_PLE(0x10e0 + ((n) << 2))
63 
64 /* WF MDP TOP */
65 #define MT_MDP_BASE				0x820cc000
66 #define MT_MDP(ofs)				(MT_MDP_BASE + (ofs))
67 
68 #define MT_MDP_DCR2				MT_MDP(0x8e8)
69 #define MT_MDP_DCR2_RX_TRANS_SHORT		BIT(2)
70 
71 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */
72 #define MT_WF_TMAC_BASE(_band)			__BASE(WF_TMAC_BASE, (_band))
73 #define MT_WF_TMAC(_band, ofs)			(MT_WF_TMAC_BASE(_band) + (ofs))
74 
75 #define MT_TMAC_TCR0(_band)			MT_WF_TMAC(_band, 0)
76 #define MT_TMAC_TCR0_TX_BLINK			GENMASK(7, 6)
77 
78 #define MT_TMAC_CDTR(_band)			MT_WF_TMAC(_band, 0x0c8)
79 #define MT_TMAC_ODTR(_band)			MT_WF_TMAC(_band, 0x0cc)
80 #define MT_TIMEOUT_VAL_PLCP			GENMASK(15, 0)
81 #define MT_TIMEOUT_VAL_CCA			GENMASK(31, 16)
82 
83 #define MT_TMAC_ICR0(_band)			MT_WF_TMAC(_band, 0x014)
84 #define MT_IFS_EIFS_OFDM			GENMASK(8, 0)
85 #define MT_IFS_RIFS				GENMASK(14, 10)
86 #define MT_IFS_SIFS				GENMASK(22, 16)
87 #define MT_IFS_SLOT				GENMASK(30, 24)
88 
89 #define MT_TMAC_ICR1(_band)			MT_WF_TMAC(_band, 0x018)
90 #define MT_IFS_EIFS_CCK				GENMASK(8, 0)
91 
92 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */
93 #define MT_WF_DMA_BASE(_band)			__BASE(WF_DMA_BASE, (_band))
94 #define MT_WF_DMA(_band, ofs)			(MT_WF_DMA_BASE(_band) + (ofs))
95 
96 #define MT_DMA_DCR0(_band)			MT_WF_DMA(_band, 0x000)
97 #define MT_DMA_DCR0_RXD_G5_EN			BIT(23)
98 
99 #define MT_DMA_TCRF1(_band)			MT_WF_DMA(_band, 0x054)
100 #define MT_DMA_TCRF1_QIDX			GENMASK(15, 13)
101 
102 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */
103 #define MT_WTBLOFF_BASE(_band)			__BASE(WF_WTBLOFF_BASE, (_band))
104 #define MT_WTBLOFF(_band, ofs)			(MT_WTBLOFF_BASE(_band) + (ofs))
105 
106 #define MT_WTBLOFF_RSCR(_band)			MT_WTBLOFF(_band, 0x008)
107 #define MT_WTBLOFF_RSCR_RCPI_MODE		GENMASK(31, 30)
108 #define MT_WTBLOFF_RSCR_RCPI_PARAM		GENMASK(25, 24)
109 
110 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */
111 #define MT_WF_ETBF_BASE(_band)			__BASE(WF_ETBF_BASE, (_band))
112 #define MT_WF_ETBF(_band, ofs)			(MT_WF_ETBF_BASE(_band) + (ofs))
113 
114 #define MT_ETBF_RX_FB_CONT(_band)		MT_WF_ETBF(_band, 0x100)
115 #define MT_ETBF_RX_FB_BW			GENMASK(10, 8)
116 #define MT_ETBF_RX_FB_NC			GENMASK(7, 4)
117 #define MT_ETBF_RX_FB_NR			GENMASK(3, 0)
118 
119 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */
120 #define MT_WF_LPON_BASE(_band)			__BASE(WF_LPON_BASE, (_band))
121 #define MT_WF_LPON(_band, ofs)			(MT_WF_LPON_BASE(_band) + (ofs))
122 
123 #define MT_LPON_UTTR0(_band)			MT_WF_LPON(_band, 0x360)
124 #define MT_LPON_UTTR1(_band)			MT_WF_LPON(_band, 0x364)
125 #define MT_LPON_FRCR(_band)			MT_WF_LPON(_band, 0x37c)
126 
127 #define MT_LPON_TCR(_band, n)			MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4))
128 #define MT_LPON_TCR_SW_MODE			GENMASK(1, 0)
129 #define MT_LPON_TCR_SW_WRITE			BIT(0)
130 #define MT_LPON_TCR_SW_ADJUST			BIT(1)
131 #define MT_LPON_TCR_SW_READ			GENMASK(1, 0)
132 
133 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/
134 /* These counters are (mostly?) clear-on-read.  So, some should not
135  * be read at all in case firmware is already reading them.  These
136  * are commented with 'DNR' below. The DNR stats will be read by querying
137  * the firmware API for the appropriate message.  For counters the driver
138  * does read, the driver should accumulate the counters.
139  */
140 #define MT_WF_MIB_BASE(_band)			__BASE(WF_MIB_BASE, (_band))
141 #define MT_WF_MIB(_band, ofs)			(MT_WF_MIB_BASE(_band) + (ofs))
142 
143 #define MT_MIB_BSCR0(_band)			MT_WF_MIB(_band, 0x9cc)
144 #define MT_MIB_BSCR1(_band)			MT_WF_MIB(_band, 0x9d0)
145 #define MT_MIB_BSCR2(_band)			MT_WF_MIB(_band, 0x9d4)
146 #define MT_MIB_BSCR3(_band)			MT_WF_MIB(_band, 0x9d8)
147 #define MT_MIB_BSCR4(_band)			MT_WF_MIB(_band, 0x9dc)
148 #define MT_MIB_BSCR5(_band)			MT_WF_MIB(_band, 0x9e0)
149 #define MT_MIB_BSCR6(_band)			MT_WF_MIB(_band, 0x9e4)
150 #define MT_MIB_BSCR7(_band)			MT_WF_MIB(_band, 0x9e8)
151 #define MT_MIB_BSCR17(_band)			MT_WF_MIB(_band, 0xa10)
152 
153 #define MT_MIB_TSCR5(_band)			MT_WF_MIB(_band, 0x6c4)
154 #define MT_MIB_TSCR6(_band)			MT_WF_MIB(_band, 0x6c8)
155 #define MT_MIB_TSCR7(_band)			MT_WF_MIB(_band, 0x6d0)
156 
157 #define MT_MIB_RSCR1(_band)			MT_WF_MIB(_band, 0x7ac)
158 /* rx mpdu counter, full 32 bits */
159 #define MT_MIB_RSCR31(_band)			MT_WF_MIB(_band, 0x964)
160 #define MT_MIB_RSCR33(_band)			MT_WF_MIB(_band, 0x96c)
161 
162 #define MT_MIB_SDR6(_band)			MT_WF_MIB(_band, 0x020)
163 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK	GENMASK(15, 0)
164 
165 #define MT_MIB_RVSR0(_band)			MT_WF_MIB(_band, 0x720)
166 
167 #define MT_MIB_RSCR35(_band)			MT_WF_MIB(_band, 0x974)
168 #define MT_MIB_RSCR36(_band)			MT_WF_MIB(_band, 0x978)
169 
170 /* tx ampdu cnt, full 32 bits */
171 #define MT_MIB_TSCR0(_band)			MT_WF_MIB(_band, 0x6b0)
172 #define MT_MIB_TSCR2(_band)			MT_WF_MIB(_band, 0x6b8)
173 
174 /* counts all mpdus in ampdu, regardless of success */
175 #define MT_MIB_TSCR3(_band)			MT_WF_MIB(_band, 0x6bc)
176 
177 /* counts all successfully tx'd mpdus in ampdu */
178 #define MT_MIB_TSCR4(_band)			MT_WF_MIB(_band, 0x6c0)
179 
180 /* rx ampdu count, 32-bit */
181 #define MT_MIB_RSCR27(_band)			MT_WF_MIB(_band, 0x954)
182 
183 /* rx ampdu bytes count, 32-bit */
184 #define MT_MIB_RSCR28(_band)			MT_WF_MIB(_band, 0x958)
185 
186 /* rx ampdu valid subframe count */
187 #define MT_MIB_RSCR29(_band)			MT_WF_MIB(_band, 0x95c)
188 
189 /* rx ampdu valid subframe bytes count, 32bits */
190 #define MT_MIB_RSCR30(_band)			MT_WF_MIB(_band, 0x960)
191 
192 /* remaining windows protected stats */
193 #define MT_MIB_SDR27(_band)			MT_WF_MIB(_band, 0x080)
194 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT		GENMASK(15, 0)
195 
196 #define MT_MIB_SDR28(_band)			MT_WF_MIB(_band, 0x084)
197 #define MT_MIB_SDR28_TX_RWP_NEED_CNT		GENMASK(15, 0)
198 
199 #define MT_MIB_RVSR1(_band)			MT_WF_MIB(_band, 0x724)
200 
201 /* rx blockack count, 32 bits */
202 #define MT_MIB_TSCR1(_band)			MT_WF_MIB(_band, 0x6b4)
203 
204 #define MT_MIB_BTSCR0(_band)			MT_WF_MIB(_band, 0x5e0)
205 #define MT_MIB_BTSCR5(_band)			MT_WF_MIB(_band, 0x788)
206 #define MT_MIB_BTSCR6(_band)			MT_WF_MIB(_band, 0x798)
207 
208 #define MT_MIB_BFTFCR(_band)			MT_WF_MIB(_band, 0x5d0)
209 
210 #define MT_TX_AGG_CNT(_band, n)			MT_WF_MIB(_band, 0xa28 + ((n) << 2))
211 #define MT_MIB_ARNG(_band, n)			MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
212 #define MT_MIB_ARNCR_RANGE(val, n)		(((val) >> ((n) << 4)) & GENMASK(9, 0))
213 
214 /* UMIB */
215 #define MT_WF_UMIB_BASE				0x820cd000
216 #define MT_WF_UMIB(ofs)				(MT_WF_UMIB_BASE + (ofs))
217 
218 #define MT_UMIB_RPDCR(_band)			(MT_WF_UMIB(0x594) + (_band) * 0x164)
219 
220 /* WTBLON TOP */
221 #define MT_WTBLON_TOP_BASE			0x820d4000
222 #define MT_WTBLON_TOP(ofs)			(MT_WTBLON_TOP_BASE + (ofs))
223 #define MT_WTBLON_TOP_WDUCR			MT_WTBLON_TOP(0x370)
224 #define MT_WTBLON_TOP_WDUCR_GROUP		GENMASK(4, 0)
225 
226 #define MT_WTBL_UPDATE				MT_WTBLON_TOP(0x380)
227 #define MT_WTBL_UPDATE_WLAN_IDX			GENMASK(11, 0)
228 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR		BIT(14)
229 #define MT_WTBL_UPDATE_BUSY			BIT(31)
230 
231 #define MT_WTBL_ITCR				MT_WTBLON_TOP(0x3b0)
232 #define MT_WTBL_ITCR_WR				BIT(16)
233 #define MT_WTBL_ITCR_EXEC			BIT(31)
234 #define MT_WTBL_ITDR0				MT_WTBLON_TOP(0x3b8)
235 #define MT_WTBL_ITDR1				MT_WTBLON_TOP(0x3bc)
236 #define MT_WTBL_SPE_IDX_SEL			BIT(6)
237 
238 /* WTBL */
239 #define MT_WTBL_BASE				0x820d8000
240 #define MT_WTBL_LMAC_ID				GENMASK(14, 8)
241 #define MT_WTBL_LMAC_DW				GENMASK(7, 2)
242 #define MT_WTBL_LMAC_OFFS(_id, _dw)		(MT_WTBL_BASE | \
243 						 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
244 						 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
245 
246 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */
247 #define MT_WF_ARB_BASE(_band)			__BASE(WF_ARB_BASE, (_band))
248 #define MT_WF_ARB(_band, ofs)			(MT_WF_ARB_BASE(_band) + (ofs))
249 
250 #define MT_ARB_SCR(_band)			MT_WF_ARB(_band, 0x000)
251 #define MT_ARB_SCR_TX_DISABLE			BIT(8)
252 #define MT_ARB_SCR_RX_DISABLE			BIT(9)
253 
254 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */
255 #define MT_WF_RMAC_BASE(_band)			__BASE(WF_RMAC_BASE, (_band))
256 #define MT_WF_RMAC(_band, ofs)			(MT_WF_RMAC_BASE(_band) + (ofs))
257 
258 #define MT_WF_RFCR(_band)			MT_WF_RMAC(_band, 0x000)
259 #define MT_WF_RFCR_DROP_STBC_MULTI		BIT(0)
260 #define MT_WF_RFCR_DROP_FCSFAIL			BIT(1)
261 #define MT_WF_RFCR_DROP_PROBEREQ		BIT(4)
262 #define MT_WF_RFCR_DROP_MCAST			BIT(5)
263 #define MT_WF_RFCR_DROP_BCAST			BIT(6)
264 #define MT_WF_RFCR_DROP_MCAST_FILTERED		BIT(7)
265 #define MT_WF_RFCR_DROP_A3_MAC			BIT(8)
266 #define MT_WF_RFCR_DROP_A3_BSSID		BIT(9)
267 #define MT_WF_RFCR_DROP_A2_BSSID		BIT(10)
268 #define MT_WF_RFCR_DROP_OTHER_BEACON		BIT(11)
269 #define MT_WF_RFCR_DROP_FRAME_REPORT		BIT(12)
270 #define MT_WF_RFCR_DROP_CTL_RSV			BIT(13)
271 #define MT_WF_RFCR_DROP_CTS			BIT(14)
272 #define MT_WF_RFCR_DROP_RTS			BIT(15)
273 #define MT_WF_RFCR_DROP_DUPLICATE		BIT(16)
274 #define MT_WF_RFCR_DROP_OTHER_BSS		BIT(17)
275 #define MT_WF_RFCR_DROP_OTHER_UC		BIT(18)
276 #define MT_WF_RFCR_DROP_OTHER_TIM		BIT(19)
277 #define MT_WF_RFCR_DROP_NDPA			BIT(20)
278 #define MT_WF_RFCR_DROP_UNWANTED_CTL		BIT(21)
279 
280 #define MT_WF_RFCR1(_band)			MT_WF_RMAC(_band, 0x004)
281 #define MT_WF_RFCR1_DROP_ACK			BIT(4)
282 #define MT_WF_RFCR1_DROP_BF_POLL		BIT(5)
283 #define MT_WF_RFCR1_DROP_BA			BIT(6)
284 #define MT_WF_RFCR1_DROP_CFEND			BIT(7)
285 #define MT_WF_RFCR1_DROP_CFACK			BIT(8)
286 
287 #define MT_WF_RMAC_MIB_AIRTIME0(_band)		MT_WF_RMAC(_band, 0x0380)
288 #define MT_WF_RMAC_MIB_RXTIME_CLR		BIT(31)
289 #define MT_WF_RMAC_MIB_ED_OFFSET		GENMASK(20, 16)
290 #define MT_WF_RMAC_MIB_OBSS_BACKOFF		GENMASK(15, 0)
291 
292 #define MT_WF_RMAC_MIB_AIRTIME1(_band)		MT_WF_RMAC(_band, 0x0384)
293 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF		GENMASK(31, 16)
294 
295 #define MT_WF_RMAC_MIB_AIRTIME3(_band)		MT_WF_RMAC(_band, 0x038c)
296 #define MT_WF_RMAC_MIB_QOS01_BACKOFF		GENMASK(31, 0)
297 
298 #define MT_WF_RMAC_MIB_AIRTIME4(_band)		MT_WF_RMAC(_band, 0x0390)
299 #define MT_WF_RMAC_MIB_QOS23_BACKOFF		GENMASK(31, 0)
300 
301 #define MT_WF_RMAC_RSVD0(_band)			MT_WF_RMAC(_band, 0x03e0)
302 #define MT_WF_RMAC_RSVD0_EIFS_CLR		BIT(21)
303 
304 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */
305 #define MT_WF_RATE_BASE(_band)			__BASE(WF_RATE_BASE, (_band))
306 #define MT_WF_RATE(_band, ofs)			(MT_WF_RATE_BASE(_band) + (ofs))
307 
308 #define MT_RATE_HRCR0(_band)			MT_WF_RATE(_band, 0x050)
309 #define MT_RATE_HRCR0_CFEND_RATE		GENMASK(14, 0)
310 
311 /* WFDMA0 */
312 #define MT_WFDMA0_BASE				0xd4000
313 #define MT_WFDMA0(ofs)				(MT_WFDMA0_BASE + (ofs))
314 
315 #define MT_WFDMA0_RST				MT_WFDMA0(0x100)
316 #define MT_WFDMA0_RST_LOGIC_RST			BIT(4)
317 #define MT_WFDMA0_RST_DMASHDL_ALL_RST		BIT(5)
318 
319 #define MT_WFDMA0_BUSY_ENA			MT_WFDMA0(0x13c)
320 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0		BIT(0)
321 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1		BIT(1)
322 #define MT_WFDMA0_BUSY_ENA_RX_FIFO		BIT(2)
323 
324 #define MT_WFDMA0_RX_INT_PCIE_SEL		MT_WFDMA0(0x154)
325 #define MT_WFDMA0_RX_INT_SEL_RING3		BIT(3)
326 
327 #define MT_WFDMA0_MCU_HOST_INT_ENA		MT_WFDMA0(0x1f4)
328 
329 #define MT_WFDMA0_GLO_CFG			MT_WFDMA0(0x208)
330 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN		BIT(0)
331 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN		BIT(2)
332 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO		BIT(28)
333 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO		BIT(27)
334 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2	BIT(21)
335 
336 #define WF_WFDMA0_GLO_CFG_EXT0			MT_WFDMA0(0x2b0)
337 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD	BIT(18)
338 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE	BIT(14)
339 
340 #define WF_WFDMA0_GLO_CFG_EXT1			MT_WFDMA0(0x2b4)
341 #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE	BIT(31)
342 #define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE	BIT(28)
343 
344 #define MT_WFDMA0_RST_DTX_PTR			MT_WFDMA0(0x20c)
345 #define MT_WFDMA0_PRI_DLY_INT_CFG0		MT_WFDMA0(0x2f0)
346 #define MT_WFDMA0_PRI_DLY_INT_CFG1		MT_WFDMA0(0x2f4)
347 #define MT_WFDMA0_PRI_DLY_INT_CFG2		MT_WFDMA0(0x2f8)
348 
349 /* WFDMA1 */
350 #define MT_WFDMA1_BASE				0xd5000
351 
352 /* WFDMA CSR */
353 #define MT_WFDMA_EXT_CSR_BASE			0xd7000
354 #define MT_WFDMA_EXT_CSR(ofs)			(MT_WFDMA_EXT_CSR_BASE + (ofs))
355 
356 #define MT_WFDMA_HOST_CONFIG			MT_WFDMA_EXT_CSR(0x30)
357 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND		BIT(0)
358 
359 #define MT_WFDMA_EXT_CSR_HIF_MISC		MT_WFDMA_EXT_CSR(0x44)
360 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY		BIT(0)
361 
362 #define MT_PCIE_RECOG_ID			0xd7090
363 #define MT_PCIE_RECOG_ID_MASK			GENMASK(30, 0)
364 #define MT_PCIE_RECOG_ID_SEM			BIT(31)
365 
366 /* WFDMA0 PCIE1 */
367 #define MT_WFDMA0_PCIE1_BASE			0xd8000
368 #define MT_WFDMA0_PCIE1(ofs)			(MT_WFDMA0_PCIE1_BASE + (ofs))
369 
370 #define MT_WFDMA0_PCIE1_BUSY_ENA		MT_WFDMA0_PCIE1(0x13c)
371 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0	BIT(0)
372 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1	BIT(1)
373 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO	BIT(2)
374 
375 /* WFDMA COMMON */
376 #define __RXQ(q)				((q) + __MT_MCUQ_MAX)
377 #define __TXQ(q)				(__RXQ(q) + __MT_RXQ_MAX)
378 
379 #define MT_Q_ID(q)				(dev->q_id[(q)])
380 #define MT_Q_BASE(q)				((dev->q_wfdma_mask >> (q)) & 0x1 ?	\
381 						 MT_WFDMA1_BASE : MT_WFDMA0_BASE)
382 
383 #define MT_MCUQ_ID(q)				MT_Q_ID(q)
384 #define MT_TXQ_ID(q)				MT_Q_ID(__TXQ(q))
385 #define MT_RXQ_ID(q)				MT_Q_ID(__RXQ(q))
386 
387 #define MT_MCUQ_RING_BASE(q)			(MT_Q_BASE(q) + 0x300)
388 #define MT_TXQ_RING_BASE(q)			(MT_Q_BASE(__TXQ(q)) + 0x300)
389 #define MT_RXQ_RING_BASE(q)			(MT_Q_BASE(__RXQ(q)) + 0x500)
390 
391 #define MT_MCUQ_EXT_CTRL(q)			(MT_Q_BASE(q) +	0x600 +	\
392 						 MT_MCUQ_ID(q) * 0x4)
393 #define MT_RXQ_BAND1_CTRL(q)			(MT_Q_BASE(__RXQ(q)) + 0x680 +	\
394 						 MT_RXQ_ID(q) * 0x4)
395 #define MT_TXQ_EXT_CTRL(q)			(MT_Q_BASE(__TXQ(q)) + 0x600 +	\
396 						 MT_TXQ_ID(q) * 0x4)
397 
398 #define MT_INT_SOURCE_CSR			MT_WFDMA0(0x200)
399 #define MT_INT_MASK_CSR				MT_WFDMA0(0x204)
400 
401 #define MT_INT1_SOURCE_CSR			MT_WFDMA0_PCIE1(0x200)
402 #define MT_INT1_MASK_CSR			MT_WFDMA0_PCIE1(0x204)
403 
404 #define MT_INT_RX_DONE_BAND0			BIT(12)
405 #define MT_INT_RX_DONE_BAND1			BIT(12)
406 #define MT_INT_RX_DONE_BAND2			BIT(13)
407 #define MT_INT_RX_DONE_WM			BIT(0)
408 #define MT_INT_RX_DONE_WA			BIT(1)
409 #define MT_INT_RX_DONE_WA_MAIN			BIT(2)
410 #define MT_INT_RX_DONE_WA_EXT			BIT(2)
411 #define MT_INT_RX_DONE_WA_TRI			BIT(3)
412 #define MT_INT_RX_TXFREE_MAIN			BIT(17)
413 #define MT_INT_RX_TXFREE_TRI			BIT(15)
414 #define MT_INT_MCU_CMD				BIT(29)
415 
416 #define MT_INT_RX(q)				(dev->q_int_mask[__RXQ(q)])
417 #define MT_INT_TX_MCU(q)			(dev->q_int_mask[(q)])
418 
419 #define MT_INT_RX_DONE_MCU			(MT_INT_RX(MT_RXQ_MCU) |	\
420 						 MT_INT_RX(MT_RXQ_MCU_WA))
421 
422 #define MT_INT_BAND0_RX_DONE			(MT_INT_RX(MT_RXQ_MAIN) |	\
423 						 MT_INT_RX(MT_RXQ_MAIN_WA))
424 
425 #define MT_INT_BAND1_RX_DONE			(MT_INT_RX(MT_RXQ_BAND1) |	\
426 						 MT_INT_RX(MT_RXQ_BAND1_WA) |	\
427 						 MT_INT_RX(MT_RXQ_MAIN_WA))
428 
429 #define MT_INT_BAND2_RX_DONE			(MT_INT_RX(MT_RXQ_BAND2) |	\
430 						 MT_INT_RX(MT_RXQ_BAND2_WA) |	\
431 						 MT_INT_RX(MT_RXQ_MAIN_WA))
432 
433 #define MT_INT_RX_DONE_ALL			(MT_INT_RX_DONE_MCU |		\
434 						 MT_INT_BAND0_RX_DONE |		\
435 						 MT_INT_BAND1_RX_DONE |		\
436 						 MT_INT_BAND2_RX_DONE)
437 
438 #define MT_INT_TX_DONE_FWDL			BIT(26)
439 #define MT_INT_TX_DONE_MCU_WM			BIT(27)
440 #define MT_INT_TX_DONE_MCU_WA			BIT(22)
441 #define MT_INT_TX_DONE_BAND0			BIT(30)
442 #define MT_INT_TX_DONE_BAND1			BIT(31)
443 #define MT_INT_TX_DONE_BAND2			BIT(15)
444 
445 #define MT_INT_TX_DONE_MCU			(MT_INT_TX_MCU(MT_MCUQ_WA) |	\
446 						 MT_INT_TX_MCU(MT_MCUQ_WM) |	\
447 						 MT_INT_TX_MCU(MT_MCUQ_FWDL))
448 
449 #define MT_MCU_CMD				MT_WFDMA0(0x1f0)
450 #define MT_MCU_CMD_STOP_DMA			BIT(2)
451 #define MT_MCU_CMD_RESET_DONE			BIT(3)
452 #define MT_MCU_CMD_RECOVERY_DONE		BIT(4)
453 #define MT_MCU_CMD_NORMAL_STATE			BIT(5)
454 #define MT_MCU_CMD_ERROR_MASK			GENMASK(5, 1)
455 
456 #define MT_MCU_CMD_WA_WDT			BIT(31)
457 #define MT_MCU_CMD_WM_WDT			BIT(30)
458 #define MT_MCU_CMD_WDT_MASK			GENMASK(31, 30)
459 
460 /* l1/l2 remap */
461 #define MT_HIF_REMAP_L1				0x155024
462 #define MT_HIF_REMAP_L1_MASK			GENMASK(31, 16)
463 #define MT_HIF_REMAP_L1_OFFSET			GENMASK(15, 0)
464 #define MT_HIF_REMAP_L1_BASE			GENMASK(31, 16)
465 #define MT_HIF_REMAP_BASE_L1			0x130000
466 
467 #define MT_HIF_REMAP_L2				0x1b4
468 #define MT_HIF_REMAP_L2_MASK			GENMASK(19, 0)
469 #define MT_HIF_REMAP_L2_OFFSET			GENMASK(11, 0)
470 #define MT_HIF_REMAP_L2_BASE			GENMASK(31, 12)
471 #define MT_HIF_REMAP_BASE_L2			0x1000
472 
473 #define MT_INFRA_BASE				0x18000000
474 #define MT_WFSYS0_PHY_START			0x18400000
475 #define MT_WFSYS1_PHY_START			0x18800000
476 #define MT_WFSYS1_PHY_END			0x18bfffff
477 #define MT_CBTOP1_PHY_START			0x70000000
478 #define MT_CBTOP1_PHY_END			0x77ffffff
479 #define MT_CBTOP2_PHY_START			0xf0000000
480 #define MT_INFRA_MCU_START			0x7c000000
481 #define MT_INFRA_MCU_END			0x7c3fffff
482 
483 /* FW MODE SYNC */
484 #define MT_FW_ASSERT_CNT			0x02208274
485 #define MT_FW_DUMP_STATE			0x02209e90
486 
487 #define MT_SWDEF_BASE				0x00401400
488 
489 #define MT_SWDEF(ofs)				(MT_SWDEF_BASE + (ofs))
490 #define MT_SWDEF_MODE				MT_SWDEF(0x3c)
491 #define MT_SWDEF_NORMAL_MODE			0
492 
493 #define MT_SWDEF_SER_STATS			MT_SWDEF(0x040)
494 #define MT_SWDEF_PLE_STATS			MT_SWDEF(0x044)
495 #define MT_SWDEF_PLE1_STATS			MT_SWDEF(0x048)
496 #define MT_SWDEF_PLE_AMSDU_STATS		MT_SWDEF(0x04c)
497 #define MT_SWDEF_PSE_STATS			MT_SWDEF(0x050)
498 #define MT_SWDEF_PSE1_STATS			MT_SWDEF(0x054)
499 #define MT_SWDEF_LAMC_WISR6_BN0_STATS		MT_SWDEF(0x058)
500 #define MT_SWDEF_LAMC_WISR6_BN1_STATS		MT_SWDEF(0x05c)
501 #define MT_SWDEF_LAMC_WISR6_BN2_STATS		MT_SWDEF(0x060)
502 #define MT_SWDEF_LAMC_WISR7_BN0_STATS		MT_SWDEF(0x064)
503 #define MT_SWDEF_LAMC_WISR7_BN1_STATS		MT_SWDEF(0x068)
504 #define MT_SWDEF_LAMC_WISR7_BN2_STATS		MT_SWDEF(0x06c)
505 
506 /* LED */
507 #define MT_LED_TOP_BASE				0x18013000
508 #define MT_LED_PHYS(_n)				(MT_LED_TOP_BASE + (_n))
509 
510 #define MT_LED_CTRL(_n)				MT_LED_PHYS(0x00 + ((_n) * 4))
511 #define MT_LED_CTRL_KICK			BIT(7)
512 #define MT_LED_CTRL_BLINK_MODE			BIT(2)
513 #define MT_LED_CTRL_POLARITY			BIT(1)
514 
515 #define MT_LED_TX_BLINK(_n)			MT_LED_PHYS(0x10 + ((_n) * 4))
516 #define MT_LED_TX_BLINK_ON_MASK			GENMASK(7, 0)
517 #define MT_LED_TX_BLINK_OFF_MASK		GENMASK(15, 8)
518 
519 #define MT_LED_EN(_n)				MT_LED_PHYS(0x40 + ((_n) * 4))
520 
521 /* CONN DBG */
522 #define MT_CONN_DBG_CTL_BASE			0x18023000
523 #define MT_CONN_DBG_CTL(ofs)			(MT_CONN_DBG_CTL_BASE + (ofs))
524 #define MT_CONN_DBG_CTL_OUT_SEL			MT_CONN_DBG_CTL(0x604)
525 #define MT_CONN_DBG_CTL_PC_LOG_SEL		MT_CONN_DBG_CTL(0x60c)
526 #define MT_CONN_DBG_CTL_PC_LOG			MT_CONN_DBG_CTL(0x610)
527 
528 #define MT_LED_GPIO_MUX2			0x70005058 /* GPIO 18 */
529 #define MT_LED_GPIO_MUX3			0x7000505C /* GPIO 26 */
530 #define MT_LED_GPIO_SEL_MASK			GENMASK(11, 8)
531 
532 /* MT TOP */
533 #define MT_TOP_BASE				0xe0000
534 #define MT_TOP(ofs)				(MT_TOP_BASE + (ofs))
535 
536 #define MT_TOP_LPCR_HOST_BAND(_band)		MT_TOP(0x10 + ((_band) * 0x10))
537 #define MT_TOP_LPCR_HOST_FW_OWN			BIT(0)
538 #define MT_TOP_LPCR_HOST_DRV_OWN		BIT(1)
539 #define MT_TOP_LPCR_HOST_FW_OWN_STAT		BIT(2)
540 
541 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band)	MT_TOP(0x14 + ((_band) * 0x10))
542 #define MT_TOP_LPCR_HOST_BAND_STAT		BIT(0)
543 
544 #define MT_TOP_MISC				MT_TOP(0xf0)
545 #define MT_TOP_MISC_FW_STATE			GENMASK(2, 0)
546 
547 #define MT_HW_REV				0x70010204
548 #define MT_WF_SUBSYS_RST			0x70028600
549 
550 /* PCIE MAC */
551 #define MT_PCIE_MAC_BASE			0x74030000
552 #define MT_PCIE_MAC(ofs)			(MT_PCIE_MAC_BASE + (ofs))
553 #define MT_PCIE_MAC_INT_ENABLE			MT_PCIE_MAC(0x188)
554 
555 #define MT_PCIE1_MAC_BASE			0x74090000
556 #define MT_PCIE1_MAC(ofs)			(MT_PCIE1_MAC_BASE + (ofs))
557 
558 #define MT_PCIE1_MAC_INT_ENABLE			MT_PCIE1_MAC(0x188)
559 
560 /* PHYRX CTRL */
561 #define MT_WF_PHYRX_BAND_BASE			0x83080000
562 #define MT_WF_PHYRX_BAND(_band, ofs)		(MT_WF_PHYRX_BAND_BASE + \
563 						 ((_band) << 20) + (ofs))
564 
565 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band)	MT_WF_PHYRX_BAND(_band, 0x2004)
566 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN	GENMASK(2, 0)
567 #define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN	GENMASK(11, 9)
568 
569 /* PHYRX CSD */
570 #define MT_WF_PHYRX_CSD_BASE			0x83000000
571 #define MT_WF_PHYRX_CSD(_band, _wf, ofs)	(MT_WF_PHYRX_CSD_BASE + \
572 						 ((_band) << 20) + \
573 						 ((_wf) << 16) + (ofs))
574 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf)	MT_WF_PHYRX_CSD(_band, _wf, 0x1000)
575 
576 /* PHYRX CSD BAND */
577 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band)		MT_WF_PHYRX_BAND(_band, 0x8230)
578 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY	BIT(18)
579 #define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR		BIT(29)
580 
581 /* CONN MCU EXCP CON */
582 #define MT_MCU_WM_EXCP_BASE			0x89050000
583 #define MT_MCU_WM_EXCP(ofs)			(MT_MCU_WM_EXCP_BASE + (ofs))
584 #define MT_MCU_WM_EXCP_PC_CTRL			MT_MCU_WM_EXCP(0x100)
585 #define MT_MCU_WM_EXCP_PC_LOG			MT_MCU_WM_EXCP(0x104)
586 #define MT_MCU_WM_EXCP_LR_CTRL			MT_MCU_WM_EXCP(0x200)
587 #define MT_MCU_WM_EXCP_LR_LOG			MT_MCU_WM_EXCP(0x204)
588 
589 #endif
590