1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_INTERFACES 19 15 #define MT7996_MAX_WMM_SETS 4 16 #define MT7996_WTBL_SIZE 544 17 #define MT7996_WTBL_RESERVED (MT7996_WTBL_SIZE - 1) 18 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 19 MT7996_MAX_INTERFACES) 20 21 #define MT7996_WATCHDOG_TIME (HZ / 10) 22 #define MT7996_RESET_TIMEOUT (30 * HZ) 23 24 #define MT7996_TX_RING_SIZE 2048 25 #define MT7996_TX_MCU_RING_SIZE 256 26 #define MT7996_TX_FWDL_RING_SIZE 128 27 28 #define MT7996_RX_RING_SIZE 1536 29 #define MT7996_RX_MCU_RING_SIZE 512 30 31 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 32 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 33 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 34 35 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 36 #define MT7996_EEPROM_SIZE 7680 37 #define MT7996_EEPROM_BLOCK_SIZE 16 38 #define MT7996_TOKEN_SIZE 8192 39 40 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 41 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 42 43 #define MT7996_MAX_TWT_AGRT 16 44 #define MT7996_MAX_STA_TWT_AGRT 8 45 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 46 47 struct mt7996_vif; 48 struct mt7996_sta; 49 struct mt7996_dfs_pulse; 50 struct mt7996_dfs_pattern; 51 52 enum mt7996_txq_id { 53 MT7996_TXQ_FWDL = 16, 54 MT7996_TXQ_MCU_WM, 55 MT7996_TXQ_BAND0, 56 MT7996_TXQ_BAND1, 57 MT7996_TXQ_MCU_WA, 58 MT7996_TXQ_BAND2, 59 }; 60 61 enum mt7996_rxq_id { 62 MT7996_RXQ_MCU_WM = 0, 63 MT7996_RXQ_MCU_WA, 64 MT7996_RXQ_MCU_WA_MAIN = 2, 65 MT7996_RXQ_MCU_WA_EXT = 2,/* unused */ 66 MT7996_RXQ_MCU_WA_TRI = 3, 67 MT7996_RXQ_BAND0 = 4, 68 MT7996_RXQ_BAND1 = 4,/* unused */ 69 MT7996_RXQ_BAND2 = 5, 70 }; 71 72 struct mt7996_twt_flow { 73 struct list_head list; 74 u64 start_tsf; 75 u64 tsf; 76 u32 duration; 77 u16 wcid; 78 __le16 mantissa; 79 u8 exp; 80 u8 table_id; 81 u8 id; 82 u8 protection:1; 83 u8 flowtype:1; 84 u8 trigger:1; 85 u8 sched:1; 86 }; 87 88 DECLARE_EWMA(avg_signal, 10, 8) 89 90 struct mt7996_sta { 91 struct mt76_wcid wcid; /* must be first */ 92 93 struct mt7996_vif *vif; 94 95 struct list_head poll_list; 96 struct list_head rc_list; 97 u32 airtime_ac[8]; 98 99 int ack_signal; 100 struct ewma_avg_signal avg_ack_signal; 101 102 unsigned long changed; 103 unsigned long jiffies; 104 unsigned long ampdu_state; 105 106 struct mt76_sta_stats stats; 107 108 struct mt76_connac_sta_key_conf bip; 109 110 struct { 111 u8 flowid_mask; 112 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 113 } twt; 114 }; 115 116 struct mt7996_vif_cap { 117 bool ht_ldpc:1; 118 bool vht_ldpc:1; 119 bool he_ldpc:1; 120 bool vht_su_ebfer:1; 121 bool vht_su_ebfee:1; 122 bool vht_mu_ebfer:1; 123 bool vht_mu_ebfee:1; 124 bool he_su_ebfer:1; 125 bool he_su_ebfee:1; 126 bool he_mu_ebfer:1; 127 }; 128 129 struct mt7996_vif { 130 struct mt76_vif mt76; /* must be first */ 131 132 struct mt7996_vif_cap cap; 133 struct mt7996_sta sta; 134 struct mt7996_phy *phy; 135 136 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 137 struct cfg80211_bitrate_mask bitrate_mask; 138 }; 139 140 /* per-phy stats. */ 141 struct mib_stats { 142 u32 ack_fail_cnt; 143 u32 fcs_err_cnt; 144 u32 rts_cnt; 145 u32 rts_retries_cnt; 146 u32 ba_miss_cnt; 147 u32 tx_mu_bf_cnt; 148 u32 tx_mu_mpdu_cnt; 149 u32 tx_mu_acked_mpdu_cnt; 150 u32 tx_su_acked_mpdu_cnt; 151 u32 tx_bf_ibf_ppdu_cnt; 152 u32 tx_bf_ebf_ppdu_cnt; 153 154 u32 tx_bf_rx_fb_all_cnt; 155 u32 tx_bf_rx_fb_eht_cnt; 156 u32 tx_bf_rx_fb_he_cnt; 157 u32 tx_bf_rx_fb_vht_cnt; 158 u32 tx_bf_rx_fb_ht_cnt; 159 160 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 161 u32 tx_bf_rx_fb_nc_cnt; 162 u32 tx_bf_rx_fb_nr_cnt; 163 u32 tx_bf_fb_cpl_cnt; 164 u32 tx_bf_fb_trig_cnt; 165 166 u32 tx_ampdu_cnt; 167 u32 tx_stop_q_empty_cnt; 168 u32 tx_mpdu_attempts_cnt; 169 u32 tx_mpdu_success_cnt; 170 /* BF counter is PPDU-based, so remove MPDU-based BF counter */ 171 172 u32 tx_rwp_fail_cnt; 173 u32 tx_rwp_need_cnt; 174 175 /* rx stats */ 176 u32 rx_fifo_full_cnt; 177 u32 channel_idle_cnt; 178 u32 rx_vector_mismatch_cnt; 179 u32 rx_delimiter_fail_cnt; 180 u32 rx_len_mismatch_cnt; 181 u32 rx_mpdu_cnt; 182 u32 rx_ampdu_cnt; 183 u32 rx_ampdu_bytes_cnt; 184 u32 rx_ampdu_valid_subframe_cnt; 185 u32 rx_ampdu_valid_subframe_bytes_cnt; 186 u32 rx_pfdrop_cnt; 187 u32 rx_vec_queue_overflow_drop_cnt; 188 u32 rx_ba_cnt; 189 190 u32 tx_amsdu[8]; 191 u32 tx_amsdu_cnt; 192 }; 193 194 struct mt7996_hif { 195 struct list_head list; 196 197 struct device *dev; 198 void __iomem *regs; 199 int irq; 200 }; 201 202 struct mt7996_phy { 203 struct mt76_phy *mt76; 204 struct mt7996_dev *dev; 205 206 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 207 208 struct ieee80211_vif *monitor_vif; 209 210 u32 rxfilter; 211 u64 omac_mask; 212 213 u16 noise; 214 215 s16 coverage_class; 216 u8 slottime; 217 218 u8 rdd_state; 219 220 u32 rx_ampdu_ts; 221 u32 ampdu_ref; 222 223 struct mib_stats mib; 224 struct mt76_channel_state state_ts; 225 }; 226 227 struct mt7996_dev { 228 union { /* must be first */ 229 struct mt76_dev mt76; 230 struct mt76_phy mphy; 231 }; 232 233 struct mt7996_hif *hif2; 234 struct mt7996_reg_desc reg; 235 u8 q_id[MT7996_MAX_QUEUE]; 236 u32 q_int_mask[MT7996_MAX_QUEUE]; 237 u32 q_wfdma_mask; 238 239 const struct mt76_bus_ops *bus_ops; 240 struct tasklet_struct irq_tasklet; 241 struct mt7996_phy phy; 242 243 /* monitor rx chain configured channel */ 244 struct cfg80211_chan_def rdd2_chandef; 245 struct mt7996_phy *rdd2_phy; 246 247 u16 chainmask; 248 u8 chainshift[__MT_MAX_BAND]; 249 u32 hif_idx; 250 251 struct work_struct init_work; 252 struct work_struct rc_work; 253 struct work_struct reset_work; 254 wait_queue_head_t reset_wait; 255 u32 reset_state; 256 257 struct list_head sta_rc_list; 258 struct list_head sta_poll_list; 259 struct list_head twt_list; 260 spinlock_t sta_poll_lock; 261 262 u32 hw_pattern; 263 264 bool dbdc_support:1; 265 bool tbtc_support:1; 266 bool flash_mode:1; 267 268 bool ibf; 269 u8 fw_debug_wm; 270 u8 fw_debug_wa; 271 u8 fw_debug_bin; 272 u16 fw_debug_seq; 273 274 struct dentry *debugfs_dir; 275 struct rchan *relay_fwlog; 276 277 struct { 278 u8 table_mask; 279 u8 n_agrt; 280 } twt; 281 282 u32 reg_l1_backup; 283 u32 reg_l2_backup; 284 }; 285 286 enum { 287 WFDMA0 = 0x0, 288 WFDMA1, 289 WFDMA_EXT, 290 __MT_WFDMA_MAX, 291 }; 292 293 enum { 294 MT_CTX0, 295 MT_HIF0 = 0x0, 296 297 MT_LMAC_AC00 = 0x0, 298 MT_LMAC_AC01, 299 MT_LMAC_AC02, 300 MT_LMAC_AC03, 301 MT_LMAC_ALTX0 = 0x10, 302 MT_LMAC_BMC0, 303 MT_LMAC_BCN0, 304 MT_LMAC_PSMP0, 305 }; 306 307 enum { 308 MT_RX_SEL0, 309 MT_RX_SEL1, 310 MT_RX_SEL2, /* monitor chain */ 311 }; 312 313 enum mt7996_rdd_cmd { 314 RDD_STOP, 315 RDD_START, 316 RDD_DET_MODE, 317 RDD_RADAR_EMULATE, 318 RDD_START_TXQ = 20, 319 RDD_CAC_START = 50, 320 RDD_CAC_END, 321 RDD_NORMAL_START, 322 RDD_DISABLE_DFS_CAL, 323 RDD_PULSE_DBG, 324 RDD_READ_PULSE, 325 RDD_RESUME_BF, 326 RDD_IRQ_OFF, 327 }; 328 329 static inline struct mt7996_phy * 330 mt7996_hw_phy(struct ieee80211_hw *hw) 331 { 332 struct mt76_phy *phy = hw->priv; 333 334 return phy->priv; 335 } 336 337 static inline struct mt7996_dev * 338 mt7996_hw_dev(struct ieee80211_hw *hw) 339 { 340 struct mt76_phy *phy = hw->priv; 341 342 return container_of(phy->dev, struct mt7996_dev, mt76); 343 } 344 345 static inline struct mt7996_phy * 346 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 347 { 348 struct mt76_phy *phy = dev->mt76.phys[band]; 349 350 if (!phy) 351 return NULL; 352 353 return phy->priv; 354 } 355 356 static inline struct mt7996_phy * 357 mt7996_phy2(struct mt7996_dev *dev) 358 { 359 return __mt7996_phy(dev, MT_BAND1); 360 } 361 362 static inline struct mt7996_phy * 363 mt7996_phy3(struct mt7996_dev *dev) 364 { 365 return __mt7996_phy(dev, MT_BAND2); 366 } 367 368 extern const struct ieee80211_ops mt7996_ops; 369 extern struct pci_driver mt7996_pci_driver; 370 extern struct pci_driver mt7996_hif_driver; 371 372 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 373 void __iomem *mem_base, u32 device_id); 374 void mt7996_wfsys_reset(struct mt7996_dev *dev); 375 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 376 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); 377 int mt7996_register_device(struct mt7996_dev *dev); 378 void mt7996_unregister_device(struct mt7996_dev *dev); 379 int mt7996_eeprom_init(struct mt7996_dev *dev); 380 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 381 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 382 struct ieee80211_channel *chan); 383 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 384 int mt7996_dma_init(struct mt7996_dev *dev); 385 void mt7996_dma_prefetch(struct mt7996_dev *dev); 386 void mt7996_dma_cleanup(struct mt7996_dev *dev); 387 int mt7996_mcu_init(struct mt7996_dev *dev); 388 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 389 struct mt7996_vif *mvif, 390 struct mt7996_twt_flow *flow, 391 int cmd); 392 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, 393 struct ieee80211_vif *vif, bool enable); 394 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, 395 struct ieee80211_vif *vif, int enable); 396 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, 397 struct ieee80211_sta *sta, bool enable); 398 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 399 struct ieee80211_ampdu_params *params, 400 bool add); 401 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 402 struct ieee80211_ampdu_params *params, 403 bool add); 404 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif, 405 struct cfg80211_he_bss_color *he_bss_color); 406 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 407 int enable); 408 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 409 struct ieee80211_vif *vif, u32 changed); 410 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif, 411 struct ieee80211_he_obss_pd *he_obss_pd); 412 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, 413 struct ieee80211_sta *sta, bool changed); 414 int mt7996_set_channel(struct mt7996_phy *phy); 415 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 416 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif); 417 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 418 void *data, u16 version); 419 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 420 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset); 421 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); 422 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 423 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 424 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 425 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 426 const struct mt7996_dfs_pulse *pulse); 427 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 428 const struct mt7996_dfs_pattern *pattern); 429 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 430 void mt7996_mcu_set_pm(void *priv, u8 *mac, struct ieee80211_vif *vif); 431 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 432 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 433 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, 434 u8 rx_sel, u8 val); 435 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 436 struct cfg80211_chan_def *chandef); 437 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 438 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 439 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val); 440 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 441 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 442 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 443 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 444 void mt7996_mcu_exit(struct mt7996_dev *dev); 445 446 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 447 u32 clear, u32 set); 448 449 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 450 { 451 if (dev->hif2) 452 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 453 else 454 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 455 456 tasklet_schedule(&dev->irq_tasklet); 457 } 458 459 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 460 { 461 if (dev->hif2) 462 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 463 else 464 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 465 } 466 467 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 468 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 469 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 470 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 471 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 472 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 473 struct ieee80211_vif *vif, bool enable); 474 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 475 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 476 struct ieee80211_key_conf *key, u32 changed); 477 void mt7996_mac_set_timing(struct mt7996_phy *phy); 478 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 479 struct ieee80211_sta *sta); 480 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 481 struct ieee80211_sta *sta); 482 void mt7996_mac_work(struct work_struct *work); 483 void mt7996_mac_reset_work(struct work_struct *work); 484 void mt7996_mac_sta_rc_work(struct work_struct *work); 485 void mt7996_mac_update_stats(struct mt7996_phy *phy); 486 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 487 struct mt7996_sta *msta, 488 u8 flowid); 489 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 490 struct ieee80211_sta *sta, 491 struct ieee80211_twt_setup *twt); 492 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 493 enum mt76_txq_id qid, struct mt76_wcid *wcid, 494 struct ieee80211_sta *sta, 495 struct mt76_tx_info *tx_info); 496 void mt7996_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e); 497 void mt7996_tx_token_put(struct mt7996_dev *dev); 498 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 499 struct sk_buff *skb, u32 *info); 500 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 501 void mt7996_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps); 502 void mt7996_stats_work(struct work_struct *work); 503 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 504 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 505 void mt7996_set_stream_he_caps(struct mt7996_phy *phy); 506 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 507 void mt7996_update_channel(struct mt76_phy *mphy); 508 int mt7996_init_debugfs(struct mt7996_phy *phy); 509 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 510 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 511 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 512 struct mt76_connac_sta_key_conf *sta_key_conf, 513 struct ieee80211_key_conf *key, int mcu_cmd, 514 struct mt76_wcid *wcid, enum set_key_cmd cmd); 515 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 516 struct ieee80211_vif *vif, 517 struct ieee80211_sta *sta); 518 #ifdef CONFIG_MAC80211_DEBUGFS 519 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 520 struct ieee80211_sta *sta, struct dentry *dir); 521 #endif 522 523 #endif 524