1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_INTERFACES 19 /* per-band */ 15 #define MT7996_MAX_WMM_SETS 4 16 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 17 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 18 mt7996_max_interface_num(dev)) 19 20 #define MT7996_WATCHDOG_TIME (HZ / 10) 21 #define MT7996_RESET_TIMEOUT (30 * HZ) 22 23 #define MT7996_TX_RING_SIZE 2048 24 #define MT7996_TX_MCU_RING_SIZE 256 25 #define MT7996_TX_FWDL_RING_SIZE 128 26 27 #define MT7996_RX_RING_SIZE 1536 28 #define MT7996_RX_MCU_RING_SIZE 512 29 #define MT7996_RX_MCU_RING_SIZE_WA 1024 30 31 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 32 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 33 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" 34 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 35 36 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 37 #define MT7996_EEPROM_SIZE 7680 38 #define MT7996_EEPROM_BLOCK_SIZE 16 39 #define MT7996_TOKEN_SIZE 16384 40 41 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 42 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 43 44 #define MT7996_MAX_TWT_AGRT 16 45 #define MT7996_MAX_STA_TWT_AGRT 8 46 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 47 48 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 49 #define MT7996_BASIC_RATES_TBL 11 50 #define MT7996_BEACON_RATES_TBL 25 51 52 struct mt7996_vif; 53 struct mt7996_sta; 54 struct mt7996_dfs_pulse; 55 struct mt7996_dfs_pattern; 56 57 enum mt7996_ram_type { 58 MT7996_RAM_TYPE_WM, 59 MT7996_RAM_TYPE_WA, 60 MT7996_RAM_TYPE_DSP, 61 }; 62 63 enum mt7996_txq_id { 64 MT7996_TXQ_FWDL = 16, 65 MT7996_TXQ_MCU_WM, 66 MT7996_TXQ_BAND0, 67 MT7996_TXQ_BAND1, 68 MT7996_TXQ_MCU_WA, 69 MT7996_TXQ_BAND2, 70 }; 71 72 enum mt7996_rxq_id { 73 MT7996_RXQ_MCU_WM = 0, 74 MT7996_RXQ_MCU_WA, 75 MT7996_RXQ_MCU_WA_MAIN = 2, 76 MT7996_RXQ_MCU_WA_EXT = 2,/* unused */ 77 MT7996_RXQ_MCU_WA_TRI = 3, 78 MT7996_RXQ_BAND0 = 4, 79 MT7996_RXQ_BAND1 = 4,/* unused */ 80 MT7996_RXQ_BAND2 = 5, 81 }; 82 83 struct mt7996_twt_flow { 84 struct list_head list; 85 u64 start_tsf; 86 u64 tsf; 87 u32 duration; 88 u16 wcid; 89 __le16 mantissa; 90 u8 exp; 91 u8 table_id; 92 u8 id; 93 u8 protection:1; 94 u8 flowtype:1; 95 u8 trigger:1; 96 u8 sched:1; 97 }; 98 99 DECLARE_EWMA(avg_signal, 10, 8) 100 101 struct mt7996_sta { 102 struct mt76_wcid wcid; /* must be first */ 103 104 struct mt7996_vif *vif; 105 106 struct list_head rc_list; 107 u32 airtime_ac[8]; 108 109 int ack_signal; 110 struct ewma_avg_signal avg_ack_signal; 111 112 unsigned long changed; 113 unsigned long jiffies; 114 115 struct mt76_connac_sta_key_conf bip; 116 117 struct { 118 u8 flowid_mask; 119 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 120 } twt; 121 }; 122 123 struct mt7996_vif { 124 struct mt76_vif mt76; /* must be first */ 125 126 struct mt7996_sta sta; 127 struct mt7996_phy *phy; 128 129 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 130 struct cfg80211_bitrate_mask bitrate_mask; 131 }; 132 133 /* crash-dump */ 134 struct mt7996_crash_data { 135 guid_t guid; 136 struct timespec64 timestamp; 137 138 u8 *memdump_buf; 139 size_t memdump_buf_len; 140 }; 141 142 struct mt7996_hif { 143 struct list_head list; 144 145 struct device *dev; 146 void __iomem *regs; 147 int irq; 148 }; 149 150 struct mt7996_phy { 151 struct mt76_phy *mt76; 152 struct mt7996_dev *dev; 153 154 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 155 156 struct ieee80211_vif *monitor_vif; 157 158 u32 rxfilter; 159 u64 omac_mask; 160 161 u16 noise; 162 163 s16 coverage_class; 164 u8 slottime; 165 166 u8 rdd_state; 167 168 u32 rx_ampdu_ts; 169 u32 ampdu_ref; 170 171 struct mt76_mib_stats mib; 172 struct mt76_channel_state state_ts; 173 }; 174 175 struct mt7996_dev { 176 union { /* must be first */ 177 struct mt76_dev mt76; 178 struct mt76_phy mphy; 179 }; 180 181 struct mt7996_hif *hif2; 182 struct mt7996_reg_desc reg; 183 u8 q_id[MT7996_MAX_QUEUE]; 184 u32 q_int_mask[MT7996_MAX_QUEUE]; 185 u32 q_wfdma_mask; 186 187 const struct mt76_bus_ops *bus_ops; 188 struct mt7996_phy phy; 189 190 /* monitor rx chain configured channel */ 191 struct cfg80211_chan_def rdd2_chandef; 192 struct mt7996_phy *rdd2_phy; 193 194 u16 chainmask; 195 u8 chainshift[__MT_MAX_BAND]; 196 u32 hif_idx; 197 198 struct work_struct init_work; 199 struct work_struct rc_work; 200 struct work_struct dump_work; 201 struct work_struct reset_work; 202 wait_queue_head_t reset_wait; 203 struct { 204 u32 state; 205 u32 wa_reset_count; 206 u32 wm_reset_count; 207 bool hw_full_reset:1; 208 bool hw_init_done:1; 209 bool restart:1; 210 } recovery; 211 212 /* protects coredump data */ 213 struct mutex dump_mutex; 214 #ifdef CONFIG_DEV_COREDUMP 215 struct { 216 struct mt7996_crash_data *crash_data; 217 } coredump; 218 #endif 219 220 struct list_head sta_rc_list; 221 struct list_head twt_list; 222 223 u32 hw_pattern; 224 225 bool dbdc_support:1; 226 bool tbtc_support:1; 227 bool flash_mode:1; 228 bool has_eht:1; 229 230 bool ibf; 231 u8 fw_debug_wm; 232 u8 fw_debug_wa; 233 u8 fw_debug_bin; 234 u16 fw_debug_seq; 235 236 struct dentry *debugfs_dir; 237 struct rchan *relay_fwlog; 238 239 struct { 240 u8 table_mask; 241 u8 n_agrt; 242 } twt; 243 244 u32 reg_l1_backup; 245 u32 reg_l2_backup; 246 247 u8 wtbl_size_group; 248 }; 249 250 enum { 251 WFDMA0 = 0x0, 252 WFDMA1, 253 WFDMA_EXT, 254 __MT_WFDMA_MAX, 255 }; 256 257 enum { 258 MT_RX_SEL0, 259 MT_RX_SEL1, 260 MT_RX_SEL2, /* monitor chain */ 261 }; 262 263 enum mt7996_rdd_cmd { 264 RDD_STOP, 265 RDD_START, 266 RDD_DET_MODE, 267 RDD_RADAR_EMULATE, 268 RDD_START_TXQ = 20, 269 RDD_CAC_START = 50, 270 RDD_CAC_END, 271 RDD_NORMAL_START, 272 RDD_DISABLE_DFS_CAL, 273 RDD_PULSE_DBG, 274 RDD_READ_PULSE, 275 RDD_RESUME_BF, 276 RDD_IRQ_OFF, 277 }; 278 279 static inline struct mt7996_phy * 280 mt7996_hw_phy(struct ieee80211_hw *hw) 281 { 282 struct mt76_phy *phy = hw->priv; 283 284 return phy->priv; 285 } 286 287 static inline struct mt7996_dev * 288 mt7996_hw_dev(struct ieee80211_hw *hw) 289 { 290 struct mt76_phy *phy = hw->priv; 291 292 return container_of(phy->dev, struct mt7996_dev, mt76); 293 } 294 295 static inline struct mt7996_phy * 296 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 297 { 298 struct mt76_phy *phy = dev->mt76.phys[band]; 299 300 if (!phy) 301 return NULL; 302 303 return phy->priv; 304 } 305 306 static inline struct mt7996_phy * 307 mt7996_phy2(struct mt7996_dev *dev) 308 { 309 return __mt7996_phy(dev, MT_BAND1); 310 } 311 312 static inline struct mt7996_phy * 313 mt7996_phy3(struct mt7996_dev *dev) 314 { 315 return __mt7996_phy(dev, MT_BAND2); 316 } 317 318 extern const struct ieee80211_ops mt7996_ops; 319 extern struct pci_driver mt7996_pci_driver; 320 extern struct pci_driver mt7996_hif_driver; 321 322 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 323 void __iomem *mem_base, u32 device_id); 324 void mt7996_wfsys_reset(struct mt7996_dev *dev); 325 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 326 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); 327 int mt7996_register_device(struct mt7996_dev *dev); 328 void mt7996_unregister_device(struct mt7996_dev *dev); 329 int mt7996_eeprom_init(struct mt7996_dev *dev); 330 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 331 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 332 struct ieee80211_channel *chan); 333 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 334 int mt7996_dma_init(struct mt7996_dev *dev); 335 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 336 void mt7996_dma_prefetch(struct mt7996_dev *dev); 337 void mt7996_dma_cleanup(struct mt7996_dev *dev); 338 void mt7996_dma_start(struct mt7996_dev *dev, bool reset); 339 void mt7996_init_txpower(struct mt7996_dev *dev, 340 struct ieee80211_supported_band *sband); 341 int mt7996_txbf_init(struct mt7996_dev *dev); 342 void mt7996_reset(struct mt7996_dev *dev); 343 int mt7996_run(struct ieee80211_hw *hw); 344 int mt7996_mcu_init(struct mt7996_dev *dev); 345 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 346 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 347 struct mt7996_vif *mvif, 348 struct mt7996_twt_flow *flow, 349 int cmd); 350 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, 351 struct ieee80211_vif *vif, bool enable); 352 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, 353 struct ieee80211_vif *vif, int enable); 354 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, 355 struct ieee80211_sta *sta, bool enable); 356 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 357 struct ieee80211_ampdu_params *params, 358 bool add); 359 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 360 struct ieee80211_ampdu_params *params, 361 bool add); 362 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif, 363 struct cfg80211_he_bss_color *he_bss_color); 364 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 365 int enable); 366 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 367 struct ieee80211_vif *vif, u32 changed); 368 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif, 369 struct ieee80211_he_obss_pd *he_obss_pd); 370 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, 371 struct ieee80211_sta *sta, bool changed); 372 int mt7996_set_channel(struct mt7996_phy *phy); 373 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 374 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif); 375 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 376 void *data, u16 version); 377 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 378 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset); 379 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); 380 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 381 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 382 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 383 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 384 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 385 const struct mt7996_dfs_pulse *pulse); 386 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 387 const struct mt7996_dfs_pattern *pattern); 388 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 389 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 390 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif); 391 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 392 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, 393 u8 rx_sel, u8 val); 394 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 395 struct cfg80211_chan_def *chandef); 396 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 397 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 398 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val); 399 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 400 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 401 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 402 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 403 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 404 void mt7996_mcu_exit(struct mt7996_dev *dev); 405 406 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 407 { 408 return MT7996_MAX_INTERFACES * (1 + dev->dbdc_support + dev->tbtc_support); 409 } 410 411 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 412 { 413 return (dev->wtbl_size_group << 8) + 64; 414 } 415 416 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 417 u32 clear, u32 set); 418 419 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 420 { 421 if (dev->hif2) 422 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 423 else 424 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 425 426 tasklet_schedule(&dev->mt76.irq_tasklet); 427 } 428 429 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 430 { 431 if (dev->hif2) 432 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 433 else 434 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 435 } 436 437 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 438 size_t len); 439 440 void mt7996_mac_init(struct mt7996_dev *dev); 441 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 442 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 443 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 444 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 445 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 446 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 447 struct ieee80211_vif *vif, bool enable); 448 void mt7996_mac_set_fixed_rate_table(struct mt7996_dev *dev, 449 u8 tbl_idx, u16 rate_idx); 450 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 451 struct sk_buff *skb, struct mt76_wcid *wcid, 452 struct ieee80211_key_conf *key, int pid, 453 enum mt76_txq_id qid, u32 changed); 454 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 455 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 456 struct ieee80211_sta *sta); 457 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 458 struct ieee80211_sta *sta); 459 void mt7996_mac_work(struct work_struct *work); 460 void mt7996_mac_reset_work(struct work_struct *work); 461 void mt7996_mac_dump_work(struct work_struct *work); 462 void mt7996_mac_sta_rc_work(struct work_struct *work); 463 void mt7996_mac_update_stats(struct mt7996_phy *phy); 464 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 465 struct mt7996_sta *msta, 466 u8 flowid); 467 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 468 struct ieee80211_sta *sta, 469 struct ieee80211_twt_setup *twt); 470 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 471 enum mt76_txq_id qid, struct mt76_wcid *wcid, 472 struct ieee80211_sta *sta, 473 struct mt76_tx_info *tx_info); 474 void mt7996_tx_token_put(struct mt7996_dev *dev); 475 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 476 struct sk_buff *skb, u32 *info); 477 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 478 void mt7996_stats_work(struct work_struct *work); 479 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 480 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 481 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 482 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 483 void mt7996_update_channel(struct mt76_phy *mphy); 484 int mt7996_init_debugfs(struct mt7996_phy *phy); 485 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 486 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 487 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 488 struct mt76_connac_sta_key_conf *sta_key_conf, 489 struct ieee80211_key_conf *key, int mcu_cmd, 490 struct mt76_wcid *wcid, enum set_key_cmd cmd); 491 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 492 struct ieee80211_vif *vif, 493 struct ieee80211_sta *sta); 494 #ifdef CONFIG_MAC80211_DEBUGFS 495 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 496 struct ieee80211_sta *sta, struct dentry *dir); 497 #endif 498 499 #endif 500