1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_INTERFACES 19 /* per-band */ 15 #define MT7996_MAX_WMM_SETS 4 16 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 17 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 18 mt7996_max_interface_num(dev)) 19 20 #define MT7996_WATCHDOG_TIME (HZ / 10) 21 #define MT7996_RESET_TIMEOUT (30 * HZ) 22 23 #define MT7996_TX_RING_SIZE 2048 24 #define MT7996_TX_MCU_RING_SIZE 256 25 #define MT7996_TX_FWDL_RING_SIZE 128 26 27 #define MT7996_RX_RING_SIZE 1536 28 #define MT7996_RX_MCU_RING_SIZE 512 29 30 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 31 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 32 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 33 34 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 35 #define MT7996_EEPROM_SIZE 7680 36 #define MT7996_EEPROM_BLOCK_SIZE 16 37 #define MT7996_TOKEN_SIZE 8192 38 39 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 40 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 41 42 #define MT7996_MAX_TWT_AGRT 16 43 #define MT7996_MAX_STA_TWT_AGRT 8 44 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 45 46 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 47 #define MT7996_BASIC_RATES_TBL 11 48 #define MT7996_BEACON_RATES_TBL 25 49 50 struct mt7996_vif; 51 struct mt7996_sta; 52 struct mt7996_dfs_pulse; 53 struct mt7996_dfs_pattern; 54 55 enum mt7996_txq_id { 56 MT7996_TXQ_FWDL = 16, 57 MT7996_TXQ_MCU_WM, 58 MT7996_TXQ_BAND0, 59 MT7996_TXQ_BAND1, 60 MT7996_TXQ_MCU_WA, 61 MT7996_TXQ_BAND2, 62 }; 63 64 enum mt7996_rxq_id { 65 MT7996_RXQ_MCU_WM = 0, 66 MT7996_RXQ_MCU_WA, 67 MT7996_RXQ_MCU_WA_MAIN = 2, 68 MT7996_RXQ_MCU_WA_EXT = 2,/* unused */ 69 MT7996_RXQ_MCU_WA_TRI = 3, 70 MT7996_RXQ_BAND0 = 4, 71 MT7996_RXQ_BAND1 = 4,/* unused */ 72 MT7996_RXQ_BAND2 = 5, 73 }; 74 75 struct mt7996_twt_flow { 76 struct list_head list; 77 u64 start_tsf; 78 u64 tsf; 79 u32 duration; 80 u16 wcid; 81 __le16 mantissa; 82 u8 exp; 83 u8 table_id; 84 u8 id; 85 u8 protection:1; 86 u8 flowtype:1; 87 u8 trigger:1; 88 u8 sched:1; 89 }; 90 91 DECLARE_EWMA(avg_signal, 10, 8) 92 93 struct mt7996_sta { 94 struct mt76_wcid wcid; /* must be first */ 95 96 struct mt7996_vif *vif; 97 98 struct list_head poll_list; 99 struct list_head rc_list; 100 u32 airtime_ac[8]; 101 102 int ack_signal; 103 struct ewma_avg_signal avg_ack_signal; 104 105 unsigned long changed; 106 unsigned long jiffies; 107 unsigned long ampdu_state; 108 109 struct mt76_sta_stats stats; 110 111 struct mt76_connac_sta_key_conf bip; 112 113 struct { 114 u8 flowid_mask; 115 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 116 } twt; 117 }; 118 119 struct mt7996_vif { 120 struct mt76_vif mt76; /* must be first */ 121 122 struct mt7996_sta sta; 123 struct mt7996_phy *phy; 124 125 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 126 struct cfg80211_bitrate_mask bitrate_mask; 127 128 u8 basic_rates_idx; 129 u8 mcast_rates_idx; 130 u8 beacon_rates_idx; 131 }; 132 133 /* per-phy stats. */ 134 struct mib_stats { 135 u32 ack_fail_cnt; 136 u32 fcs_err_cnt; 137 u32 rts_cnt; 138 u32 rts_retries_cnt; 139 u32 ba_miss_cnt; 140 u32 tx_mu_bf_cnt; 141 u32 tx_mu_mpdu_cnt; 142 u32 tx_mu_acked_mpdu_cnt; 143 u32 tx_su_acked_mpdu_cnt; 144 u32 tx_bf_ibf_ppdu_cnt; 145 u32 tx_bf_ebf_ppdu_cnt; 146 147 u32 tx_bf_rx_fb_all_cnt; 148 u32 tx_bf_rx_fb_eht_cnt; 149 u32 tx_bf_rx_fb_he_cnt; 150 u32 tx_bf_rx_fb_vht_cnt; 151 u32 tx_bf_rx_fb_ht_cnt; 152 153 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 154 u32 tx_bf_rx_fb_nc_cnt; 155 u32 tx_bf_rx_fb_nr_cnt; 156 u32 tx_bf_fb_cpl_cnt; 157 u32 tx_bf_fb_trig_cnt; 158 159 u32 tx_ampdu_cnt; 160 u32 tx_stop_q_empty_cnt; 161 u32 tx_mpdu_attempts_cnt; 162 u32 tx_mpdu_success_cnt; 163 /* BF counter is PPDU-based, so remove MPDU-based BF counter */ 164 165 u32 tx_rwp_fail_cnt; 166 u32 tx_rwp_need_cnt; 167 168 /* rx stats */ 169 u32 rx_fifo_full_cnt; 170 u32 channel_idle_cnt; 171 u32 rx_vector_mismatch_cnt; 172 u32 rx_delimiter_fail_cnt; 173 u32 rx_len_mismatch_cnt; 174 u32 rx_mpdu_cnt; 175 u32 rx_ampdu_cnt; 176 u32 rx_ampdu_bytes_cnt; 177 u32 rx_ampdu_valid_subframe_cnt; 178 u32 rx_ampdu_valid_subframe_bytes_cnt; 179 u32 rx_pfdrop_cnt; 180 u32 rx_vec_queue_overflow_drop_cnt; 181 u32 rx_ba_cnt; 182 183 u32 tx_amsdu[8]; 184 u32 tx_amsdu_cnt; 185 }; 186 187 /* crash-dump */ 188 struct mt7996_crash_data { 189 guid_t guid; 190 struct timespec64 timestamp; 191 192 u8 *memdump_buf; 193 size_t memdump_buf_len; 194 }; 195 196 struct mt7996_hif { 197 struct list_head list; 198 199 struct device *dev; 200 void __iomem *regs; 201 int irq; 202 }; 203 204 struct mt7996_phy { 205 struct mt76_phy *mt76; 206 struct mt7996_dev *dev; 207 208 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 209 210 struct ieee80211_vif *monitor_vif; 211 212 u32 rxfilter; 213 u64 omac_mask; 214 215 u16 noise; 216 217 s16 coverage_class; 218 u8 slottime; 219 220 u8 rdd_state; 221 222 u32 rx_ampdu_ts; 223 u32 ampdu_ref; 224 225 struct mib_stats mib; 226 struct mt76_channel_state state_ts; 227 }; 228 229 struct mt7996_dev { 230 union { /* must be first */ 231 struct mt76_dev mt76; 232 struct mt76_phy mphy; 233 }; 234 235 struct mt7996_hif *hif2; 236 struct mt7996_reg_desc reg; 237 u8 q_id[MT7996_MAX_QUEUE]; 238 u32 q_int_mask[MT7996_MAX_QUEUE]; 239 u32 q_wfdma_mask; 240 241 const struct mt76_bus_ops *bus_ops; 242 struct mt7996_phy phy; 243 244 /* monitor rx chain configured channel */ 245 struct cfg80211_chan_def rdd2_chandef; 246 struct mt7996_phy *rdd2_phy; 247 248 u16 chainmask; 249 u8 chainshift[__MT_MAX_BAND]; 250 u32 hif_idx; 251 252 struct work_struct init_work; 253 struct work_struct rc_work; 254 struct work_struct dump_work; 255 struct work_struct reset_work; 256 wait_queue_head_t reset_wait; 257 struct { 258 u32 state; 259 u32 wa_reset_count; 260 u32 wm_reset_count; 261 bool hw_full_reset:1; 262 bool hw_init_done:1; 263 bool restart:1; 264 } recovery; 265 266 /* protects coredump data */ 267 struct mutex dump_mutex; 268 #ifdef CONFIG_DEV_COREDUMP 269 struct { 270 struct mt7996_crash_data *crash_data; 271 } coredump; 272 #endif 273 274 struct list_head sta_rc_list; 275 struct list_head sta_poll_list; 276 struct list_head twt_list; 277 spinlock_t sta_poll_lock; 278 279 u32 hw_pattern; 280 281 bool dbdc_support:1; 282 bool tbtc_support:1; 283 bool flash_mode:1; 284 bool has_eht:1; 285 286 bool ibf; 287 u8 fw_debug_wm; 288 u8 fw_debug_wa; 289 u8 fw_debug_bin; 290 u16 fw_debug_seq; 291 292 struct dentry *debugfs_dir; 293 struct rchan *relay_fwlog; 294 295 struct { 296 u8 table_mask; 297 u8 n_agrt; 298 } twt; 299 300 u32 reg_l1_backup; 301 u32 reg_l2_backup; 302 303 u8 wtbl_size_group; 304 }; 305 306 enum { 307 WFDMA0 = 0x0, 308 WFDMA1, 309 WFDMA_EXT, 310 __MT_WFDMA_MAX, 311 }; 312 313 enum { 314 MT_CTX0, 315 MT_HIF0 = 0x0, 316 317 MT_LMAC_AC00 = 0x0, 318 MT_LMAC_AC01, 319 MT_LMAC_AC02, 320 MT_LMAC_AC03, 321 MT_LMAC_ALTX0 = 0x10, 322 MT_LMAC_BMC0, 323 MT_LMAC_BCN0, 324 MT_LMAC_PSMP0, 325 }; 326 327 enum { 328 MT_RX_SEL0, 329 MT_RX_SEL1, 330 MT_RX_SEL2, /* monitor chain */ 331 }; 332 333 enum mt7996_rdd_cmd { 334 RDD_STOP, 335 RDD_START, 336 RDD_DET_MODE, 337 RDD_RADAR_EMULATE, 338 RDD_START_TXQ = 20, 339 RDD_CAC_START = 50, 340 RDD_CAC_END, 341 RDD_NORMAL_START, 342 RDD_DISABLE_DFS_CAL, 343 RDD_PULSE_DBG, 344 RDD_READ_PULSE, 345 RDD_RESUME_BF, 346 RDD_IRQ_OFF, 347 }; 348 349 static inline struct mt7996_phy * 350 mt7996_hw_phy(struct ieee80211_hw *hw) 351 { 352 struct mt76_phy *phy = hw->priv; 353 354 return phy->priv; 355 } 356 357 static inline struct mt7996_dev * 358 mt7996_hw_dev(struct ieee80211_hw *hw) 359 { 360 struct mt76_phy *phy = hw->priv; 361 362 return container_of(phy->dev, struct mt7996_dev, mt76); 363 } 364 365 static inline struct mt7996_phy * 366 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 367 { 368 struct mt76_phy *phy = dev->mt76.phys[band]; 369 370 if (!phy) 371 return NULL; 372 373 return phy->priv; 374 } 375 376 static inline struct mt7996_phy * 377 mt7996_phy2(struct mt7996_dev *dev) 378 { 379 return __mt7996_phy(dev, MT_BAND1); 380 } 381 382 static inline struct mt7996_phy * 383 mt7996_phy3(struct mt7996_dev *dev) 384 { 385 return __mt7996_phy(dev, MT_BAND2); 386 } 387 388 extern const struct ieee80211_ops mt7996_ops; 389 extern struct pci_driver mt7996_pci_driver; 390 extern struct pci_driver mt7996_hif_driver; 391 392 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 393 void __iomem *mem_base, u32 device_id); 394 void mt7996_wfsys_reset(struct mt7996_dev *dev); 395 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 396 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); 397 int mt7996_register_device(struct mt7996_dev *dev); 398 void mt7996_unregister_device(struct mt7996_dev *dev); 399 int mt7996_eeprom_init(struct mt7996_dev *dev); 400 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 401 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 402 struct ieee80211_channel *chan); 403 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 404 int mt7996_dma_init(struct mt7996_dev *dev); 405 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 406 void mt7996_dma_prefetch(struct mt7996_dev *dev); 407 void mt7996_dma_cleanup(struct mt7996_dev *dev); 408 void mt7996_init_txpower(struct mt7996_dev *dev, 409 struct ieee80211_supported_band *sband); 410 int mt7996_txbf_init(struct mt7996_dev *dev); 411 void mt7996_reset(struct mt7996_dev *dev); 412 int mt7996_run(struct ieee80211_hw *hw); 413 int mt7996_mcu_init(struct mt7996_dev *dev); 414 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 415 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 416 struct mt7996_vif *mvif, 417 struct mt7996_twt_flow *flow, 418 int cmd); 419 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, 420 struct ieee80211_vif *vif, bool enable); 421 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, 422 struct ieee80211_vif *vif, int enable); 423 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, 424 struct ieee80211_sta *sta, bool enable); 425 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 426 struct ieee80211_ampdu_params *params, 427 bool add); 428 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 429 struct ieee80211_ampdu_params *params, 430 bool add); 431 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif, 432 struct cfg80211_he_bss_color *he_bss_color); 433 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 434 int enable); 435 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 436 struct ieee80211_vif *vif, u32 changed); 437 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif, 438 struct ieee80211_he_obss_pd *he_obss_pd); 439 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, 440 struct ieee80211_sta *sta, bool changed); 441 int mt7996_set_channel(struct mt7996_phy *phy); 442 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 443 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif); 444 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 445 void *data, u16 version); 446 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 447 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset); 448 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); 449 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 450 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 451 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 452 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 453 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 454 const struct mt7996_dfs_pulse *pulse); 455 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 456 const struct mt7996_dfs_pattern *pattern); 457 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 458 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 459 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 460 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, 461 u8 rx_sel, u8 val); 462 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 463 struct cfg80211_chan_def *chandef); 464 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 465 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 466 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val); 467 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 468 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 469 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 470 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 471 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 472 void mt7996_mcu_exit(struct mt7996_dev *dev); 473 474 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 475 { 476 return MT7996_MAX_INTERFACES * (1 + dev->dbdc_support + dev->tbtc_support); 477 } 478 479 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 480 { 481 return (dev->wtbl_size_group << 8) + 64; 482 } 483 484 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 485 u32 clear, u32 set); 486 487 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 488 { 489 if (dev->hif2) 490 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 491 else 492 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 493 494 tasklet_schedule(&dev->mt76.irq_tasklet); 495 } 496 497 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 498 { 499 if (dev->hif2) 500 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 501 else 502 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 503 } 504 505 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 506 size_t len); 507 508 void mt7996_mac_init(struct mt7996_dev *dev); 509 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 510 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 511 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 512 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 513 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 514 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 515 struct ieee80211_vif *vif, bool enable); 516 void mt7996_mac_set_fixed_rate_table(struct mt7996_dev *dev, 517 u8 tbl_idx, u16 rate_idx); 518 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 519 struct sk_buff *skb, struct mt76_wcid *wcid, 520 struct ieee80211_key_conf *key, int pid, 521 enum mt76_txq_id qid, u32 changed); 522 void mt7996_mac_set_timing(struct mt7996_phy *phy); 523 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 524 struct ieee80211_sta *sta); 525 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 526 struct ieee80211_sta *sta); 527 void mt7996_mac_work(struct work_struct *work); 528 void mt7996_mac_reset_work(struct work_struct *work); 529 void mt7996_mac_dump_work(struct work_struct *work); 530 void mt7996_mac_sta_rc_work(struct work_struct *work); 531 void mt7996_mac_update_stats(struct mt7996_phy *phy); 532 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 533 struct mt7996_sta *msta, 534 u8 flowid); 535 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 536 struct ieee80211_sta *sta, 537 struct ieee80211_twt_setup *twt); 538 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 539 enum mt76_txq_id qid, struct mt76_wcid *wcid, 540 struct ieee80211_sta *sta, 541 struct mt76_tx_info *tx_info); 542 void mt7996_tx_token_put(struct mt7996_dev *dev); 543 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 544 struct sk_buff *skb, u32 *info); 545 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 546 void mt7996_stats_work(struct work_struct *work); 547 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 548 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 549 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 550 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 551 void mt7996_update_channel(struct mt76_phy *mphy); 552 int mt7996_init_debugfs(struct mt7996_phy *phy); 553 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 554 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 555 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 556 struct mt76_connac_sta_key_conf *sta_key_conf, 557 struct ieee80211_key_conf *key, int mcu_cmd, 558 struct mt76_wcid *wcid, enum set_key_cmd cmd); 559 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 560 struct ieee80211_vif *vif, 561 struct ieee80211_sta *sta); 562 #ifdef CONFIG_MAC80211_DEBUGFS 563 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 564 struct ieee80211_sta *sta, struct dentry *dir); 565 #endif 566 567 #endif 568