1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_INTERFACES 19 /* per-band */ 15 #define MT7996_MAX_WMM_SETS 4 16 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 17 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 18 mt7996_max_interface_num(dev)) 19 20 #define MT7996_WATCHDOG_TIME (HZ / 10) 21 #define MT7996_RESET_TIMEOUT (30 * HZ) 22 23 #define MT7996_TX_RING_SIZE 2048 24 #define MT7996_TX_MCU_RING_SIZE 256 25 #define MT7996_TX_FWDL_RING_SIZE 128 26 27 #define MT7996_RX_RING_SIZE 1536 28 #define MT7996_RX_MCU_RING_SIZE 512 29 #define MT7996_RX_MCU_RING_SIZE_WA 1024 30 31 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 32 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 33 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" 34 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 35 36 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 37 #define MT7996_EEPROM_SIZE 7680 38 #define MT7996_EEPROM_BLOCK_SIZE 16 39 #define MT7996_TOKEN_SIZE 16384 40 41 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 42 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 43 44 #define MT7996_MAX_TWT_AGRT 16 45 #define MT7996_MAX_STA_TWT_AGRT 8 46 #define MT7996_MIN_TWT_DUR 64 47 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 48 49 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 50 #define MT7996_BASIC_RATES_TBL 11 51 #define MT7996_BEACON_RATES_TBL 25 52 53 struct mt7996_vif; 54 struct mt7996_sta; 55 struct mt7996_dfs_pulse; 56 struct mt7996_dfs_pattern; 57 58 enum mt7996_ram_type { 59 MT7996_RAM_TYPE_WM, 60 MT7996_RAM_TYPE_WA, 61 MT7996_RAM_TYPE_DSP, 62 }; 63 64 enum mt7996_txq_id { 65 MT7996_TXQ_FWDL = 16, 66 MT7996_TXQ_MCU_WM, 67 MT7996_TXQ_BAND0, 68 MT7996_TXQ_BAND1, 69 MT7996_TXQ_MCU_WA, 70 MT7996_TXQ_BAND2, 71 }; 72 73 enum mt7996_rxq_id { 74 MT7996_RXQ_MCU_WM = 0, 75 MT7996_RXQ_MCU_WA, 76 MT7996_RXQ_MCU_WA_MAIN = 2, 77 MT7996_RXQ_MCU_WA_EXT = 2,/* unused */ 78 MT7996_RXQ_MCU_WA_TRI = 3, 79 MT7996_RXQ_BAND0 = 4, 80 MT7996_RXQ_BAND1 = 4,/* unused */ 81 MT7996_RXQ_BAND2 = 5, 82 }; 83 84 struct mt7996_twt_flow { 85 struct list_head list; 86 u64 start_tsf; 87 u64 tsf; 88 u32 duration; 89 u16 wcid; 90 __le16 mantissa; 91 u8 exp; 92 u8 table_id; 93 u8 id; 94 u8 protection:1; 95 u8 flowtype:1; 96 u8 trigger:1; 97 u8 sched:1; 98 }; 99 100 DECLARE_EWMA(avg_signal, 10, 8) 101 102 struct mt7996_sta { 103 struct mt76_wcid wcid; /* must be first */ 104 105 struct mt7996_vif *vif; 106 107 struct list_head rc_list; 108 u32 airtime_ac[8]; 109 110 int ack_signal; 111 struct ewma_avg_signal avg_ack_signal; 112 113 unsigned long changed; 114 unsigned long jiffies; 115 116 struct mt76_connac_sta_key_conf bip; 117 118 struct { 119 u8 flowid_mask; 120 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 121 } twt; 122 }; 123 124 struct mt7996_vif { 125 struct mt76_vif mt76; /* must be first */ 126 127 struct mt7996_sta sta; 128 struct mt7996_phy *phy; 129 130 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 131 struct cfg80211_bitrate_mask bitrate_mask; 132 }; 133 134 /* crash-dump */ 135 struct mt7996_crash_data { 136 guid_t guid; 137 struct timespec64 timestamp; 138 139 u8 *memdump_buf; 140 size_t memdump_buf_len; 141 }; 142 143 struct mt7996_hif { 144 struct list_head list; 145 146 struct device *dev; 147 void __iomem *regs; 148 int irq; 149 }; 150 151 struct mt7996_phy { 152 struct mt76_phy *mt76; 153 struct mt7996_dev *dev; 154 155 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 156 157 struct ieee80211_vif *monitor_vif; 158 159 u32 rxfilter; 160 u64 omac_mask; 161 162 u16 noise; 163 164 s16 coverage_class; 165 u8 slottime; 166 167 u8 rdd_state; 168 169 u32 rx_ampdu_ts; 170 u32 ampdu_ref; 171 172 struct mt76_mib_stats mib; 173 struct mt76_channel_state state_ts; 174 }; 175 176 struct mt7996_dev { 177 union { /* must be first */ 178 struct mt76_dev mt76; 179 struct mt76_phy mphy; 180 }; 181 182 struct mt7996_hif *hif2; 183 struct mt7996_reg_desc reg; 184 u8 q_id[MT7996_MAX_QUEUE]; 185 u32 q_int_mask[MT7996_MAX_QUEUE]; 186 u32 q_wfdma_mask; 187 188 const struct mt76_bus_ops *bus_ops; 189 struct mt7996_phy phy; 190 191 /* monitor rx chain configured channel */ 192 struct cfg80211_chan_def rdd2_chandef; 193 struct mt7996_phy *rdd2_phy; 194 195 u16 chainmask; 196 u8 chainshift[__MT_MAX_BAND]; 197 u32 hif_idx; 198 199 struct work_struct init_work; 200 struct work_struct rc_work; 201 struct work_struct dump_work; 202 struct work_struct reset_work; 203 wait_queue_head_t reset_wait; 204 struct { 205 u32 state; 206 u32 wa_reset_count; 207 u32 wm_reset_count; 208 bool hw_full_reset:1; 209 bool hw_init_done:1; 210 bool restart:1; 211 } recovery; 212 213 /* protects coredump data */ 214 struct mutex dump_mutex; 215 #ifdef CONFIG_DEV_COREDUMP 216 struct { 217 struct mt7996_crash_data *crash_data; 218 } coredump; 219 #endif 220 221 struct list_head sta_rc_list; 222 struct list_head twt_list; 223 224 u32 hw_pattern; 225 226 bool dbdc_support:1; 227 bool tbtc_support:1; 228 bool flash_mode:1; 229 bool has_eht:1; 230 231 bool ibf; 232 u8 fw_debug_wm; 233 u8 fw_debug_wa; 234 u8 fw_debug_bin; 235 u16 fw_debug_seq; 236 237 struct dentry *debugfs_dir; 238 struct rchan *relay_fwlog; 239 240 struct { 241 u16 table_mask; 242 u8 n_agrt; 243 } twt; 244 245 u32 reg_l1_backup; 246 u32 reg_l2_backup; 247 248 u8 wtbl_size_group; 249 }; 250 251 enum { 252 WFDMA0 = 0x0, 253 WFDMA1, 254 WFDMA_EXT, 255 __MT_WFDMA_MAX, 256 }; 257 258 enum { 259 MT_RX_SEL0, 260 MT_RX_SEL1, 261 MT_RX_SEL2, /* monitor chain */ 262 }; 263 264 enum mt7996_rdd_cmd { 265 RDD_STOP, 266 RDD_START, 267 RDD_DET_MODE, 268 RDD_RADAR_EMULATE, 269 RDD_START_TXQ = 20, 270 RDD_CAC_START = 50, 271 RDD_CAC_END, 272 RDD_NORMAL_START, 273 RDD_DISABLE_DFS_CAL, 274 RDD_PULSE_DBG, 275 RDD_READ_PULSE, 276 RDD_RESUME_BF, 277 RDD_IRQ_OFF, 278 }; 279 280 static inline struct mt7996_phy * 281 mt7996_hw_phy(struct ieee80211_hw *hw) 282 { 283 struct mt76_phy *phy = hw->priv; 284 285 return phy->priv; 286 } 287 288 static inline struct mt7996_dev * 289 mt7996_hw_dev(struct ieee80211_hw *hw) 290 { 291 struct mt76_phy *phy = hw->priv; 292 293 return container_of(phy->dev, struct mt7996_dev, mt76); 294 } 295 296 static inline struct mt7996_phy * 297 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 298 { 299 struct mt76_phy *phy = dev->mt76.phys[band]; 300 301 if (!phy) 302 return NULL; 303 304 return phy->priv; 305 } 306 307 static inline struct mt7996_phy * 308 mt7996_phy2(struct mt7996_dev *dev) 309 { 310 return __mt7996_phy(dev, MT_BAND1); 311 } 312 313 static inline struct mt7996_phy * 314 mt7996_phy3(struct mt7996_dev *dev) 315 { 316 return __mt7996_phy(dev, MT_BAND2); 317 } 318 319 extern const struct ieee80211_ops mt7996_ops; 320 extern struct pci_driver mt7996_pci_driver; 321 extern struct pci_driver mt7996_hif_driver; 322 323 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 324 void __iomem *mem_base, u32 device_id); 325 void mt7996_wfsys_reset(struct mt7996_dev *dev); 326 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 327 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); 328 int mt7996_register_device(struct mt7996_dev *dev); 329 void mt7996_unregister_device(struct mt7996_dev *dev); 330 int mt7996_eeprom_init(struct mt7996_dev *dev); 331 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 332 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 333 struct ieee80211_channel *chan); 334 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 335 int mt7996_dma_init(struct mt7996_dev *dev); 336 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 337 void mt7996_dma_prefetch(struct mt7996_dev *dev); 338 void mt7996_dma_cleanup(struct mt7996_dev *dev); 339 void mt7996_dma_start(struct mt7996_dev *dev, bool reset); 340 void mt7996_init_txpower(struct mt7996_dev *dev, 341 struct ieee80211_supported_band *sband); 342 int mt7996_txbf_init(struct mt7996_dev *dev); 343 void mt7996_reset(struct mt7996_dev *dev); 344 int mt7996_run(struct ieee80211_hw *hw); 345 int mt7996_mcu_init(struct mt7996_dev *dev); 346 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 347 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 348 struct mt7996_vif *mvif, 349 struct mt7996_twt_flow *flow, 350 int cmd); 351 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, 352 struct ieee80211_vif *vif, bool enable); 353 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, 354 struct ieee80211_vif *vif, int enable); 355 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, 356 struct ieee80211_sta *sta, bool enable); 357 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 358 struct ieee80211_ampdu_params *params, 359 bool add); 360 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 361 struct ieee80211_ampdu_params *params, 362 bool add); 363 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif, 364 struct cfg80211_he_bss_color *he_bss_color); 365 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 366 int enable); 367 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 368 struct ieee80211_vif *vif, u32 changed); 369 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif, 370 struct ieee80211_he_obss_pd *he_obss_pd); 371 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, 372 struct ieee80211_sta *sta, bool changed); 373 int mt7996_set_channel(struct mt7996_phy *phy); 374 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 375 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif); 376 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 377 void *data, u16 version); 378 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 379 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset); 380 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); 381 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 382 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 383 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 384 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 385 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 386 const struct mt7996_dfs_pulse *pulse); 387 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 388 const struct mt7996_dfs_pattern *pattern); 389 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 390 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 391 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif); 392 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 393 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, 394 u8 rx_sel, u8 val); 395 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 396 struct cfg80211_chan_def *chandef); 397 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 398 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 399 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val); 400 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 401 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 402 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 403 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 404 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 405 void mt7996_mcu_exit(struct mt7996_dev *dev); 406 407 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 408 { 409 return MT7996_MAX_INTERFACES * (1 + dev->dbdc_support + dev->tbtc_support); 410 } 411 412 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 413 { 414 return (dev->wtbl_size_group << 8) + 64; 415 } 416 417 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 418 u32 clear, u32 set); 419 420 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 421 { 422 if (dev->hif2) 423 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 424 else 425 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 426 427 tasklet_schedule(&dev->mt76.irq_tasklet); 428 } 429 430 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 431 { 432 if (dev->hif2) 433 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 434 else 435 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 436 } 437 438 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 439 size_t len); 440 441 void mt7996_mac_init(struct mt7996_dev *dev); 442 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 443 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 444 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 445 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 446 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 447 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 448 struct ieee80211_vif *vif, bool enable); 449 void mt7996_mac_set_fixed_rate_table(struct mt7996_dev *dev, 450 u8 tbl_idx, u16 rate_idx); 451 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 452 struct sk_buff *skb, struct mt76_wcid *wcid, 453 struct ieee80211_key_conf *key, int pid, 454 enum mt76_txq_id qid, u32 changed); 455 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 456 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 457 struct ieee80211_sta *sta); 458 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 459 struct ieee80211_sta *sta); 460 void mt7996_mac_work(struct work_struct *work); 461 void mt7996_mac_reset_work(struct work_struct *work); 462 void mt7996_mac_dump_work(struct work_struct *work); 463 void mt7996_mac_sta_rc_work(struct work_struct *work); 464 void mt7996_mac_update_stats(struct mt7996_phy *phy); 465 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 466 struct mt7996_sta *msta, 467 u8 flowid); 468 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 469 struct ieee80211_sta *sta, 470 struct ieee80211_twt_setup *twt); 471 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 472 enum mt76_txq_id qid, struct mt76_wcid *wcid, 473 struct ieee80211_sta *sta, 474 struct mt76_tx_info *tx_info); 475 void mt7996_tx_token_put(struct mt7996_dev *dev); 476 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 477 struct sk_buff *skb, u32 *info); 478 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 479 void mt7996_stats_work(struct work_struct *work); 480 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 481 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 482 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 483 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 484 void mt7996_update_channel(struct mt76_phy *mphy); 485 int mt7996_init_debugfs(struct mt7996_phy *phy); 486 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 487 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 488 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 489 struct mt76_connac_sta_key_conf *sta_key_conf, 490 struct ieee80211_key_conf *key, int mcu_cmd, 491 struct mt76_wcid *wcid, enum set_key_cmd cmd); 492 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 493 struct ieee80211_vif *vif, 494 struct ieee80211_sta *sta); 495 #ifdef CONFIG_MAC80211_DEBUGFS 496 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 497 struct ieee80211_sta *sta, struct dentry *dir); 498 #endif 499 500 #endif 501