1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (C) 2022 MediaTek Inc.
4  */
5 
6 #ifndef __MT7996_MAC_H
7 #define __MT7996_MAC_H
8 
9 #define MT_CT_PARSE_LEN			72
10 #define MT_CT_DMA_BUF_NUM		2
11 
12 #define MT_RXD0_LENGTH			GENMASK(15, 0)
13 #define MT_RXD0_PKT_TYPE		GENMASK(31, 27)
14 
15 #define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
16 #define MT_RXD0_NORMAL_IP_SUM		BIT(23)
17 #define MT_RXD0_NORMAL_UDP_TCP_SUM	BIT(24)
18 
19 #define MT_RXD0_SW_PKT_TYPE_MASK	GENMASK(31, 16)
20 #define MT_RXD0_SW_PKT_TYPE_MAP		0x380F
21 #define MT_RXD0_SW_PKT_TYPE_FRAME	0x3801
22 
23 enum rx_pkt_type {
24 	PKT_TYPE_TXS,
25 	PKT_TYPE_TXRXV,
26 	PKT_TYPE_NORMAL,
27 	PKT_TYPE_RX_DUP_RFB,
28 	PKT_TYPE_RX_TMR,
29 	PKT_TYPE_RETRIEVE,
30 	PKT_TYPE_TXRX_NOTIFY,
31 	PKT_TYPE_RX_EVENT,
32 	PKT_TYPE_RX_FW_MONITOR = 0x0c,
33 };
34 
35 /* RXD DW1 */
36 #define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(11, 0)
37 #define MT_RXD1_NORMAL_GROUP_1		BIT(16)
38 #define MT_RXD1_NORMAL_GROUP_2		BIT(17)
39 #define MT_RXD1_NORMAL_GROUP_3		BIT(18)
40 #define MT_RXD1_NORMAL_GROUP_4		BIT(19)
41 #define MT_RXD1_NORMAL_GROUP_5		BIT(20)
42 #define MT_RXD1_NORMAL_KEY_ID		GENMASK(22, 21)
43 #define MT_RXD1_NORMAL_CM		BIT(23)
44 #define MT_RXD1_NORMAL_CLM		BIT(24)
45 #define MT_RXD1_NORMAL_ICV_ERR		BIT(25)
46 #define MT_RXD1_NORMAL_TKIP_MIC_ERR	BIT(26)
47 #define MT_RXD1_NORMAL_BAND_IDX		GENMASK(28, 27)
48 #define MT_RXD1_NORMAL_SPP_EN		BIT(29)
49 #define MT_RXD1_NORMAL_ADD_OM		BIT(30)
50 #define MT_RXD1_NORMAL_SEC_DONE		BIT(31)
51 
52 /* RXD DW2 */
53 #define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)
54 #define MT_RXD2_NORMAL_MAC_HDR_LEN	GENMASK(12, 8)
55 #define MT_RXD2_NORMAL_HDR_TRANS	BIT(7)
56 #define MT_RXD2_NORMAL_HDR_OFFSET	GENMASK(15, 13)
57 #define MT_RXD2_NORMAL_SEC_MODE		GENMASK(20, 16)
58 #define MT_RXD2_NORMAL_MU_BAR		BIT(21)
59 #define MT_RXD2_NORMAL_SW_BIT		BIT(22)
60 #define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)
61 #define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)
62 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)
63 #define MT_RXD2_NORMAL_INT_FRAME	BIT(26)
64 #define MT_RXD2_NORMAL_FRAG		BIT(27)
65 #define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)
66 #define MT_RXD2_NORMAL_NDATA		BIT(29)
67 #define MT_RXD2_NORMAL_NON_AMPDU	BIT(30)
68 #define MT_RXD2_NORMAL_BF_REPORT	BIT(31)
69 
70 /* RXD DW3 */
71 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
72 #define MT_RXD3_NORMAL_CH_FREQ		GENMASK(15, 8)
73 #define MT_RXD3_NORMAL_ADDR_TYPE	GENMASK(17, 16)
74 #define MT_RXD3_NORMAL_U2M		BIT(0)
75 #define MT_RXD3_NORMAL_HTC_VLD		BIT(18)
76 #define MT_RXD3_NORMAL_BEACON_MC	BIT(20)
77 #define MT_RXD3_NORMAL_BEACON_UC	BIT(21)
78 #define MT_RXD3_NORMAL_CO_ANT		BIT(22)
79 #define MT_RXD3_NORMAL_FCS_ERR		BIT(24)
80 #define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)
81 
82 /* RXD DW4 */
83 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)
84 #define MT_RXD4_FIRST_AMSDU_FRAME	GENMASK(1, 0)
85 #define MT_RXD4_MID_AMSDU_FRAME		BIT(1)
86 #define MT_RXD4_LAST_AMSDU_FRAME	BIT(0)
87 
88 #define MT_RXV_HDR_BAND_IDX		BIT(24)
89 
90 /* RXD GROUP4 */
91 #define MT_RXD8_FRAME_CONTROL		GENMASK(15, 0)
92 
93 #define MT_RXD10_SEQ_CTRL		GENMASK(15, 0)
94 #define MT_RXD10_QOS_CTL		GENMASK(31, 16)
95 
96 #define MT_RXD11_HT_CONTROL		GENMASK(31, 0)
97 
98 /* P-RXV */
99 #define MT_PRXV_TX_RATE			GENMASK(6, 0)
100 #define MT_PRXV_TX_DCM			BIT(4)
101 #define MT_PRXV_TX_ER_SU_106T		BIT(5)
102 #define MT_PRXV_NSTS			GENMASK(10, 7)
103 #define MT_PRXV_TXBF			BIT(11)
104 #define MT_PRXV_HT_AD_CODE		BIT(12)
105 #define MT_PRXV_HE_RU_ALLOC_L		GENMASK(31, 28)
106 #define MT_PRXV_HE_RU_ALLOC_H		GENMASK(3, 0)
107 #define MT_PRXV_RCPI3			GENMASK(31, 24)
108 #define MT_PRXV_RCPI2			GENMASK(23, 16)
109 #define MT_PRXV_RCPI1			GENMASK(15, 8)
110 #define MT_PRXV_RCPI0			GENMASK(7, 0)
111 #define MT_PRXV_HT_SHORT_GI		GENMASK(4, 3)
112 #define MT_PRXV_HT_STBC			GENMASK(10, 9)
113 #define MT_PRXV_TX_MODE			GENMASK(14, 11)
114 #define MT_PRXV_FRAME_MODE		GENMASK(2, 0)
115 #define MT_PRXV_DCM			BIT(5)
116 #define MT_PRXV_NUM_RX			BIT(8, 6)
117 
118 /* C-RXV */
119 #define MT_CRXV_HT_STBC			GENMASK(1, 0)
120 #define MT_CRXV_TX_MODE			GENMASK(7, 4)
121 #define MT_CRXV_FRAME_MODE		GENMASK(10, 8)
122 #define MT_CRXV_HT_SHORT_GI		GENMASK(14, 13)
123 #define MT_CRXV_HE_LTF_SIZE		GENMASK(18, 17)
124 #define MT_CRXV_HE_LDPC_EXT_SYM		BIT(20)
125 #define MT_CRXV_HE_PE_DISAMBIG		BIT(23)
126 #define MT_CRXV_HE_NUM_USER		GENMASK(30, 24)
127 #define MT_CRXV_HE_UPLINK		BIT(31)
128 #define MT_CRXV_HE_RU0			GENMASK(7, 0)
129 #define MT_CRXV_HE_RU1			GENMASK(15, 8)
130 #define MT_CRXV_HE_RU2			GENMASK(23, 16)
131 #define MT_CRXV_HE_RU3			GENMASK(31, 24)
132 
133 #define MT_CRXV_HE_MU_AID		GENMASK(30, 20)
134 
135 #define MT_CRXV_HE_SR_MASK		GENMASK(11, 8)
136 #define MT_CRXV_HE_SR1_MASK		GENMASK(16, 12)
137 #define MT_CRXV_HE_SR2_MASK             GENMASK(20, 17)
138 #define MT_CRXV_HE_SR3_MASK             GENMASK(24, 21)
139 
140 #define MT_CRXV_HE_BSS_COLOR		GENMASK(5, 0)
141 #define MT_CRXV_HE_TXOP_DUR		GENMASK(12, 6)
142 #define MT_CRXV_HE_BEAM_CHNG		BIT(13)
143 #define MT_CRXV_HE_DOPPLER		BIT(16)
144 
145 enum tx_header_format {
146 	MT_HDR_FORMAT_802_3,
147 	MT_HDR_FORMAT_CMD,
148 	MT_HDR_FORMAT_802_11,
149 	MT_HDR_FORMAT_802_11_EXT,
150 };
151 
152 enum tx_pkt_type {
153 	MT_TX_TYPE_CT,
154 	MT_TX_TYPE_SF,
155 	MT_TX_TYPE_CMD,
156 	MT_TX_TYPE_FW,
157 };
158 
159 enum tx_port_idx {
160 	MT_TX_PORT_IDX_LMAC,
161 	MT_TX_PORT_IDX_MCU
162 };
163 
164 enum tx_mcu_port_q_idx {
165 	MT_TX_MCU_PORT_RX_Q0 = 0x20,
166 	MT_TX_MCU_PORT_RX_Q1,
167 	MT_TX_MCU_PORT_RX_Q2,
168 	MT_TX_MCU_PORT_RX_Q3,
169 	MT_TX_MCU_PORT_RX_FWDL = 0x3e
170 };
171 
172 enum tx_mgnt_type {
173 	MT_TX_NORMAL,
174 	MT_TX_TIMING,
175 	MT_TX_ADDBA,
176 };
177 
178 #define MT_CT_INFO_APPLY_TXD		BIT(0)
179 #define MT_CT_INFO_COPY_HOST_TXD_ALL	BIT(1)
180 #define MT_CT_INFO_MGMT_FRAME		BIT(2)
181 #define MT_CT_INFO_NONE_CIPHER_FRAME	BIT(3)
182 #define MT_CT_INFO_HSR2_TX		BIT(4)
183 #define MT_CT_INFO_FROM_HOST		BIT(7)
184 
185 #define MT_TXD_SIZE			(8 * 4)
186 
187 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
188 #define MT_TXD0_PKT_FMT			GENMASK(24, 23)
189 #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
190 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
191 
192 #define MT_TXD1_FIXED_RATE		BIT(31)
193 #define MT_TXD1_OWN_MAC			GENMASK(30, 25)
194 #define MT_TXD1_TID			GENMASK(24, 21)
195 #define MT_TXD1_BIP			BIT(24)
196 #define MT_TXD1_ETH_802_3		BIT(20)
197 #define MT_TXD1_HDR_INFO		GENMASK(20, 16)
198 #define MT_TXD1_HDR_FORMAT		GENMASK(15, 14)
199 #define MT_TXD1_TGID			GENMASK(13, 12)
200 #define MT_TXD1_WLAN_IDX		GENMASK(11, 0)
201 
202 #define MT_TXD2_POWER_OFFSET		GENMASK(31, 26)
203 #define MT_TXD2_MAX_TX_TIME		GENMASK(25, 16)
204 #define MT_TXD2_FRAG			GENMASK(15, 14)
205 #define MT_TXD2_HTC_VLD			BIT(13)
206 #define MT_TXD2_DURATION		BIT(12)
207 #define MT_TXD2_HDR_PAD			GENMASK(11, 10)
208 #define MT_TXD2_RTS			BIT(9)
209 #define MT_TXD2_OWN_MAC_MAP		BIT(8)
210 #define MT_TXD2_BF_TYPE			GENMASK(6, 7)
211 #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
212 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
213 
214 #define MT_TXD3_SN_VALID		BIT(31)
215 #define MT_TXD3_PN_VALID		BIT(30)
216 #define MT_TXD3_SW_POWER_MGMT		BIT(29)
217 #define MT_TXD3_BA_DISABLE		BIT(28)
218 #define MT_TXD3_SEQ			GENMASK(27, 16)
219 #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
220 #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
221 #define MT_TXD3_HW_AMSDU		BIT(5)
222 #define MT_TXD3_BCM			BIT(4)
223 #define MT_TXD3_EEOSP			BIT(3)
224 #define MT_TXD3_EMRD			BIT(2)
225 #define MT_TXD3_PROTECT_FRAME		BIT(1)
226 #define MT_TXD3_NO_ACK			BIT(0)
227 
228 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
229 
230 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
231 #define MT_TXD5_FL			BIT(15)
232 #define MT_TXD5_BYPASS_TBB		BIT(14)
233 #define MT_TXD5_BYPASS_RBB		BIT(13)
234 #define MT_TXD5_BSS_COLOR_ZERO		BIT(12)
235 #define MT_TXD5_TX_STATUS_HOST		BIT(10)
236 #define MT_TXD5_TX_STATUS_MCU		BIT(9)
237 #define MT_TXD5_TX_STATUS_FMT		BIT(8)
238 #define MT_TXD5_PID			GENMASK(7, 0)
239 
240 #define MT_TXD6_TX_SRC			GENMASK(31, 30)
241 #define MT_TXD6_VTA			BIT(28)
242 #define MT_TXD6_FIXED_BW		BIT(25)
243 #define MT_TXD6_BW			GENMASK(24, 22)
244 #define MT_TXD6_TX_RATE			GENMASK(21, 16)
245 #define MT_TXD6_TIMESTAMP_OFS_EN	BIT(15)
246 #define MT_TXD6_TIMESTAMP_OFS_IDX	GENMASK(14, 10)
247 #define MT_TXD6_MSDU_CNT		GENMASK(9, 4)
248 #define MT_TXD6_SPE_ID_IDX		BIT(10)
249 #define MT_TXD6_ANT_ID			GENMASK(7, 4)
250 #define MT_TXD6_DIS_MAT			BIT(3)
251 #define MT_TXD6_DAS			BIT(2)
252 #define MT_TXD6_AMSDU_CAP		BIT(1)
253 
254 #define MT_TXD7_TXD_LEN			GENMASK(31, 30)
255 #define MT_TXD7_IP_SUM			BIT(29)
256 #define MT_TXD7_DROP_BY_SDO		BIT(28)
257 #define MT_TXD7_MAC_TXD			BIT(27)
258 #define MT_TXD7_CTXD			BIT(26)
259 #define MT_TXD7_CTXD_CNT		GENMASK(25, 22)
260 #define MT_TXD7_UDP_TCP_SUM		BIT(15)
261 #define MT_TXD7_TX_TIME			GENMASK(9, 0)
262 
263 #define MT_TX_RATE_STBC			BIT(13)
264 #define MT_TX_RATE_NSS			GENMASK(13, 10)
265 #define MT_TX_RATE_MODE			GENMASK(9, 6)
266 #define MT_TX_RATE_SU_EXT_TONE		BIT(5)
267 #define MT_TX_RATE_DCM			BIT(4)
268 /* VHT/HE only use bits 0-3 */
269 #define MT_TX_RATE_IDX			GENMASK(5, 0)
270 
271 struct mt7996_txp {
272 	__le16 flags;
273 	__le16 token;
274 	u8 bss_idx;
275 	__le16 rept_wds_wcid;
276 	u8 nbuf;
277 #define MT_TXP_MAX_BUF_NUM	6
278 	__le32 buf[MT_TXP_MAX_BUF_NUM];
279 	__le16 len[MT_TXP_MAX_BUF_NUM];
280 } __packed __aligned(4);
281 
282 #define MT_TXFREE0_PKT_TYPE		GENMASK(31, 27)
283 #define MT_TXFREE0_MSDU_CNT		GENMASK(25, 16)
284 #define MT_TXFREE0_RX_BYTE		GENMASK(15, 0)
285 
286 #define MT_TXFREE1_VER			GENMASK(18, 16)
287 
288 #define MT_TXFREE_INFO_PAIR		BIT(31)
289 #define MT_TXFREE_INFO_HEADER		BIT(30)
290 #define MT_TXFREE_INFO_WLAN_ID		GENMASK(23, 12)
291 #define MT_TXFREE_INFO_MSDU_ID		GENMASK(14, 0)
292 
293 #define MT_TXS0_BW			GENMASK(31, 29)
294 #define MT_TXS0_TID			GENMASK(28, 26)
295 #define MT_TXS0_AMPDU			BIT(25)
296 #define MT_TXS0_TXS_FORMAT		GENMASK(24, 23)
297 #define MT_TXS0_BA_ERROR		BIT(22)
298 #define MT_TXS0_PS_FLAG			BIT(21)
299 #define MT_TXS0_TXOP_TIMEOUT		BIT(20)
300 #define MT_TXS0_BIP_ERROR		BIT(19)
301 
302 #define MT_TXS0_QUEUE_TIMEOUT		BIT(18)
303 #define MT_TXS0_RTS_TIMEOUT		BIT(17)
304 #define MT_TXS0_ACK_TIMEOUT		BIT(16)
305 #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
306 
307 #define MT_TXS0_TX_STATUS_HOST		BIT(15)
308 #define MT_TXS0_TX_STATUS_MCU		BIT(14)
309 #define MT_TXS0_TX_RATE			GENMASK(13, 0)
310 
311 #define MT_TXS1_SEQNO			GENMASK(31, 20)
312 #define MT_TXS1_RESP_RATE		GENMASK(19, 16)
313 #define MT_TXS1_RXV_SEQNO		GENMASK(15, 8)
314 #define MT_TXS1_TX_POWER_DBM		GENMASK(7, 0)
315 
316 #define MT_TXS2_BF_STATUS		GENMASK(31, 30)
317 #define MT_TXS2_BAND			GENMASK(29, 28)
318 #define MT_TXS2_WCID			GENMASK(27, 16)
319 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
320 
321 #define MT_TXS3_PID			GENMASK(31, 24)
322 #define MT_TXS3_RATE_STBC		BIT(7)
323 #define MT_TXS3_FIXED_RATE		BIT(6)
324 #define MT_TXS3_SRC			GENMASK(5, 4)
325 #define MT_TXS3_SHARED_ANTENNA		BIT(3)
326 #define MT_TXS3_LAST_TX_RATE		GENMASK(2, 0)
327 
328 #define MT_TXS4_TIMESTAMP		GENMASK(31, 0)
329 
330 #define MT_TXS5_F0_FINAL_MPDU		BIT(31)
331 #define MT_TXS5_F0_QOS			BIT(30)
332 #define MT_TXS5_F0_TX_COUNT		GENMASK(29, 25)
333 #define MT_TXS5_F0_FRONT_TIME		GENMASK(24, 0)
334 #define MT_TXS5_F1_MPDU_TX_COUNT	GENMASK(31, 24)
335 #define MT_TXS5_F1_MPDU_TX_BYTES	GENMASK(23, 0)
336 
337 #define MT_TXS6_F0_NOISE_3		GENMASK(31, 24)
338 #define MT_TXS6_F0_NOISE_2		GENMASK(23, 16)
339 #define MT_TXS6_F0_NOISE_1		GENMASK(15, 8)
340 #define MT_TXS6_F0_NOISE_0		GENMASK(7, 0)
341 #define MT_TXS6_F1_MPDU_FAIL_COUNT	GENMASK(31, 24)
342 #define MT_TXS6_F1_MPDU_FAIL_BYTES	GENMASK(23, 0)
343 
344 #define MT_TXS7_F0_RCPI_3		GENMASK(31, 24)
345 #define MT_TXS7_F0_RCPI_2		GENMASK(23, 16)
346 #define MT_TXS7_F0_RCPI_1		GENMASK(15, 8)
347 #define MT_TXS7_F0_RCPI_0		GENMASK(7, 0)
348 #define MT_TXS7_F1_MPDU_RETRY_COUNT	GENMASK(31, 24)
349 #define MT_TXS7_F1_MPDU_RETRY_BYTES	GENMASK(23, 0)
350 
351 struct mt7996_dfs_pulse {
352 	u32 max_width;		/* us */
353 	int max_pwr;		/* dbm */
354 	int min_pwr;		/* dbm */
355 	u32 min_stgr_pri;	/* us */
356 	u32 max_stgr_pri;	/* us */
357 	u32 min_cr_pri;		/* us */
358 	u32 max_cr_pri;		/* us */
359 };
360 
361 struct mt7996_dfs_pattern {
362 	u8 enb;
363 	u8 stgr;
364 	u8 min_crpn;
365 	u8 max_crpn;
366 	u8 min_crpr;
367 	u8 min_pw;
368 	u32 min_pri;
369 	u32 max_pri;
370 	u8 max_pw;
371 	u8 min_crbn;
372 	u8 max_crbn;
373 	u8 min_stgpn;
374 	u8 max_stgpn;
375 	u8 min_stgpr;
376 	u8 rsv[2];
377 	u32 min_stgpr_diff;
378 } __packed;
379 
380 struct mt7996_dfs_radar_spec {
381 	struct mt7996_dfs_pulse pulse_th;
382 	struct mt7996_dfs_pattern radar_pattern[16];
383 };
384 
385 static inline struct mt7996_txp *
386 mt7996_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
387 {
388 	u8 *txwi;
389 
390 	if (!t)
391 		return NULL;
392 
393 	txwi = mt76_get_txwi_ptr(dev, t);
394 
395 	return (struct mt7996_txp *)(txwi + MT_TXD_SIZE);
396 }
397 
398 #endif
399