1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/timekeeping.h> 8 #include "mt7996.h" 9 #include "../dma.h" 10 #include "mac.h" 11 #include "mcu.h" 12 13 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 14 15 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 16 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 17 IEEE80211_RADIOTAP_HE_##f) 18 19 static const struct mt7996_dfs_radar_spec etsi_radar_specs = { 20 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 21 .radar_pattern = { 22 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 23 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 24 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 25 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 26 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 27 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 28 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 29 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 30 }, 31 }; 32 33 static const struct mt7996_dfs_radar_spec fcc_radar_specs = { 34 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 35 .radar_pattern = { 36 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 37 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 38 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 39 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 40 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 41 }, 42 }; 43 44 static const struct mt7996_dfs_radar_spec jp_radar_specs = { 45 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 46 .radar_pattern = { 47 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 48 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 49 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 50 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 51 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 52 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 53 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 54 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 55 }, 56 }; 57 58 static struct mt76_wcid *mt7996_rx_get_wcid(struct mt7996_dev *dev, 59 u16 idx, bool unicast) 60 { 61 struct mt7996_sta *sta; 62 struct mt76_wcid *wcid; 63 64 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 65 return NULL; 66 67 wcid = rcu_dereference(dev->mt76.wcid[idx]); 68 if (unicast || !wcid) 69 return wcid; 70 71 if (!wcid->sta) 72 return NULL; 73 74 sta = container_of(wcid, struct mt7996_sta, wcid); 75 if (!sta->vif) 76 return NULL; 77 78 return &sta->vif->sta.wcid; 79 } 80 81 void mt7996_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 82 { 83 } 84 85 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask) 86 { 87 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 88 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 89 90 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 91 0, 5000); 92 } 93 94 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw) 95 { 96 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 97 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 98 99 return MT_WTBL_LMAC_OFFS(wcid, dw); 100 } 101 102 static void mt7996_mac_sta_poll(struct mt7996_dev *dev) 103 { 104 static const u8 ac_to_tid[] = { 105 [IEEE80211_AC_BE] = 0, 106 [IEEE80211_AC_BK] = 1, 107 [IEEE80211_AC_VI] = 4, 108 [IEEE80211_AC_VO] = 6 109 }; 110 struct ieee80211_sta *sta; 111 struct mt7996_sta *msta; 112 struct rate_info *rate; 113 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 114 LIST_HEAD(sta_poll_list); 115 int i; 116 117 spin_lock_bh(&dev->sta_poll_lock); 118 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 119 spin_unlock_bh(&dev->sta_poll_lock); 120 121 rcu_read_lock(); 122 123 while (true) { 124 bool clear = false; 125 u32 addr, val; 126 u16 idx; 127 s8 rssi[4]; 128 u8 bw; 129 130 spin_lock_bh(&dev->sta_poll_lock); 131 if (list_empty(&sta_poll_list)) { 132 spin_unlock_bh(&dev->sta_poll_lock); 133 break; 134 } 135 msta = list_first_entry(&sta_poll_list, 136 struct mt7996_sta, poll_list); 137 list_del_init(&msta->poll_list); 138 spin_unlock_bh(&dev->sta_poll_lock); 139 140 idx = msta->wcid.idx; 141 142 /* refresh peer's airtime reporting */ 143 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 20); 144 145 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 146 u32 tx_last = msta->airtime_ac[i]; 147 u32 rx_last = msta->airtime_ac[i + 4]; 148 149 msta->airtime_ac[i] = mt76_rr(dev, addr); 150 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 151 152 tx_time[i] = msta->airtime_ac[i] - tx_last; 153 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 154 155 if ((tx_last | rx_last) & BIT(30)) 156 clear = true; 157 158 addr += 8; 159 } 160 161 if (clear) { 162 mt7996_mac_wtbl_update(dev, idx, 163 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 164 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 165 } 166 167 if (!msta->wcid.sta) 168 continue; 169 170 sta = container_of((void *)msta, struct ieee80211_sta, 171 drv_priv); 172 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 173 u8 q = mt76_connac_lmac_mapping(i); 174 u32 tx_cur = tx_time[q]; 175 u32 rx_cur = rx_time[q]; 176 u8 tid = ac_to_tid[i]; 177 178 if (!tx_cur && !rx_cur) 179 continue; 180 181 ieee80211_sta_register_airtime(sta, tid, tx_cur, rx_cur); 182 } 183 184 /* We don't support reading GI info from txs packets. 185 * For accurate tx status reporting and AQL improvement, 186 * we need to make sure that flags match so polling GI 187 * from per-sta counters directly. 188 */ 189 rate = &msta->wcid.rate; 190 191 switch (rate->bw) { 192 case RATE_INFO_BW_320: 193 bw = IEEE80211_STA_RX_BW_320; 194 break; 195 case RATE_INFO_BW_160: 196 bw = IEEE80211_STA_RX_BW_160; 197 break; 198 case RATE_INFO_BW_80: 199 bw = IEEE80211_STA_RX_BW_80; 200 break; 201 case RATE_INFO_BW_40: 202 bw = IEEE80211_STA_RX_BW_40; 203 break; 204 default: 205 bw = IEEE80211_STA_RX_BW_20; 206 break; 207 } 208 209 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 6); 210 val = mt76_rr(dev, addr); 211 if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) { 212 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 5); 213 val = mt76_rr(dev, addr); 214 rate->eht_gi = FIELD_GET(GENMASK(25, 24), val); 215 } else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 216 u8 offs = 24 + 2 * bw; 217 218 rate->he_gi = (val & (0x3 << offs)) >> offs; 219 } else if (rate->flags & 220 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 221 if (val & BIT(12 + bw)) 222 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 223 else 224 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 225 } 226 227 /* get signal strength of resp frames (CTS/BA/ACK) */ 228 addr = mt7996_mac_wtbl_lmac_addr(dev, idx, 34); 229 val = mt76_rr(dev, addr); 230 231 rssi[0] = to_rssi(GENMASK(7, 0), val); 232 rssi[1] = to_rssi(GENMASK(15, 8), val); 233 rssi[2] = to_rssi(GENMASK(23, 16), val); 234 rssi[3] = to_rssi(GENMASK(31, 14), val); 235 236 msta->ack_signal = 237 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 238 239 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 240 } 241 242 rcu_read_unlock(); 243 } 244 245 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 246 struct ieee80211_vif *vif, bool enable) 247 { 248 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 249 u32 addr; 250 251 addr = mt7996_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 252 if (enable) 253 mt76_set(dev, addr, BIT(5)); 254 else 255 mt76_clear(dev, addr, BIT(5)); 256 } 257 258 static void 259 mt7996_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 260 struct ieee80211_radiotap_he *he, 261 __le32 *rxv) 262 { 263 u32 ru_h, ru_l; 264 u8 ru, offs = 0; 265 266 ru_l = le32_get_bits(rxv[0], MT_PRXV_HE_RU_ALLOC_L); 267 ru_h = le32_get_bits(rxv[1], MT_PRXV_HE_RU_ALLOC_H); 268 ru = (u8)(ru_l | ru_h << 4); 269 270 status->bw = RATE_INFO_BW_HE_RU; 271 272 switch (ru) { 273 case 0 ... 36: 274 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 275 offs = ru; 276 break; 277 case 37 ... 52: 278 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 279 offs = ru - 37; 280 break; 281 case 53 ... 60: 282 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 283 offs = ru - 53; 284 break; 285 case 61 ... 64: 286 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 287 offs = ru - 61; 288 break; 289 case 65 ... 66: 290 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 291 offs = ru - 65; 292 break; 293 case 67: 294 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 295 break; 296 case 68: 297 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 298 break; 299 } 300 301 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 302 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 303 le16_encode_bits(offs, 304 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 305 } 306 307 static void 308 mt7996_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv) 309 { 310 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 311 static const struct ieee80211_radiotap_he_mu mu_known = { 312 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 313 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 314 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 315 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN), 316 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN), 317 }; 318 struct ieee80211_radiotap_he_mu *he_mu = NULL; 319 320 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 321 322 he_mu = skb_push(skb, sizeof(mu_known)); 323 memcpy(he_mu, &mu_known, sizeof(mu_known)); 324 325 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 326 327 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 328 if (status->he_dcm) 329 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 330 331 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 332 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 333 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 334 335 he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0); 336 337 if (status->bw >= RATE_INFO_BW_40) { 338 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 339 he_mu->ru_ch2[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU1); 340 } 341 342 if (status->bw >= RATE_INFO_BW_80) { 343 he_mu->ru_ch1[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU2); 344 he_mu->ru_ch2[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU3); 345 } 346 } 347 348 static void 349 mt7996_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u8 mode) 350 { 351 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 352 static const struct ieee80211_radiotap_he known = { 353 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 354 HE_BITS(DATA1_DATA_DCM_KNOWN) | 355 HE_BITS(DATA1_STBC_KNOWN) | 356 HE_BITS(DATA1_CODING_KNOWN) | 357 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 358 HE_BITS(DATA1_DOPPLER_KNOWN) | 359 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 360 HE_BITS(DATA1_BSS_COLOR_KNOWN), 361 .data2 = HE_BITS(DATA2_GI_KNOWN) | 362 HE_BITS(DATA2_TXBF_KNOWN) | 363 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 364 HE_BITS(DATA2_TXOP_KNOWN), 365 }; 366 struct ieee80211_radiotap_he *he = NULL; 367 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 368 369 status->flag |= RX_FLAG_RADIOTAP_HE; 370 371 he = skb_push(skb, sizeof(known)); 372 memcpy(he, &known, sizeof(known)); 373 374 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 375 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 376 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 377 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 378 le16_encode_bits(ltf_size, 379 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 380 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 381 he->data5 |= HE_BITS(DATA5_TXBF); 382 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 383 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 384 385 switch (mode) { 386 case MT_PHY_TYPE_HE_SU: 387 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 388 HE_BITS(DATA1_UL_DL_KNOWN) | 389 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) | 390 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 391 392 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 393 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 394 break; 395 case MT_PHY_TYPE_HE_EXT_SU: 396 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 397 HE_BITS(DATA1_UL_DL_KNOWN) | 398 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 399 400 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 401 break; 402 case MT_PHY_TYPE_HE_MU: 403 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 404 HE_BITS(DATA1_UL_DL_KNOWN); 405 406 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 407 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 408 409 mt7996_mac_decode_he_radiotap_ru(status, he, rxv); 410 mt7996_mac_decode_he_mu_radiotap(skb, rxv); 411 break; 412 case MT_PHY_TYPE_HE_TB: 413 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 414 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 415 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 416 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 417 418 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 419 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 420 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 421 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 422 423 mt7996_mac_decode_he_radiotap_ru(status, he, rxv); 424 break; 425 default: 426 break; 427 } 428 } 429 430 /* The HW does not translate the mac header to 802.3 for mesh point */ 431 static int mt7996_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 432 { 433 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 434 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 435 struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 436 __le32 *rxd = (__le32 *)skb->data; 437 struct ieee80211_sta *sta; 438 struct ieee80211_vif *vif; 439 struct ieee80211_hdr hdr; 440 u16 frame_control; 441 442 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != 443 MT_RXD3_NORMAL_U2M) 444 return -EINVAL; 445 446 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 447 return -EINVAL; 448 449 if (!msta || !msta->vif) 450 return -EINVAL; 451 452 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 453 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 454 455 /* store the info from RXD and ethhdr to avoid being overridden */ 456 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); 457 hdr.frame_control = cpu_to_le16(frame_control); 458 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_SEQ_CTRL)); 459 hdr.duration_id = 0; 460 461 ether_addr_copy(hdr.addr1, vif->addr); 462 ether_addr_copy(hdr.addr2, sta->addr); 463 switch (frame_control & (IEEE80211_FCTL_TODS | 464 IEEE80211_FCTL_FROMDS)) { 465 case 0: 466 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 467 break; 468 case IEEE80211_FCTL_FROMDS: 469 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 470 break; 471 case IEEE80211_FCTL_TODS: 472 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 473 break; 474 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 475 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 476 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 477 break; 478 default: 479 return -EINVAL; 480 } 481 482 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 483 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 484 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 485 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 486 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 487 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 488 else 489 skb_pull(skb, 2); 490 491 if (ieee80211_has_order(hdr.frame_control)) 492 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[11], 493 IEEE80211_HT_CTL_LEN); 494 if (ieee80211_is_data_qos(hdr.frame_control)) { 495 __le16 qos_ctrl; 496 497 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[10], MT_RXD10_QOS_CTL)); 498 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 499 IEEE80211_QOS_CTL_LEN); 500 } 501 502 if (ieee80211_has_a4(hdr.frame_control)) 503 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 504 else 505 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 506 507 return 0; 508 } 509 510 static int 511 mt7996_mac_fill_rx_rate(struct mt7996_dev *dev, 512 struct mt76_rx_status *status, 513 struct ieee80211_supported_band *sband, 514 __le32 *rxv, u8 *mode) 515 { 516 u32 v0, v2; 517 u8 stbc, gi, bw, dcm, nss; 518 int i, idx; 519 bool cck = false; 520 521 v0 = le32_to_cpu(rxv[0]); 522 v2 = le32_to_cpu(rxv[2]); 523 524 idx = FIELD_GET(MT_PRXV_TX_RATE, v0); 525 i = idx; 526 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 527 528 stbc = FIELD_GET(MT_PRXV_HT_STBC, v2); 529 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v2); 530 *mode = FIELD_GET(MT_PRXV_TX_MODE, v2); 531 dcm = FIELD_GET(MT_PRXV_DCM, v2); 532 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v2); 533 534 switch (*mode) { 535 case MT_PHY_TYPE_CCK: 536 cck = true; 537 fallthrough; 538 case MT_PHY_TYPE_OFDM: 539 i = mt76_get_rate(&dev->mt76, sband, i, cck); 540 break; 541 case MT_PHY_TYPE_HT_GF: 542 case MT_PHY_TYPE_HT: 543 status->encoding = RX_ENC_HT; 544 if (gi) 545 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 546 if (i > 31) 547 return -EINVAL; 548 break; 549 case MT_PHY_TYPE_VHT: 550 status->nss = nss; 551 status->encoding = RX_ENC_VHT; 552 if (gi) 553 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 554 if (i > 11) 555 return -EINVAL; 556 break; 557 case MT_PHY_TYPE_HE_MU: 558 case MT_PHY_TYPE_HE_SU: 559 case MT_PHY_TYPE_HE_EXT_SU: 560 case MT_PHY_TYPE_HE_TB: 561 status->nss = nss; 562 status->encoding = RX_ENC_HE; 563 i &= GENMASK(3, 0); 564 565 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 566 status->he_gi = gi; 567 568 status->he_dcm = dcm; 569 break; 570 case MT_PHY_TYPE_EHT_SU: 571 case MT_PHY_TYPE_EHT_TRIG: 572 case MT_PHY_TYPE_EHT_MU: 573 /* TODO: currently report rx rate with HE rate */ 574 status->nss = nss; 575 status->encoding = RX_ENC_HE; 576 bw = min_t(int, bw, IEEE80211_STA_RX_BW_160); 577 i = min_t(int, i & 0xf, 11); 578 break; 579 default: 580 return -EINVAL; 581 } 582 status->rate_idx = i; 583 584 switch (bw) { 585 case IEEE80211_STA_RX_BW_20: 586 break; 587 case IEEE80211_STA_RX_BW_40: 588 if (*mode & MT_PHY_TYPE_HE_EXT_SU && 589 (idx & MT_PRXV_TX_ER_SU_106T)) { 590 status->bw = RATE_INFO_BW_HE_RU; 591 status->he_ru = 592 NL80211_RATE_INFO_HE_RU_ALLOC_106; 593 } else { 594 status->bw = RATE_INFO_BW_40; 595 } 596 break; 597 case IEEE80211_STA_RX_BW_80: 598 status->bw = RATE_INFO_BW_80; 599 break; 600 case IEEE80211_STA_RX_BW_160: 601 status->bw = RATE_INFO_BW_160; 602 break; 603 case IEEE80211_STA_RX_BW_320: 604 status->bw = RATE_INFO_BW_320; 605 break; 606 default: 607 return -EINVAL; 608 } 609 610 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 611 if (*mode < MT_PHY_TYPE_HE_SU && gi) 612 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 613 614 return 0; 615 } 616 617 static int 618 mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb) 619 { 620 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 621 struct mt76_phy *mphy = &dev->mt76.phy; 622 struct mt7996_phy *phy = &dev->phy; 623 struct ieee80211_supported_band *sband; 624 __le32 *rxd = (__le32 *)skb->data; 625 __le32 *rxv = NULL; 626 u32 rxd0 = le32_to_cpu(rxd[0]); 627 u32 rxd1 = le32_to_cpu(rxd[1]); 628 u32 rxd2 = le32_to_cpu(rxd[2]); 629 u32 rxd3 = le32_to_cpu(rxd[3]); 630 u32 rxd4 = le32_to_cpu(rxd[4]); 631 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 632 u32 csum_status = *(u32 *)skb->cb; 633 bool unicast, insert_ccmp_hdr = false; 634 u8 remove_pad, amsdu_info, band_idx; 635 u8 mode = 0, qos_ctl = 0; 636 bool hdr_trans; 637 u16 hdr_gap; 638 u16 seq_ctrl = 0; 639 __le16 fc = 0; 640 int idx; 641 642 memset(status, 0, sizeof(*status)); 643 644 band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); 645 mphy = dev->mt76.phys[band_idx]; 646 phy = mphy->priv; 647 status->phy_idx = mphy->band_idx; 648 649 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 650 return -EINVAL; 651 652 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 653 return -EINVAL; 654 655 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 656 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 657 return -EINVAL; 658 659 /* ICV error or CCMP/BIP/WPI MIC error */ 660 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 661 status->flag |= RX_FLAG_ONLY_MONITOR; 662 663 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 664 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 665 status->wcid = mt7996_rx_get_wcid(dev, idx, unicast); 666 667 if (status->wcid) { 668 struct mt7996_sta *msta; 669 670 msta = container_of(status->wcid, struct mt7996_sta, wcid); 671 spin_lock_bh(&dev->sta_poll_lock); 672 if (list_empty(&msta->poll_list)) 673 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 674 spin_unlock_bh(&dev->sta_poll_lock); 675 } 676 677 status->freq = mphy->chandef.chan->center_freq; 678 status->band = mphy->chandef.chan->band; 679 if (status->band == NL80211_BAND_5GHZ) 680 sband = &mphy->sband_5g.sband; 681 else if (status->band == NL80211_BAND_6GHZ) 682 sband = &mphy->sband_6g.sband; 683 else 684 sband = &mphy->sband_2g.sband; 685 686 if (!sband->channels) 687 return -EINVAL; 688 689 if ((rxd0 & csum_mask) == csum_mask && 690 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 691 skb->ip_summed = CHECKSUM_UNNECESSARY; 692 693 if (rxd1 & MT_RXD3_NORMAL_FCS_ERR) 694 status->flag |= RX_FLAG_FAILED_FCS_CRC; 695 696 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 697 status->flag |= RX_FLAG_MMIC_ERROR; 698 699 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 700 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 701 status->flag |= RX_FLAG_DECRYPTED; 702 status->flag |= RX_FLAG_IV_STRIPPED; 703 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 704 } 705 706 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 707 708 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 709 return -EINVAL; 710 711 rxd += 8; 712 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 713 u32 v0 = le32_to_cpu(rxd[0]); 714 u32 v2 = le32_to_cpu(rxd[2]); 715 716 fc = cpu_to_le16(FIELD_GET(MT_RXD8_FRAME_CONTROL, v0)); 717 qos_ctl = FIELD_GET(MT_RXD10_QOS_CTL, v2); 718 seq_ctrl = FIELD_GET(MT_RXD10_SEQ_CTRL, v2); 719 720 rxd += 4; 721 if ((u8 *)rxd - skb->data >= skb->len) 722 return -EINVAL; 723 } 724 725 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 726 u8 *data = (u8 *)rxd; 727 728 if (status->flag & RX_FLAG_DECRYPTED) { 729 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 730 case MT_CIPHER_AES_CCMP: 731 case MT_CIPHER_CCMP_CCX: 732 case MT_CIPHER_CCMP_256: 733 insert_ccmp_hdr = 734 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 735 fallthrough; 736 case MT_CIPHER_TKIP: 737 case MT_CIPHER_TKIP_NO_MIC: 738 case MT_CIPHER_GCMP: 739 case MT_CIPHER_GCMP_256: 740 status->iv[0] = data[5]; 741 status->iv[1] = data[4]; 742 status->iv[2] = data[3]; 743 status->iv[3] = data[2]; 744 status->iv[4] = data[1]; 745 status->iv[5] = data[0]; 746 break; 747 default: 748 break; 749 } 750 } 751 rxd += 4; 752 if ((u8 *)rxd - skb->data >= skb->len) 753 return -EINVAL; 754 } 755 756 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 757 status->timestamp = le32_to_cpu(rxd[0]); 758 status->flag |= RX_FLAG_MACTIME_START; 759 760 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 761 status->flag |= RX_FLAG_AMPDU_DETAILS; 762 763 /* all subframes of an A-MPDU have the same timestamp */ 764 if (phy->rx_ampdu_ts != status->timestamp) { 765 if (!++phy->ampdu_ref) 766 phy->ampdu_ref++; 767 } 768 phy->rx_ampdu_ts = status->timestamp; 769 770 status->ampdu_ref = phy->ampdu_ref; 771 } 772 773 rxd += 4; 774 if ((u8 *)rxd - skb->data >= skb->len) 775 return -EINVAL; 776 } 777 778 /* RXD Group 3 - P-RXV */ 779 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 780 u32 v3; 781 int ret; 782 783 rxv = rxd; 784 rxd += 4; 785 if ((u8 *)rxd - skb->data >= skb->len) 786 return -EINVAL; 787 788 v3 = le32_to_cpu(rxv[3]); 789 790 status->chains = mphy->antenna_mask; 791 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3); 792 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3); 793 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3); 794 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3); 795 796 /* RXD Group 5 - C-RXV */ 797 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 798 rxd += 24; 799 if ((u8 *)rxd - skb->data >= skb->len) 800 return -EINVAL; 801 } 802 803 ret = mt7996_mac_fill_rx_rate(dev, status, sband, rxv, &mode); 804 if (ret < 0) 805 return ret; 806 } 807 808 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 809 status->amsdu = !!amsdu_info; 810 if (status->amsdu) { 811 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 812 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 813 } 814 815 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 816 if (hdr_trans && ieee80211_has_morefrags(fc)) { 817 if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap)) 818 return -EINVAL; 819 hdr_trans = false; 820 } else { 821 int pad_start = 0; 822 823 skb_pull(skb, hdr_gap); 824 if (!hdr_trans && status->amsdu) { 825 pad_start = ieee80211_get_hdrlen_from_skb(skb); 826 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 827 /* When header translation failure is indicated, 828 * the hardware will insert an extra 2-byte field 829 * containing the data length after the protocol 830 * type field. 831 */ 832 pad_start = 12; 833 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 834 pad_start += 4; 835 else 836 pad_start = 0; 837 } 838 839 if (pad_start) { 840 memmove(skb->data + 2, skb->data, pad_start); 841 skb_pull(skb, 2); 842 } 843 } 844 845 if (!hdr_trans) { 846 struct ieee80211_hdr *hdr; 847 848 if (insert_ccmp_hdr) { 849 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 850 851 mt76_insert_ccmp_hdr(skb, key_id); 852 } 853 854 hdr = mt76_skb_get_hdr(skb); 855 fc = hdr->frame_control; 856 if (ieee80211_is_data_qos(fc)) { 857 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 858 qos_ctl = *ieee80211_get_qos_ctl(hdr); 859 } 860 } else { 861 status->flag |= RX_FLAG_8023; 862 } 863 864 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 865 mt7996_mac_decode_he_radiotap(skb, rxv, mode); 866 867 if (!status->wcid || !ieee80211_is_data_qos(fc)) 868 return 0; 869 870 status->aggr = unicast && 871 !ieee80211_is_qos_nullfunc(fc); 872 status->qos_ctl = qos_ctl; 873 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 874 875 return 0; 876 } 877 878 static void 879 mt7996_mac_write_txwi_8023(struct mt7996_dev *dev, __le32 *txwi, 880 struct sk_buff *skb, struct mt76_wcid *wcid) 881 { 882 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 883 u8 fc_type, fc_stype; 884 u16 ethertype; 885 bool wmm = false; 886 u32 val; 887 888 if (wcid->sta) { 889 struct ieee80211_sta *sta; 890 891 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 892 wmm = sta->wme; 893 } 894 895 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 896 FIELD_PREP(MT_TXD1_TID, tid); 897 898 ethertype = get_unaligned_be16(&skb->data[12]); 899 if (ethertype >= ETH_P_802_3_MIN) 900 val |= MT_TXD1_ETH_802_3; 901 902 txwi[1] |= cpu_to_le32(val); 903 904 fc_type = IEEE80211_FTYPE_DATA >> 2; 905 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 906 907 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 908 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 909 910 txwi[2] |= cpu_to_le32(val); 911 } 912 913 static void 914 mt7996_mac_write_txwi_80211(struct mt7996_dev *dev, __le32 *txwi, 915 struct sk_buff *skb, struct ieee80211_key_conf *key) 916 { 917 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 918 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 919 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 920 bool multicast = is_multicast_ether_addr(hdr->addr1); 921 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 922 __le16 fc = hdr->frame_control; 923 u8 fc_type, fc_stype; 924 u32 val; 925 926 if (ieee80211_is_action(fc) && 927 mgmt->u.action.category == WLAN_CATEGORY_BACK && 928 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) 929 tid = MT_TX_ADDBA; 930 else if (ieee80211_is_mgmt(hdr->frame_control)) 931 tid = MT_TX_NORMAL; 932 933 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 934 FIELD_PREP(MT_TXD1_HDR_INFO, 935 ieee80211_get_hdrlen_from_skb(skb) / 2) | 936 FIELD_PREP(MT_TXD1_TID, tid); 937 938 if (!ieee80211_is_data(fc) || multicast || 939 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 940 val |= MT_TXD1_FIXED_RATE; 941 942 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 943 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 944 val |= MT_TXD1_BIP; 945 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 946 } 947 948 txwi[1] |= cpu_to_le32(val); 949 950 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 951 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 952 953 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 954 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 955 956 txwi[2] |= cpu_to_le32(val); 957 958 txwi[3] |= cpu_to_le32(FIELD_PREP(MT_TXD3_BCM, multicast)); 959 if (ieee80211_is_beacon(fc)) { 960 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 961 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 962 } 963 964 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 965 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 966 967 if (ieee80211_is_back_req(hdr->frame_control)) { 968 struct ieee80211_bar *bar; 969 970 bar = (struct ieee80211_bar *)skb->data; 971 seqno = le16_to_cpu(bar->start_seq_num); 972 } 973 974 val = MT_TXD3_SN_VALID | 975 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 976 txwi[3] |= cpu_to_le32(val); 977 txwi[3] &= ~cpu_to_le32(MT_TXD3_HW_AMSDU); 978 } 979 } 980 981 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 982 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 983 struct ieee80211_key_conf *key, u32 changed) 984 { 985 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 986 struct ieee80211_vif *vif = info->control.vif; 987 struct mt76_phy *mphy = &dev->mphy; 988 u8 band_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 989 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 990 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 991 u16 tx_count = 15; 992 u32 val; 993 bool beacon = !!(changed & (BSS_CHANGED_BEACON | 994 BSS_CHANGED_BEACON_ENABLED)); 995 bool inband_disc = !!(changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | 996 BSS_CHANGED_FILS_DISCOVERY)); 997 998 if (vif) { 999 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1000 1001 omac_idx = mvif->mt76.omac_idx; 1002 wmm_idx = mvif->mt76.wmm_idx; 1003 band_idx = mvif->mt76.band_idx; 1004 } 1005 1006 mphy = mt76_dev_phy(&dev->mt76, band_idx); 1007 1008 if (inband_disc) { 1009 p_fmt = MT_TX_TYPE_FW; 1010 q_idx = MT_LMAC_ALTX0; 1011 } else if (beacon) { 1012 p_fmt = MT_TX_TYPE_FW; 1013 q_idx = MT_LMAC_BCN0; 1014 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 1015 p_fmt = MT_TX_TYPE_CT; 1016 q_idx = MT_LMAC_ALTX0; 1017 } else { 1018 p_fmt = MT_TX_TYPE_CT; 1019 q_idx = wmm_idx * MT7996_MAX_WMM_SETS + 1020 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 1021 } 1022 1023 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 1024 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 1025 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 1026 txwi[0] = cpu_to_le32(val); 1027 1028 val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 1029 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 1030 1031 if (band_idx) 1032 val |= FIELD_PREP(MT_TXD1_TGID, band_idx); 1033 1034 txwi[1] = cpu_to_le32(val); 1035 txwi[2] = 0; 1036 1037 val = MT_TXD3_SW_POWER_MGMT | 1038 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 1039 if (key) 1040 val |= MT_TXD3_PROTECT_FRAME; 1041 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1042 val |= MT_TXD3_NO_ACK; 1043 if (wcid->amsdu) 1044 val |= MT_TXD3_HW_AMSDU; 1045 1046 txwi[3] = cpu_to_le32(val); 1047 txwi[4] = 0; 1048 1049 val = FIELD_PREP(MT_TXD5_PID, pid); 1050 if (pid >= MT_PACKET_ID_FIRST) 1051 val |= MT_TXD5_TX_STATUS_HOST; 1052 txwi[5] = cpu_to_le32(val); 1053 1054 val = MT_TXD6_DIS_MAT | MT_TXD6_DAS | 1055 FIELD_PREP(MT_TXD6_MSDU_CNT, 1); 1056 txwi[6] = cpu_to_le32(val); 1057 txwi[7] = 0; 1058 1059 if (is_8023) 1060 mt7996_mac_write_txwi_8023(dev, txwi, skb, wcid); 1061 else 1062 mt7996_mac_write_txwi_80211(dev, txwi, skb, key); 1063 1064 if (txwi[1] & cpu_to_le32(MT_TXD1_FIXED_RATE)) { 1065 /* Fixed rata is available just for 802.11 txd */ 1066 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1067 bool multicast = is_multicast_ether_addr(hdr->addr1); 1068 u16 rate = mt76_connac2_mac_tx_rate_val(mphy, vif, beacon, 1069 multicast); 1070 1071 /* fix to bw 20 */ 1072 val = MT_TXD6_FIXED_BW | 1073 FIELD_PREP(MT_TXD6_BW, 0) | 1074 FIELD_PREP(MT_TXD6_TX_RATE, rate); 1075 1076 txwi[6] |= cpu_to_le32(val); 1077 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1078 } 1079 } 1080 1081 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1082 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1083 struct ieee80211_sta *sta, 1084 struct mt76_tx_info *tx_info) 1085 { 1086 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 1087 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1088 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1089 struct ieee80211_key_conf *key = info->control.hw_key; 1090 struct ieee80211_vif *vif = info->control.vif; 1091 struct mt76_connac_txp_common *txp; 1092 struct mt76_txwi_cache *t; 1093 int id, i, pid, nbuf = tx_info->nbuf - 1; 1094 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1095 u8 *txwi = (u8 *)txwi_ptr; 1096 1097 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1098 return -EINVAL; 1099 1100 if (!wcid) 1101 wcid = &dev->mt76.global_wcid; 1102 1103 if (sta) { 1104 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1105 1106 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 1107 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 1108 msta->jiffies = jiffies; 1109 } 1110 } 1111 1112 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 1113 t->skb = tx_info->skb; 1114 1115 id = mt76_token_consume(mdev, &t); 1116 if (id < 0) 1117 return id; 1118 1119 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1120 memset(txwi_ptr, 0, MT_TXD_SIZE); 1121 /* Transmit non qos data by 802.11 header and need to fill txd by host*/ 1122 if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1123 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, pid, 1124 key, 0); 1125 1126 txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1127 for (i = 0; i < nbuf; i++) { 1128 txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1129 txp->fw.len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 1130 } 1131 txp->fw.nbuf = nbuf; 1132 1133 txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); 1134 1135 if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1136 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); 1137 1138 if (!key) 1139 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1140 1141 if (!is_8023 && ieee80211_is_mgmt(hdr->frame_control)) 1142 txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1143 1144 if (vif) { 1145 struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1146 1147 txp->fw.bss_idx = mvif->mt76.idx; 1148 } 1149 1150 txp->fw.token = cpu_to_le16(id); 1151 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 1152 txp->fw.rept_wds_wcid = cpu_to_le16(wcid->idx); 1153 else 1154 txp->fw.rept_wds_wcid = cpu_to_le16(0xfff); 1155 tx_info->skb = DMA_DUMMY_DATA; 1156 1157 /* pass partial skb header to fw */ 1158 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1159 tx_info->buf[1].skip_unmap = true; 1160 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1161 1162 return 0; 1163 } 1164 1165 static void 1166 mt7996_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1167 { 1168 struct mt7996_sta *msta; 1169 u16 fc, tid; 1170 u32 val; 1171 1172 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 1173 return; 1174 1175 tid = le32_get_bits(txwi[1], MT_TXD1_TID); 1176 if (tid >= 6) /* skip VO queue */ 1177 return; 1178 1179 val = le32_to_cpu(txwi[2]); 1180 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1181 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1182 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1183 return; 1184 1185 msta = (struct mt7996_sta *)sta->drv_priv; 1186 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1187 ieee80211_start_tx_ba_session(sta, tid, 0); 1188 } 1189 1190 static void 1191 mt7996_txwi_free(struct mt7996_dev *dev, struct mt76_txwi_cache *t, 1192 struct ieee80211_sta *sta, struct list_head *free_list) 1193 { 1194 struct mt76_dev *mdev = &dev->mt76; 1195 struct mt76_wcid *wcid; 1196 __le32 *txwi; 1197 u16 wcid_idx; 1198 1199 mt76_connac_txp_skb_unmap(mdev, t); 1200 if (!t->skb) 1201 goto out; 1202 1203 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1204 if (sta) { 1205 wcid = (struct mt76_wcid *)sta->drv_priv; 1206 wcid_idx = wcid->idx; 1207 1208 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1209 mt7996_tx_check_aggr(sta, txwi); 1210 } else { 1211 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); 1212 } 1213 1214 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1215 1216 out: 1217 t->skb = NULL; 1218 mt76_put_txwi(mdev, t); 1219 } 1220 1221 static void 1222 mt7996_mac_tx_free(struct mt7996_dev *dev, void *data, int len) 1223 { 1224 __le32 *tx_free = (__le32 *)data, *cur_info; 1225 struct mt76_dev *mdev = &dev->mt76; 1226 struct mt76_phy *phy2 = mdev->phys[MT_BAND1]; 1227 struct mt76_phy *phy3 = mdev->phys[MT_BAND2]; 1228 struct mt76_txwi_cache *txwi; 1229 struct ieee80211_sta *sta = NULL; 1230 LIST_HEAD(free_list); 1231 struct sk_buff *skb, *tmp; 1232 void *end = data + len; 1233 bool wake = false; 1234 u16 total, count = 0; 1235 1236 /* clean DMA queues and unmap buffers first */ 1237 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1238 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1239 if (phy2) { 1240 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_PSD], false); 1241 mt76_queue_tx_cleanup(dev, phy2->q_tx[MT_TXQ_BE], false); 1242 } 1243 if (phy3) { 1244 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_PSD], false); 1245 mt76_queue_tx_cleanup(dev, phy3->q_tx[MT_TXQ_BE], false); 1246 } 1247 1248 if (WARN_ON_ONCE(le32_get_bits(tx_free[1], MT_TXFREE1_VER) < 4)) 1249 return; 1250 1251 total = le32_get_bits(tx_free[0], MT_TXFREE0_MSDU_CNT); 1252 for (cur_info = &tx_free[2]; count < total; cur_info++) { 1253 u32 msdu, info; 1254 u8 i; 1255 1256 if (WARN_ON_ONCE((void *)cur_info >= end)) 1257 return; 1258 /* 1'b1: new wcid pair. 1259 * 1'b0: msdu_id with the same 'wcid pair' as above. 1260 */ 1261 info = le32_to_cpu(*cur_info); 1262 if (info & MT_TXFREE_INFO_PAIR) { 1263 struct mt7996_sta *msta; 1264 struct mt76_wcid *wcid; 1265 u16 idx; 1266 1267 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); 1268 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1269 sta = wcid_to_sta(wcid); 1270 if (!sta) 1271 continue; 1272 1273 msta = container_of(wcid, struct mt7996_sta, wcid); 1274 spin_lock_bh(&dev->sta_poll_lock); 1275 if (list_empty(&msta->poll_list)) 1276 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1277 spin_unlock_bh(&dev->sta_poll_lock); 1278 continue; 1279 } 1280 1281 if (info & MT_TXFREE_INFO_HEADER) 1282 continue; 1283 1284 for (i = 0; i < 2; i++) { 1285 msdu = (info >> (15 * i)) & MT_TXFREE_INFO_MSDU_ID; 1286 if (msdu == MT_TXFREE_INFO_MSDU_ID) 1287 continue; 1288 1289 count++; 1290 txwi = mt76_token_release(mdev, msdu, &wake); 1291 if (!txwi) 1292 continue; 1293 1294 mt7996_txwi_free(dev, txwi, sta, &free_list); 1295 } 1296 } 1297 1298 mt7996_mac_sta_poll(dev); 1299 1300 if (wake) 1301 mt76_set_tx_blocked(&dev->mt76, false); 1302 1303 mt76_worker_schedule(&dev->mt76.tx_worker); 1304 1305 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1306 skb_list_del_init(skb); 1307 napi_consume_skb(skb, 1); 1308 } 1309 } 1310 1311 static bool 1312 mt7996_mac_add_txs_skb(struct mt7996_dev *dev, struct mt76_wcid *wcid, int pid, 1313 __le32 *txs_data, struct mt76_sta_stats *stats) 1314 { 1315 struct ieee80211_supported_band *sband; 1316 struct mt76_dev *mdev = &dev->mt76; 1317 struct mt76_phy *mphy; 1318 struct ieee80211_tx_info *info; 1319 struct sk_buff_head list; 1320 struct rate_info rate = {}; 1321 struct sk_buff *skb; 1322 bool cck = false; 1323 u32 txrate, txs, mode, stbc; 1324 1325 mt76_tx_status_lock(mdev, &list); 1326 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1327 if (!skb) 1328 goto out_no_skb; 1329 1330 txs = le32_to_cpu(txs_data[0]); 1331 1332 info = IEEE80211_SKB_CB(skb); 1333 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1334 info->flags |= IEEE80211_TX_STAT_ACK; 1335 1336 info->status.ampdu_len = 1; 1337 info->status.ampdu_ack_len = !!(info->flags & 1338 IEEE80211_TX_STAT_ACK); 1339 1340 info->status.rates[0].idx = -1; 1341 1342 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1343 1344 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1345 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1346 stbc = le32_get_bits(txs_data[3], MT_TXS3_RATE_STBC); 1347 1348 if (stbc && rate.nss > 1) 1349 rate.nss >>= 1; 1350 1351 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1352 stats->tx_nss[rate.nss - 1]++; 1353 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1354 stats->tx_mcs[rate.mcs]++; 1355 1356 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1357 switch (mode) { 1358 case MT_PHY_TYPE_CCK: 1359 cck = true; 1360 fallthrough; 1361 case MT_PHY_TYPE_OFDM: 1362 mphy = mt76_dev_phy(mdev, wcid->phy_idx); 1363 1364 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1365 sband = &mphy->sband_5g.sband; 1366 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 1367 sband = &mphy->sband_6g.sband; 1368 else 1369 sband = &mphy->sband_2g.sband; 1370 1371 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1372 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1373 break; 1374 case MT_PHY_TYPE_HT: 1375 case MT_PHY_TYPE_HT_GF: 1376 if (rate.mcs > 31) 1377 goto out; 1378 1379 rate.flags = RATE_INFO_FLAGS_MCS; 1380 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1381 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1382 break; 1383 case MT_PHY_TYPE_VHT: 1384 if (rate.mcs > 9) 1385 goto out; 1386 1387 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1388 break; 1389 case MT_PHY_TYPE_HE_SU: 1390 case MT_PHY_TYPE_HE_EXT_SU: 1391 case MT_PHY_TYPE_HE_TB: 1392 case MT_PHY_TYPE_HE_MU: 1393 if (rate.mcs > 11) 1394 goto out; 1395 1396 rate.he_gi = wcid->rate.he_gi; 1397 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1398 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1399 break; 1400 case MT_PHY_TYPE_EHT_SU: 1401 case MT_PHY_TYPE_EHT_TRIG: 1402 case MT_PHY_TYPE_EHT_MU: 1403 if (rate.mcs > 13) 1404 goto out; 1405 1406 rate.eht_gi = wcid->rate.eht_gi; 1407 rate.flags = RATE_INFO_FLAGS_EHT_MCS; 1408 break; 1409 default: 1410 goto out; 1411 } 1412 1413 stats->tx_mode[mode]++; 1414 1415 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1416 case IEEE80211_STA_RX_BW_320: 1417 rate.bw = RATE_INFO_BW_320; 1418 stats->tx_bw[4]++; 1419 break; 1420 case IEEE80211_STA_RX_BW_160: 1421 rate.bw = RATE_INFO_BW_160; 1422 stats->tx_bw[3]++; 1423 break; 1424 case IEEE80211_STA_RX_BW_80: 1425 rate.bw = RATE_INFO_BW_80; 1426 stats->tx_bw[2]++; 1427 break; 1428 case IEEE80211_STA_RX_BW_40: 1429 rate.bw = RATE_INFO_BW_40; 1430 stats->tx_bw[1]++; 1431 break; 1432 default: 1433 rate.bw = RATE_INFO_BW_20; 1434 stats->tx_bw[0]++; 1435 break; 1436 } 1437 wcid->rate = rate; 1438 1439 out: 1440 mt76_tx_status_skb_done(mdev, skb, &list); 1441 1442 out_no_skb: 1443 mt76_tx_status_unlock(mdev, &list); 1444 1445 return !!skb; 1446 } 1447 1448 static void mt7996_mac_add_txs(struct mt7996_dev *dev, void *data) 1449 { 1450 struct mt7996_sta *msta = NULL; 1451 struct mt76_wcid *wcid; 1452 __le32 *txs_data = data; 1453 u16 wcidx; 1454 u8 pid; 1455 1456 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1) 1457 return; 1458 1459 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1460 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1461 1462 if (pid < MT_PACKET_ID_FIRST) 1463 return; 1464 1465 if (wcidx >= mt7996_wtbl_size(dev)) 1466 return; 1467 1468 rcu_read_lock(); 1469 1470 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1471 if (!wcid) 1472 goto out; 1473 1474 msta = container_of(wcid, struct mt7996_sta, wcid); 1475 1476 mt7996_mac_add_txs_skb(dev, wcid, pid, txs_data, &msta->stats); 1477 1478 if (!wcid->sta) 1479 goto out; 1480 1481 spin_lock_bh(&dev->sta_poll_lock); 1482 if (list_empty(&msta->poll_list)) 1483 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1484 spin_unlock_bh(&dev->sta_poll_lock); 1485 1486 out: 1487 rcu_read_unlock(); 1488 } 1489 1490 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len) 1491 { 1492 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1493 __le32 *rxd = (__le32 *)data; 1494 __le32 *end = (__le32 *)&rxd[len / 4]; 1495 enum rx_pkt_type type; 1496 1497 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1498 if (type != PKT_TYPE_NORMAL) { 1499 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1500 1501 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1502 MT_RXD0_SW_PKT_TYPE_FRAME)) 1503 return true; 1504 } 1505 1506 switch (type) { 1507 case PKT_TYPE_TXRX_NOTIFY: 1508 mt7996_mac_tx_free(dev, data, len); 1509 return false; 1510 case PKT_TYPE_TXS: 1511 for (rxd += 4; rxd + 8 <= end; rxd += 8) 1512 mt7996_mac_add_txs(dev, rxd); 1513 return false; 1514 case PKT_TYPE_RX_FW_MONITOR: 1515 mt7996_debugfs_rx_fw_monitor(dev, data, len); 1516 return false; 1517 default: 1518 return true; 1519 } 1520 } 1521 1522 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1523 struct sk_buff *skb, u32 *info) 1524 { 1525 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1526 __le32 *rxd = (__le32 *)skb->data; 1527 __le32 *end = (__le32 *)&skb->data[skb->len]; 1528 enum rx_pkt_type type; 1529 1530 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1531 if (type != PKT_TYPE_NORMAL) { 1532 u32 sw_type = le32_get_bits(rxd[0], MT_RXD0_SW_PKT_TYPE_MASK); 1533 1534 if (unlikely((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == 1535 MT_RXD0_SW_PKT_TYPE_FRAME)) 1536 type = PKT_TYPE_NORMAL; 1537 } 1538 1539 switch (type) { 1540 case PKT_TYPE_TXRX_NOTIFY: 1541 mt7996_mac_tx_free(dev, skb->data, skb->len); 1542 napi_consume_skb(skb, 1); 1543 break; 1544 case PKT_TYPE_RX_EVENT: 1545 mt7996_mcu_rx_event(dev, skb); 1546 break; 1547 case PKT_TYPE_TXS: 1548 for (rxd += 4; rxd + 8 <= end; rxd += 8) 1549 mt7996_mac_add_txs(dev, rxd); 1550 dev_kfree_skb(skb); 1551 break; 1552 case PKT_TYPE_RX_FW_MONITOR: 1553 mt7996_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1554 dev_kfree_skb(skb); 1555 break; 1556 case PKT_TYPE_NORMAL: 1557 if (!mt7996_mac_fill_rx(dev, skb)) { 1558 mt76_rx(&dev->mt76, q, skb); 1559 return; 1560 } 1561 fallthrough; 1562 default: 1563 dev_kfree_skb(skb); 1564 break; 1565 } 1566 } 1567 1568 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1569 { 1570 struct mt7996_dev *dev = phy->dev; 1571 u32 reg = MT_WF_PHYRX_BAND_RX_CTRL1(phy->mt76->band_idx); 1572 1573 mt76_clear(dev, reg, MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN); 1574 mt76_set(dev, reg, BIT(11) | BIT(9)); 1575 } 1576 1577 void mt7996_mac_reset_counters(struct mt7996_phy *phy) 1578 { 1579 struct mt7996_dev *dev = phy->dev; 1580 u8 band_idx = phy->mt76->band_idx; 1581 int i; 1582 1583 for (i = 0; i < 16; i++) 1584 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 1585 1586 phy->mt76->survey_time = ktime_get_boottime(); 1587 1588 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1589 1590 /* reset airtime counters */ 1591 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(band_idx), 1592 MT_WF_RMAC_MIB_RXTIME_CLR); 1593 1594 mt7996_mcu_get_chan_mib_info(phy, true); 1595 } 1596 1597 void mt7996_mac_set_timing(struct mt7996_phy *phy) 1598 { 1599 s16 coverage_class = phy->coverage_class; 1600 struct mt7996_dev *dev = phy->dev; 1601 struct mt7996_phy *phy2 = mt7996_phy2(dev); 1602 struct mt7996_phy *phy3 = mt7996_phy3(dev); 1603 u32 val, reg_offset; 1604 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1605 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1606 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1607 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1608 u8 band_idx = phy->mt76->band_idx; 1609 int offset; 1610 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1611 1612 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1613 return; 1614 1615 if (phy2) 1616 coverage_class = max_t(s16, dev->phy.coverage_class, 1617 phy2->coverage_class); 1618 1619 if (phy3) 1620 coverage_class = max_t(s16, coverage_class, 1621 phy3->coverage_class); 1622 1623 mt76_set(dev, MT_ARB_SCR(band_idx), 1624 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1625 udelay(1); 1626 1627 offset = 3 * coverage_class; 1628 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1629 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1630 1631 mt76_wr(dev, MT_TMAC_CDTR(band_idx), cck + reg_offset); 1632 mt76_wr(dev, MT_TMAC_ODTR(band_idx), ofdm + reg_offset); 1633 mt76_wr(dev, MT_TMAC_ICR0(band_idx), 1634 FIELD_PREP(MT_IFS_EIFS_OFDM, a_band ? 84 : 78) | 1635 FIELD_PREP(MT_IFS_RIFS, 2) | 1636 FIELD_PREP(MT_IFS_SIFS, 10) | 1637 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1638 1639 if (!a_band) 1640 mt76_wr(dev, MT_TMAC_ICR1(band_idx), 1641 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1642 1643 if (phy->slottime < 20 || a_band) 1644 val = MT7996_CFEND_RATE_DEFAULT; 1645 else 1646 val = MT7996_CFEND_RATE_11B; 1647 1648 mt76_rmw_field(dev, MT_RATE_HRCR0(band_idx), MT_RATE_HRCR0_CFEND_RATE, val); 1649 mt76_clear(dev, MT_ARB_SCR(band_idx), 1650 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1651 } 1652 1653 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band) 1654 { 1655 mt76_set(dev, MT_WF_PHYRX_CSD_BAND_RXTD12(band), 1656 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY | 1657 MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR); 1658 1659 mt76_set(dev, MT_WF_PHYRX_BAND_RX_CTRL1(band), 1660 FIELD_PREP(MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN, 0x5)); 1661 } 1662 1663 static u8 1664 mt7996_phy_get_nf(struct mt7996_phy *phy, u8 band_idx) 1665 { 1666 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1667 struct mt7996_dev *dev = phy->dev; 1668 u32 val, sum = 0, n = 0; 1669 int ant, i; 1670 1671 for (ant = 0; ant < hweight8(phy->mt76->antenna_mask); ant++) { 1672 u32 reg = MT_WF_PHYRX_CSD_IRPI(band_idx, ant); 1673 1674 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1675 val = mt76_rr(dev, reg); 1676 sum += val * nf_power[i]; 1677 n += val; 1678 } 1679 } 1680 1681 return n ? sum / n : 0; 1682 } 1683 1684 void mt7996_update_channel(struct mt76_phy *mphy) 1685 { 1686 struct mt7996_phy *phy = (struct mt7996_phy *)mphy->priv; 1687 struct mt76_channel_state *state = mphy->chan_state; 1688 int nf; 1689 1690 mt7996_mcu_get_chan_mib_info(phy, false); 1691 1692 nf = mt7996_phy_get_nf(phy, mphy->band_idx); 1693 if (!phy->noise) 1694 phy->noise = nf << 4; 1695 else if (nf) 1696 phy->noise += nf - (phy->noise >> 4); 1697 1698 state->noise = -(phy->noise >> 4); 1699 } 1700 1701 static bool 1702 mt7996_wait_reset_state(struct mt7996_dev *dev, u32 state) 1703 { 1704 bool ret; 1705 1706 ret = wait_event_timeout(dev->reset_wait, 1707 (READ_ONCE(dev->reset_state) & state), 1708 MT7996_RESET_TIMEOUT); 1709 1710 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1711 return ret; 1712 } 1713 1714 static void 1715 mt7996_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1716 { 1717 struct ieee80211_hw *hw = priv; 1718 1719 switch (vif->type) { 1720 case NL80211_IFTYPE_MESH_POINT: 1721 case NL80211_IFTYPE_ADHOC: 1722 case NL80211_IFTYPE_AP: 1723 mt7996_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1724 break; 1725 default: 1726 break; 1727 } 1728 } 1729 1730 static void 1731 mt7996_update_beacons(struct mt7996_dev *dev) 1732 { 1733 struct mt76_phy *phy2, *phy3; 1734 1735 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1736 IEEE80211_IFACE_ITER_RESUME_ALL, 1737 mt7996_update_vif_beacon, dev->mt76.hw); 1738 1739 phy2 = dev->mt76.phys[MT_BAND1]; 1740 if (!phy2) 1741 return; 1742 1743 ieee80211_iterate_active_interfaces(phy2->hw, 1744 IEEE80211_IFACE_ITER_RESUME_ALL, 1745 mt7996_update_vif_beacon, phy2->hw); 1746 1747 phy3 = dev->mt76.phys[MT_BAND2]; 1748 if (!phy3) 1749 return; 1750 1751 ieee80211_iterate_active_interfaces(phy3->hw, 1752 IEEE80211_IFACE_ITER_RESUME_ALL, 1753 mt7996_update_vif_beacon, phy3->hw); 1754 } 1755 1756 static void 1757 mt7996_dma_reset(struct mt7996_dev *dev) 1758 { 1759 struct mt76_phy *phy2 = dev->mt76.phys[MT_BAND1]; 1760 struct mt76_phy *phy3 = dev->mt76.phys[MT_BAND2]; 1761 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 1762 int i; 1763 1764 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 1765 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1766 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1767 1768 if (dev->hif2) 1769 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1770 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1771 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1772 1773 usleep_range(1000, 2000); 1774 1775 for (i = 0; i < __MT_TXQ_MAX; i++) { 1776 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 1777 if (phy2) 1778 mt76_queue_tx_cleanup(dev, phy2->q_tx[i], true); 1779 if (phy3) 1780 mt76_queue_tx_cleanup(dev, phy3->q_tx[i], true); 1781 } 1782 1783 for (i = 0; i < __MT_MCUQ_MAX; i++) 1784 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); 1785 1786 mt76_for_each_q_rx(&dev->mt76, i) 1787 mt76_queue_rx_reset(dev, i); 1788 1789 mt76_tx_status_check(&dev->mt76, true); 1790 1791 /* re-init prefetch settings after reset */ 1792 mt7996_dma_prefetch(dev); 1793 1794 mt76_set(dev, MT_WFDMA0_GLO_CFG, 1795 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1796 1797 if (dev->hif2) 1798 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1799 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1800 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1801 } 1802 1803 void mt7996_tx_token_put(struct mt7996_dev *dev) 1804 { 1805 struct mt76_txwi_cache *txwi; 1806 int id; 1807 1808 spin_lock_bh(&dev->mt76.token_lock); 1809 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1810 mt7996_txwi_free(dev, txwi, NULL, NULL); 1811 dev->mt76.token_count--; 1812 } 1813 spin_unlock_bh(&dev->mt76.token_lock); 1814 idr_destroy(&dev->mt76.token); 1815 } 1816 1817 /* system error recovery */ 1818 void mt7996_mac_reset_work(struct work_struct *work) 1819 { 1820 struct mt7996_phy *phy2, *phy3; 1821 struct mt7996_dev *dev; 1822 int i; 1823 1824 dev = container_of(work, struct mt7996_dev, reset_work); 1825 phy2 = mt7996_phy2(dev); 1826 phy3 = mt7996_phy3(dev); 1827 1828 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA)) 1829 return; 1830 1831 ieee80211_stop_queues(mt76_hw(dev)); 1832 if (phy2) 1833 ieee80211_stop_queues(phy2->mt76->hw); 1834 if (phy3) 1835 ieee80211_stop_queues(phy3->mt76->hw); 1836 1837 set_bit(MT76_RESET, &dev->mphy.state); 1838 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1839 wake_up(&dev->mt76.mcu.wait); 1840 cancel_delayed_work_sync(&dev->mphy.mac_work); 1841 if (phy2) { 1842 set_bit(MT76_RESET, &phy2->mt76->state); 1843 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1844 } 1845 if (phy3) { 1846 set_bit(MT76_RESET, &phy3->mt76->state); 1847 cancel_delayed_work_sync(&phy3->mt76->mac_work); 1848 } 1849 mt76_worker_disable(&dev->mt76.tx_worker); 1850 mt76_for_each_q_rx(&dev->mt76, i) 1851 napi_disable(&dev->mt76.napi[i]); 1852 napi_disable(&dev->mt76.tx_napi); 1853 1854 mutex_lock(&dev->mt76.mutex); 1855 1856 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1857 1858 if (mt7996_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1859 mt7996_dma_reset(dev); 1860 1861 mt7996_tx_token_put(dev); 1862 idr_init(&dev->mt76.token); 1863 1864 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1865 mt7996_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1866 } 1867 1868 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1869 clear_bit(MT76_RESET, &dev->mphy.state); 1870 if (phy2) 1871 clear_bit(MT76_RESET, &phy2->mt76->state); 1872 if (phy3) 1873 clear_bit(MT76_RESET, &phy3->mt76->state); 1874 1875 local_bh_disable(); 1876 mt76_for_each_q_rx(&dev->mt76, i) { 1877 napi_enable(&dev->mt76.napi[i]); 1878 napi_schedule(&dev->mt76.napi[i]); 1879 } 1880 local_bh_enable(); 1881 1882 tasklet_schedule(&dev->irq_tasklet); 1883 1884 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1885 mt7996_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1886 1887 mt76_worker_enable(&dev->mt76.tx_worker); 1888 1889 local_bh_disable(); 1890 napi_enable(&dev->mt76.tx_napi); 1891 napi_schedule(&dev->mt76.tx_napi); 1892 local_bh_enable(); 1893 1894 ieee80211_wake_queues(mt76_hw(dev)); 1895 if (phy2) 1896 ieee80211_wake_queues(phy2->mt76->hw); 1897 if (phy3) 1898 ieee80211_wake_queues(phy3->mt76->hw); 1899 1900 mutex_unlock(&dev->mt76.mutex); 1901 1902 mt7996_update_beacons(dev); 1903 1904 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1905 MT7996_WATCHDOG_TIME); 1906 if (phy2) 1907 ieee80211_queue_delayed_work(phy2->mt76->hw, 1908 &phy2->mt76->mac_work, 1909 MT7996_WATCHDOG_TIME); 1910 if (phy3) 1911 ieee80211_queue_delayed_work(phy3->mt76->hw, 1912 &phy3->mt76->mac_work, 1913 MT7996_WATCHDOG_TIME); 1914 } 1915 1916 void mt7996_mac_update_stats(struct mt7996_phy *phy) 1917 { 1918 struct mt7996_dev *dev = phy->dev; 1919 struct mib_stats *mib = &phy->mib; 1920 u8 band_idx = phy->mt76->band_idx; 1921 u32 cnt; 1922 int i; 1923 1924 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); 1925 mib->fcs_err_cnt += cnt; 1926 1927 cnt = mt76_rr(dev, MT_MIB_RSCR33(band_idx)); 1928 mib->rx_fifo_full_cnt += cnt; 1929 1930 cnt = mt76_rr(dev, MT_MIB_RSCR31(band_idx)); 1931 mib->rx_mpdu_cnt += cnt; 1932 1933 cnt = mt76_rr(dev, MT_MIB_SDR6(band_idx)); 1934 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1935 1936 cnt = mt76_rr(dev, MT_MIB_RVSR0(band_idx)); 1937 mib->rx_vector_mismatch_cnt += cnt; 1938 1939 cnt = mt76_rr(dev, MT_MIB_RSCR35(band_idx)); 1940 mib->rx_delimiter_fail_cnt += cnt; 1941 1942 cnt = mt76_rr(dev, MT_MIB_RSCR36(band_idx)); 1943 mib->rx_len_mismatch_cnt += cnt; 1944 1945 cnt = mt76_rr(dev, MT_MIB_TSCR0(band_idx)); 1946 mib->tx_ampdu_cnt += cnt; 1947 1948 cnt = mt76_rr(dev, MT_MIB_TSCR2(band_idx)); 1949 mib->tx_stop_q_empty_cnt += cnt; 1950 1951 cnt = mt76_rr(dev, MT_MIB_TSCR3(band_idx)); 1952 mib->tx_mpdu_attempts_cnt += cnt; 1953 1954 cnt = mt76_rr(dev, MT_MIB_TSCR4(band_idx)); 1955 mib->tx_mpdu_success_cnt += cnt; 1956 1957 cnt = mt76_rr(dev, MT_MIB_RSCR27(band_idx)); 1958 mib->rx_ampdu_cnt += cnt; 1959 1960 cnt = mt76_rr(dev, MT_MIB_RSCR28(band_idx)); 1961 mib->rx_ampdu_bytes_cnt += cnt; 1962 1963 cnt = mt76_rr(dev, MT_MIB_RSCR29(band_idx)); 1964 mib->rx_ampdu_valid_subframe_cnt += cnt; 1965 1966 cnt = mt76_rr(dev, MT_MIB_RSCR30(band_idx)); 1967 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1968 1969 cnt = mt76_rr(dev, MT_MIB_SDR27(band_idx)); 1970 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT, cnt); 1971 1972 cnt = mt76_rr(dev, MT_MIB_SDR28(band_idx)); 1973 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT, cnt); 1974 1975 cnt = mt76_rr(dev, MT_UMIB_RPDCR(band_idx)); 1976 mib->rx_pfdrop_cnt += cnt; 1977 1978 cnt = mt76_rr(dev, MT_MIB_RVSR1(band_idx)); 1979 mib->rx_vec_queue_overflow_drop_cnt += cnt; 1980 1981 cnt = mt76_rr(dev, MT_MIB_TSCR1(band_idx)); 1982 mib->rx_ba_cnt += cnt; 1983 1984 cnt = mt76_rr(dev, MT_MIB_BSCR0(band_idx)); 1985 mib->tx_bf_ebf_ppdu_cnt += cnt; 1986 1987 cnt = mt76_rr(dev, MT_MIB_BSCR1(band_idx)); 1988 mib->tx_bf_ibf_ppdu_cnt += cnt; 1989 1990 cnt = mt76_rr(dev, MT_MIB_BSCR2(band_idx)); 1991 mib->tx_mu_bf_cnt += cnt; 1992 1993 cnt = mt76_rr(dev, MT_MIB_TSCR5(band_idx)); 1994 mib->tx_mu_mpdu_cnt += cnt; 1995 1996 cnt = mt76_rr(dev, MT_MIB_TSCR6(band_idx)); 1997 mib->tx_mu_acked_mpdu_cnt += cnt; 1998 1999 cnt = mt76_rr(dev, MT_MIB_TSCR7(band_idx)); 2000 mib->tx_su_acked_mpdu_cnt += cnt; 2001 2002 cnt = mt76_rr(dev, MT_MIB_BSCR3(band_idx)); 2003 mib->tx_bf_rx_fb_ht_cnt += cnt; 2004 mib->tx_bf_rx_fb_all_cnt += cnt; 2005 2006 cnt = mt76_rr(dev, MT_MIB_BSCR4(band_idx)); 2007 mib->tx_bf_rx_fb_vht_cnt += cnt; 2008 mib->tx_bf_rx_fb_all_cnt += cnt; 2009 2010 cnt = mt76_rr(dev, MT_MIB_BSCR5(band_idx)); 2011 mib->tx_bf_rx_fb_he_cnt += cnt; 2012 mib->tx_bf_rx_fb_all_cnt += cnt; 2013 2014 cnt = mt76_rr(dev, MT_MIB_BSCR6(band_idx)); 2015 mib->tx_bf_rx_fb_eht_cnt += cnt; 2016 mib->tx_bf_rx_fb_all_cnt += cnt; 2017 2018 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(band_idx)); 2019 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2020 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2021 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2022 2023 cnt = mt76_rr(dev, MT_MIB_BSCR7(band_idx)); 2024 mib->tx_bf_fb_trig_cnt += cnt; 2025 2026 cnt = mt76_rr(dev, MT_MIB_BSCR17(band_idx)); 2027 mib->tx_bf_fb_cpl_cnt += cnt; 2028 2029 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2030 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2031 mib->tx_amsdu[i] += cnt; 2032 mib->tx_amsdu_cnt += cnt; 2033 } 2034 2035 /* rts count */ 2036 cnt = mt76_rr(dev, MT_MIB_BTSCR5(band_idx)); 2037 mib->rts_cnt += cnt; 2038 2039 /* rts retry count */ 2040 cnt = mt76_rr(dev, MT_MIB_BTSCR6(band_idx)); 2041 mib->rts_retries_cnt += cnt; 2042 2043 /* ba miss count */ 2044 cnt = mt76_rr(dev, MT_MIB_BTSCR0(band_idx)); 2045 mib->ba_miss_cnt += cnt; 2046 2047 /* ack fail count */ 2048 cnt = mt76_rr(dev, MT_MIB_BFTFCR(band_idx)); 2049 mib->ack_fail_cnt += cnt; 2050 2051 for (i = 0; i < 16; i++) { 2052 cnt = mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); 2053 phy->mt76->aggr_stats[i] += cnt; 2054 } 2055 } 2056 2057 void mt7996_mac_sta_rc_work(struct work_struct *work) 2058 { 2059 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, rc_work); 2060 struct ieee80211_sta *sta; 2061 struct ieee80211_vif *vif; 2062 struct mt7996_sta *msta; 2063 u32 changed; 2064 LIST_HEAD(list); 2065 2066 spin_lock_bh(&dev->sta_poll_lock); 2067 list_splice_init(&dev->sta_rc_list, &list); 2068 2069 while (!list_empty(&list)) { 2070 msta = list_first_entry(&list, struct mt7996_sta, rc_list); 2071 list_del_init(&msta->rc_list); 2072 changed = msta->changed; 2073 msta->changed = 0; 2074 spin_unlock_bh(&dev->sta_poll_lock); 2075 2076 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2077 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2078 2079 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2080 IEEE80211_RC_NSS_CHANGED | 2081 IEEE80211_RC_BW_CHANGED)) 2082 mt7996_mcu_add_rate_ctrl(dev, vif, sta, true); 2083 2084 /* TODO: smps change */ 2085 2086 spin_lock_bh(&dev->sta_poll_lock); 2087 } 2088 2089 spin_unlock_bh(&dev->sta_poll_lock); 2090 } 2091 2092 void mt7996_mac_work(struct work_struct *work) 2093 { 2094 struct mt7996_phy *phy; 2095 struct mt76_phy *mphy; 2096 2097 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2098 mac_work.work); 2099 phy = mphy->priv; 2100 2101 mutex_lock(&mphy->dev->mutex); 2102 2103 mt76_update_survey(mphy); 2104 if (++mphy->mac_work_count == 5) { 2105 mphy->mac_work_count = 0; 2106 2107 mt7996_mac_update_stats(phy); 2108 } 2109 2110 mutex_unlock(&mphy->dev->mutex); 2111 2112 mt76_tx_status_check(mphy->dev, false); 2113 2114 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2115 MT7996_WATCHDOG_TIME); 2116 } 2117 2118 static void mt7996_dfs_stop_radar_detector(struct mt7996_phy *phy) 2119 { 2120 struct mt7996_dev *dev = phy->dev; 2121 2122 if (phy->rdd_state & BIT(0)) 2123 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 0, 2124 MT_RX_SEL0, 0); 2125 if (phy->rdd_state & BIT(1)) 2126 mt7996_mcu_rdd_cmd(dev, RDD_STOP, 1, 2127 MT_RX_SEL0, 0); 2128 } 2129 2130 static int mt7996_dfs_start_rdd(struct mt7996_dev *dev, int chain) 2131 { 2132 int err, region; 2133 2134 switch (dev->mt76.region) { 2135 case NL80211_DFS_ETSI: 2136 region = 0; 2137 break; 2138 case NL80211_DFS_JP: 2139 region = 2; 2140 break; 2141 case NL80211_DFS_FCC: 2142 default: 2143 region = 1; 2144 break; 2145 } 2146 2147 err = mt7996_mcu_rdd_cmd(dev, RDD_START, chain, 2148 MT_RX_SEL0, region); 2149 if (err < 0) 2150 return err; 2151 2152 return mt7996_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, 2153 MT_RX_SEL0, 1); 2154 } 2155 2156 static int mt7996_dfs_start_radar_detector(struct mt7996_phy *phy) 2157 { 2158 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2159 struct mt7996_dev *dev = phy->dev; 2160 u8 band_idx = phy->mt76->band_idx; 2161 int err; 2162 2163 /* start CAC */ 2164 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_START, band_idx, 2165 MT_RX_SEL0, 0); 2166 if (err < 0) 2167 return err; 2168 2169 err = mt7996_dfs_start_rdd(dev, band_idx); 2170 if (err < 0) 2171 return err; 2172 2173 phy->rdd_state |= BIT(band_idx); 2174 2175 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2176 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2177 err = mt7996_dfs_start_rdd(dev, 1); 2178 if (err < 0) 2179 return err; 2180 2181 phy->rdd_state |= BIT(1); 2182 } 2183 2184 return 0; 2185 } 2186 2187 static int 2188 mt7996_dfs_init_radar_specs(struct mt7996_phy *phy) 2189 { 2190 const struct mt7996_dfs_radar_spec *radar_specs; 2191 struct mt7996_dev *dev = phy->dev; 2192 int err, i; 2193 2194 switch (dev->mt76.region) { 2195 case NL80211_DFS_FCC: 2196 radar_specs = &fcc_radar_specs; 2197 err = mt7996_mcu_set_fcc5_lpn(dev, 8); 2198 if (err < 0) 2199 return err; 2200 break; 2201 case NL80211_DFS_ETSI: 2202 radar_specs = &etsi_radar_specs; 2203 break; 2204 case NL80211_DFS_JP: 2205 radar_specs = &jp_radar_specs; 2206 break; 2207 default: 2208 return -EINVAL; 2209 } 2210 2211 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2212 err = mt7996_mcu_set_radar_th(dev, i, 2213 &radar_specs->radar_pattern[i]); 2214 if (err < 0) 2215 return err; 2216 } 2217 2218 return mt7996_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2219 } 2220 2221 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy) 2222 { 2223 struct mt7996_dev *dev = phy->dev; 2224 enum mt76_dfs_state dfs_state, prev_state; 2225 int err; 2226 2227 prev_state = phy->mt76->dfs_state; 2228 dfs_state = mt76_phy_dfs_state(phy->mt76); 2229 2230 if (prev_state == dfs_state) 2231 return 0; 2232 2233 if (prev_state == MT_DFS_STATE_UNKNOWN) 2234 mt7996_dfs_stop_radar_detector(phy); 2235 2236 if (dfs_state == MT_DFS_STATE_DISABLED) 2237 goto stop; 2238 2239 if (prev_state <= MT_DFS_STATE_DISABLED) { 2240 err = mt7996_dfs_init_radar_specs(phy); 2241 if (err < 0) 2242 return err; 2243 2244 err = mt7996_dfs_start_radar_detector(phy); 2245 if (err < 0) 2246 return err; 2247 2248 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2249 } 2250 2251 if (dfs_state == MT_DFS_STATE_CAC) 2252 return 0; 2253 2254 err = mt7996_mcu_rdd_cmd(dev, RDD_CAC_END, 2255 phy->mt76->band_idx, MT_RX_SEL0, 0); 2256 if (err < 0) { 2257 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2258 return err; 2259 } 2260 2261 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2262 return 0; 2263 2264 stop: 2265 err = mt7996_mcu_rdd_cmd(dev, RDD_NORMAL_START, 2266 phy->mt76->band_idx, MT_RX_SEL0, 0); 2267 if (err < 0) 2268 return err; 2269 2270 mt7996_dfs_stop_radar_detector(phy); 2271 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2272 2273 return 0; 2274 } 2275 2276 static int 2277 mt7996_mac_twt_duration_align(int duration) 2278 { 2279 return duration << 8; 2280 } 2281 2282 static u64 2283 mt7996_mac_twt_sched_list_add(struct mt7996_dev *dev, 2284 struct mt7996_twt_flow *flow) 2285 { 2286 struct mt7996_twt_flow *iter, *iter_next; 2287 u32 duration = flow->duration << 8; 2288 u64 start_tsf; 2289 2290 iter = list_first_entry_or_null(&dev->twt_list, 2291 struct mt7996_twt_flow, list); 2292 if (!iter || !iter->sched || iter->start_tsf > duration) { 2293 /* add flow as first entry in the list */ 2294 list_add(&flow->list, &dev->twt_list); 2295 return 0; 2296 } 2297 2298 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2299 start_tsf = iter->start_tsf + 2300 mt7996_mac_twt_duration_align(iter->duration); 2301 if (list_is_last(&iter->list, &dev->twt_list)) 2302 break; 2303 2304 if (!iter_next->sched || 2305 iter_next->start_tsf > start_tsf + duration) { 2306 list_add(&flow->list, &iter->list); 2307 goto out; 2308 } 2309 } 2310 2311 /* add flow as last entry in the list */ 2312 list_add_tail(&flow->list, &dev->twt_list); 2313 out: 2314 return start_tsf; 2315 } 2316 2317 static int mt7996_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2318 { 2319 struct ieee80211_twt_params *twt_agrt; 2320 u64 interval, duration; 2321 u16 mantissa; 2322 u8 exp; 2323 2324 /* only individual agreement supported */ 2325 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2326 return -EOPNOTSUPP; 2327 2328 /* only 256us unit supported */ 2329 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2330 return -EOPNOTSUPP; 2331 2332 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2333 2334 /* explicit agreement not supported */ 2335 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2336 return -EOPNOTSUPP; 2337 2338 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2339 le16_to_cpu(twt_agrt->req_type)); 2340 mantissa = le16_to_cpu(twt_agrt->mantissa); 2341 duration = twt_agrt->min_twt_dur << 8; 2342 2343 interval = (u64)mantissa << exp; 2344 if (interval < duration) 2345 return -EOPNOTSUPP; 2346 2347 return 0; 2348 } 2349 2350 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 2351 struct ieee80211_sta *sta, 2352 struct ieee80211_twt_setup *twt) 2353 { 2354 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2355 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 2356 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2357 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2358 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2359 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2360 struct mt7996_twt_flow *flow; 2361 int flowid, table_id; 2362 u8 exp; 2363 2364 if (mt7996_mac_check_twt_req(twt)) 2365 goto out; 2366 2367 mutex_lock(&dev->mt76.mutex); 2368 2369 if (dev->twt.n_agrt == MT7996_MAX_TWT_AGRT) 2370 goto unlock; 2371 2372 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2373 goto unlock; 2374 2375 flowid = ffs(~msta->twt.flowid_mask) - 1; 2376 le16p_replace_bits(&twt_agrt->req_type, flowid, 2377 IEEE80211_TWT_REQTYPE_FLOWID); 2378 2379 table_id = ffs(~dev->twt.table_mask) - 1; 2380 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2381 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2382 2383 flow = &msta->twt.flow[flowid]; 2384 memset(flow, 0, sizeof(*flow)); 2385 INIT_LIST_HEAD(&flow->list); 2386 flow->wcid = msta->wcid.idx; 2387 flow->table_id = table_id; 2388 flow->id = flowid; 2389 flow->duration = twt_agrt->min_twt_dur; 2390 flow->mantissa = twt_agrt->mantissa; 2391 flow->exp = exp; 2392 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2393 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2394 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2395 2396 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2397 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2398 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2399 u64 flow_tsf, curr_tsf; 2400 u32 rem; 2401 2402 flow->sched = true; 2403 flow->start_tsf = mt7996_mac_twt_sched_list_add(dev, flow); 2404 curr_tsf = __mt7996_get_tsf(hw, msta->vif); 2405 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2406 flow_tsf = curr_tsf + interval - rem; 2407 twt_agrt->twt = cpu_to_le64(flow_tsf); 2408 } else { 2409 list_add_tail(&flow->list, &dev->twt_list); 2410 } 2411 flow->tsf = le64_to_cpu(twt_agrt->twt); 2412 2413 if (mt7996_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2414 goto unlock; 2415 2416 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2417 dev->twt.table_mask |= BIT(table_id); 2418 msta->twt.flowid_mask |= BIT(flowid); 2419 dev->twt.n_agrt++; 2420 2421 unlock: 2422 mutex_unlock(&dev->mt76.mutex); 2423 out: 2424 le16p_replace_bits(&twt_agrt->req_type, setup_cmd, 2425 IEEE80211_TWT_REQTYPE_SETUP_CMD); 2426 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2427 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2428 } 2429 2430 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 2431 struct mt7996_sta *msta, 2432 u8 flowid) 2433 { 2434 struct mt7996_twt_flow *flow; 2435 2436 lockdep_assert_held(&dev->mt76.mutex); 2437 2438 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2439 return; 2440 2441 if (!(msta->twt.flowid_mask & BIT(flowid))) 2442 return; 2443 2444 flow = &msta->twt.flow[flowid]; 2445 if (mt7996_mcu_twt_agrt_update(dev, msta->vif, flow, 2446 MCU_TWT_AGRT_DELETE)) 2447 return; 2448 2449 list_del_init(&flow->list); 2450 msta->twt.flowid_mask &= ~BIT(flowid); 2451 dev->twt.table_mask &= ~BIT(flow->table_id); 2452 dev->twt.n_agrt--; 2453 } 2454