1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/thermal.h> 8 #include "mt7996.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "eeprom.h" 12 13 static const struct ieee80211_iface_limit if_limits[] = { 14 { 15 .max = 1, 16 .types = BIT(NL80211_IFTYPE_ADHOC) 17 }, { 18 .max = 16, 19 .types = BIT(NL80211_IFTYPE_AP) 20 #ifdef CONFIG_MAC80211_MESH 21 | BIT(NL80211_IFTYPE_MESH_POINT) 22 #endif 23 }, { 24 .max = MT7996_MAX_INTERFACES, 25 .types = BIT(NL80211_IFTYPE_STATION) 26 } 27 }; 28 29 static const struct ieee80211_iface_combination if_comb[] = { 30 { 31 .limits = if_limits, 32 .n_limits = ARRAY_SIZE(if_limits), 33 .max_interfaces = MT7996_MAX_INTERFACES, 34 .num_different_channels = 1, 35 .beacon_int_infra_match = true, 36 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 37 BIT(NL80211_CHAN_WIDTH_20) | 38 BIT(NL80211_CHAN_WIDTH_40) | 39 BIT(NL80211_CHAN_WIDTH_80) | 40 BIT(NL80211_CHAN_WIDTH_160) | 41 BIT(NL80211_CHAN_WIDTH_80P80), 42 } 43 }; 44 45 static void mt7996_led_set_config(struct led_classdev *led_cdev, 46 u8 delay_on, u8 delay_off) 47 { 48 struct mt7996_dev *dev; 49 struct mt76_phy *mphy; 50 u32 val; 51 52 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 53 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 54 55 /* select TX blink mode, 2: only data frames */ 56 mt76_rmw_field(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TX_BLINK, 2); 57 58 /* enable LED */ 59 mt76_wr(dev, MT_LED_EN(0), 1); 60 61 /* set LED Tx blink on/off time */ 62 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 63 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 64 mt76_wr(dev, MT_LED_TX_BLINK(0), val); 65 66 /* control LED */ 67 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 68 if (mphy->leds.al) 69 val |= MT_LED_CTRL_POLARITY; 70 71 mt76_wr(dev, MT_LED_CTRL(0), val); 72 mt76_clear(dev, MT_LED_CTRL(0), MT_LED_CTRL_KICK); 73 } 74 75 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 76 unsigned long *delay_on, 77 unsigned long *delay_off) 78 { 79 u16 delta_on = 0, delta_off = 0; 80 81 #define HW_TICK 10 82 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 83 84 if (*delay_on) 85 delta_on = TO_HW_TICK(*delay_on); 86 if (*delay_off) 87 delta_off = TO_HW_TICK(*delay_off); 88 89 mt7996_led_set_config(led_cdev, delta_on, delta_off); 90 91 return 0; 92 } 93 94 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 95 enum led_brightness brightness) 96 { 97 if (!brightness) 98 mt7996_led_set_config(led_cdev, 0, 0xff); 99 else 100 mt7996_led_set_config(led_cdev, 0xff, 0); 101 } 102 103 static void 104 mt7996_init_txpower(struct mt7996_dev *dev, 105 struct ieee80211_supported_band *sband) 106 { 107 int i, nss = hweight8(dev->mphy.antenna_mask); 108 int nss_delta = mt76_tx_power_nss_delta(nss); 109 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 110 struct mt76_power_limits limits; 111 112 for (i = 0; i < sband->n_channels; i++) { 113 struct ieee80211_channel *chan = &sband->channels[i]; 114 int target_power = mt7996_eeprom_get_target_power(dev, chan); 115 116 target_power += pwr_delta; 117 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 118 &limits, 119 target_power); 120 target_power += nss_delta; 121 target_power = DIV_ROUND_UP(target_power, 2); 122 chan->max_power = min_t(int, chan->max_reg_power, 123 target_power); 124 chan->orig_mpwr = target_power; 125 } 126 } 127 128 static void 129 mt7996_regd_notifier(struct wiphy *wiphy, 130 struct regulatory_request *request) 131 { 132 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 133 struct mt7996_dev *dev = mt7996_hw_dev(hw); 134 struct mt7996_phy *phy = mt7996_hw_phy(hw); 135 136 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 137 dev->mt76.region = request->dfs_region; 138 139 if (dev->mt76.region == NL80211_DFS_UNSET) 140 mt7996_mcu_rdd_background_enable(phy, NULL); 141 142 mt7996_init_txpower(dev, &phy->mt76->sband_2g.sband); 143 mt7996_init_txpower(dev, &phy->mt76->sband_5g.sband); 144 mt7996_init_txpower(dev, &phy->mt76->sband_6g.sband); 145 146 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 147 mt7996_dfs_init_radar_detector(phy); 148 } 149 150 static void 151 mt7996_init_wiphy(struct ieee80211_hw *hw) 152 { 153 struct mt7996_phy *phy = mt7996_hw_phy(hw); 154 struct mt76_dev *mdev = &phy->dev->mt76; 155 struct wiphy *wiphy = hw->wiphy; 156 157 hw->queues = 4; 158 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 159 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 160 hw->netdev_features = NETIF_F_RXCSUM; 161 162 hw->radiotap_timestamp.units_pos = 163 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 164 165 phy->slottime = 9; 166 167 hw->sta_data_size = sizeof(struct mt7996_sta); 168 hw->vif_data_size = sizeof(struct mt7996_vif); 169 170 wiphy->iface_combinations = if_comb; 171 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 172 wiphy->reg_notifier = mt7996_regd_notifier; 173 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 174 175 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 176 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 177 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 178 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 179 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 180 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 181 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 182 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 183 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 184 185 if (!mdev->dev->of_node || 186 !of_property_read_bool(mdev->dev->of_node, 187 "mediatek,disable-radar-background")) 188 wiphy_ext_feature_set(wiphy, 189 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 190 191 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 192 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 193 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 194 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 195 196 hw->max_tx_fragments = 4; 197 198 if (phy->mt76->cap.has_2ghz) 199 phy->mt76->sband_2g.sband.ht_cap.cap |= 200 IEEE80211_HT_CAP_LDPC_CODING | 201 IEEE80211_HT_CAP_MAX_AMSDU; 202 203 if (phy->mt76->cap.has_5ghz) { 204 phy->mt76->sband_5g.sband.ht_cap.cap |= 205 IEEE80211_HT_CAP_LDPC_CODING | 206 IEEE80211_HT_CAP_MAX_AMSDU; 207 208 phy->mt76->sband_5g.sband.vht_cap.cap |= 209 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 210 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 211 IEEE80211_VHT_CAP_SHORT_GI_160 | 212 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 213 } 214 215 mt76_set_stream_caps(phy->mt76, true); 216 mt7996_set_stream_vht_txbf_caps(phy); 217 mt7996_set_stream_he_caps(phy); 218 219 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 220 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 221 } 222 223 static void 224 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 225 { 226 u32 mask, set; 227 228 /* clear estimated value of EIFS for Rx duration & OBSS time */ 229 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 230 231 /* clear backoff time for Rx duration */ 232 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 233 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 234 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 235 MT_WF_RMAC_MIB_QOS01_BACKOFF); 236 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 237 MT_WF_RMAC_MIB_QOS23_BACKOFF); 238 239 /* clear backoff time and set software compensation for OBSS time */ 240 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 241 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 242 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 243 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 244 245 /* filter out non-resp frames and get instanstaeous signal reporting */ 246 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 247 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 248 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 249 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 250 } 251 252 static void mt7996_mac_init(struct mt7996_dev *dev) 253 { 254 #define HIF_TXD_V2_1 4 255 int i; 256 257 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 258 259 for (i = 0; i < MT7996_WTBL_SIZE; i++) 260 mt7996_mac_wtbl_update(dev, i, 261 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 262 263 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 264 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 265 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 266 } 267 268 /* txs report queue */ 269 mt76_rmw_field(dev, MT_DMA_TCRF1(0), MT_DMA_TCRF1_QIDX, 0); 270 mt76_rmw_field(dev, MT_DMA_TCRF1(1), MT_DMA_TCRF1_QIDX, 6); 271 mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0); 272 273 /* rro module init */ 274 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 275 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 276 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 277 278 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 279 MCU_WA_PARAM_HW_PATH_HIF_VER, 280 HIF_TXD_V2_1, 0); 281 282 for (i = MT_BAND0; i <= MT_BAND2; i++) 283 mt7996_mac_init_band(dev, i); 284 } 285 286 static int mt7996_txbf_init(struct mt7996_dev *dev) 287 { 288 int ret; 289 290 if (dev->dbdc_support) { 291 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 292 if (ret) 293 return ret; 294 } 295 296 /* trigger sounding packets */ 297 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 298 if (ret) 299 return ret; 300 301 /* enable eBF */ 302 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 303 } 304 305 static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, 306 enum mt76_band_id band) 307 { 308 struct mt76_phy *mphy; 309 u32 mac_ofs, hif1_ofs = 0; 310 int ret; 311 312 if (band != MT_BAND1 && band != MT_BAND2) 313 return 0; 314 315 if ((band == MT_BAND1 && !dev->dbdc_support) || 316 (band == MT_BAND2 && !dev->tbtc_support)) 317 return 0; 318 319 if (phy) 320 return 0; 321 322 if (band == MT_BAND2 && dev->hif2) 323 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 324 325 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band); 326 if (!mphy) 327 return -ENOMEM; 328 329 phy = mphy->priv; 330 phy->dev = dev; 331 phy->mt76 = mphy; 332 mphy->dev->phys[band] = mphy; 333 334 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 335 336 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 337 if (ret) 338 goto error; 339 340 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 341 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 342 /* Make the extra PHY MAC address local without overlapping with 343 * the usual MAC address allocation scheme on multiple virtual interfaces 344 */ 345 if (!is_valid_ether_addr(mphy->macaddr)) { 346 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 347 ETH_ALEN); 348 mphy->macaddr[0] |= 2; 349 mphy->macaddr[0] ^= BIT(7); 350 if (band == MT_BAND2) 351 mphy->macaddr[0] ^= BIT(6); 352 } 353 mt76_eeprom_override(mphy); 354 355 /* init wiphy according to mphy and phy */ 356 mt7996_init_wiphy(mphy->hw); 357 ret = mt76_connac_init_tx_queues(phy->mt76, 358 MT_TXQ_ID(band), 359 MT7996_TX_RING_SIZE, 360 MT_TXQ_RING_BASE(band) + hif1_ofs, 0); 361 if (ret) 362 goto error; 363 364 ret = mt76_register_phy(mphy, true, mt76_rates, 365 ARRAY_SIZE(mt76_rates)); 366 if (ret) 367 goto error; 368 369 ret = mt7996_init_debugfs(phy); 370 if (ret) 371 goto error; 372 373 return 0; 374 375 error: 376 mphy->dev->phys[band] = NULL; 377 ieee80211_free_hw(mphy->hw); 378 return ret; 379 } 380 381 static void 382 mt7996_unregister_phy(struct mt7996_phy *phy, enum mt76_band_id band) 383 { 384 struct mt76_phy *mphy; 385 386 if (!phy) 387 return; 388 389 mphy = phy->dev->mt76.phys[band]; 390 mt76_unregister_phy(mphy); 391 ieee80211_free_hw(mphy->hw); 392 phy->dev->mt76.phys[band] = NULL; 393 } 394 395 static void mt7996_init_work(struct work_struct *work) 396 { 397 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 398 init_work); 399 400 mt7996_mcu_set_eeprom(dev); 401 mt7996_mac_init(dev); 402 mt7996_init_txpower(dev, &dev->mphy.sband_2g.sband); 403 mt7996_init_txpower(dev, &dev->mphy.sband_5g.sband); 404 mt7996_init_txpower(dev, &dev->mphy.sband_6g.sband); 405 mt7996_txbf_init(dev); 406 } 407 408 void mt7996_wfsys_reset(struct mt7996_dev *dev) 409 { 410 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 411 msleep(20); 412 413 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 414 msleep(20); 415 } 416 417 static int mt7996_init_hardware(struct mt7996_dev *dev) 418 { 419 int ret, idx; 420 421 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 422 423 INIT_WORK(&dev->init_work, mt7996_init_work); 424 425 dev->dbdc_support = true; 426 dev->tbtc_support = true; 427 428 ret = mt7996_dma_init(dev); 429 if (ret) 430 return ret; 431 432 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 433 434 ret = mt7996_mcu_init(dev); 435 if (ret) 436 return ret; 437 438 ret = mt7996_eeprom_init(dev); 439 if (ret < 0) 440 return ret; 441 442 /* Beacon and mgmt frames should occupy wcid 0 */ 443 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 444 if (idx) 445 return -ENOSPC; 446 447 dev->mt76.global_wcid.idx = idx; 448 dev->mt76.global_wcid.hw_key_idx = -1; 449 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 450 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 451 452 return 0; 453 } 454 455 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 456 { 457 int sts; 458 u32 *cap; 459 460 if (!phy->mt76->cap.has_5ghz) 461 return; 462 463 sts = hweight16(phy->mt76->chainmask); 464 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 465 466 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 467 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 468 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, sts - 1); 469 470 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 471 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 472 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 473 474 if (sts < 2) 475 return; 476 477 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 478 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 479 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 480 } 481 482 static void 483 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 484 struct ieee80211_sta_he_cap *he_cap, int vif) 485 { 486 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 487 int sts = hweight16(phy->mt76->chainmask); 488 u8 c; 489 490 #ifdef CONFIG_MAC80211_MESH 491 if (vif == NL80211_IFTYPE_MESH_POINT) 492 return; 493 #endif 494 495 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 496 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 497 498 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 499 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 500 elem->phy_cap_info[5] &= ~c; 501 502 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 503 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 504 elem->phy_cap_info[6] &= ~c; 505 506 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 507 508 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 509 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 510 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 511 elem->phy_cap_info[2] |= c; 512 513 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 514 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 515 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 516 elem->phy_cap_info[4] |= c; 517 518 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 519 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 520 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 521 522 if (vif == NL80211_IFTYPE_STATION) 523 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 524 525 elem->phy_cap_info[6] |= c; 526 527 if (sts < 2) 528 return; 529 530 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 531 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 532 533 if (vif != NL80211_IFTYPE_AP) 534 return; 535 536 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 537 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 538 539 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 540 sts - 1) | 541 FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 542 sts - 1); 543 elem->phy_cap_info[5] |= c; 544 545 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 546 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 547 elem->phy_cap_info[6] |= c; 548 549 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 550 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 551 elem->phy_cap_info[7] |= c; 552 } 553 554 static void 555 mt7996_gen_ppe_thresh(u8 *he_ppet, int nss) 556 { 557 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ 558 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; 559 560 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | 561 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, 562 ru_bit_mask); 563 564 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * 565 nss * hweight8(ru_bit_mask) * 2; 566 ppet_size = DIV_ROUND_UP(ppet_bits, 8); 567 568 for (i = 0; i < ppet_size - 1; i++) 569 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; 570 571 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & 572 (0xff >> (8 - (ppet_bits - 1) % 8)); 573 } 574 575 static int 576 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 577 struct ieee80211_sband_iftype_data *data) 578 { 579 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 580 u16 mcs_map = 0; 581 582 for (i = 0; i < 8; i++) { 583 if (i < nss) 584 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 585 else 586 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 587 } 588 589 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 590 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 591 struct ieee80211_he_cap_elem *he_cap_elem = 592 &he_cap->he_cap_elem; 593 struct ieee80211_he_mcs_nss_supp *he_mcs = 594 &he_cap->he_mcs_nss_supp; 595 596 switch (i) { 597 case NL80211_IFTYPE_STATION: 598 case NL80211_IFTYPE_AP: 599 #ifdef CONFIG_MAC80211_MESH 600 case NL80211_IFTYPE_MESH_POINT: 601 #endif 602 break; 603 default: 604 continue; 605 } 606 607 data[idx].types_mask = BIT(i); 608 he_cap->has_he = true; 609 610 he_cap_elem->mac_cap_info[0] = 611 IEEE80211_HE_MAC_CAP0_HTC_HE; 612 he_cap_elem->mac_cap_info[3] = 613 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 614 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 615 he_cap_elem->mac_cap_info[4] = 616 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 617 618 if (band == NL80211_BAND_2GHZ) 619 he_cap_elem->phy_cap_info[0] = 620 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 621 else 622 he_cap_elem->phy_cap_info[0] = 623 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 624 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | 625 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; 626 627 he_cap_elem->phy_cap_info[1] = 628 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 629 he_cap_elem->phy_cap_info[2] = 630 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 631 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 632 633 switch (i) { 634 case NL80211_IFTYPE_AP: 635 he_cap_elem->mac_cap_info[0] |= 636 IEEE80211_HE_MAC_CAP0_TWT_RES; 637 he_cap_elem->mac_cap_info[2] |= 638 IEEE80211_HE_MAC_CAP2_BSR; 639 he_cap_elem->mac_cap_info[4] |= 640 IEEE80211_HE_MAC_CAP4_BQR; 641 he_cap_elem->mac_cap_info[5] |= 642 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 643 he_cap_elem->phy_cap_info[3] |= 644 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 645 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 646 he_cap_elem->phy_cap_info[6] |= 647 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 648 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 649 he_cap_elem->phy_cap_info[9] |= 650 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 651 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 652 break; 653 case NL80211_IFTYPE_STATION: 654 he_cap_elem->mac_cap_info[1] |= 655 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 656 657 if (band == NL80211_BAND_2GHZ) 658 he_cap_elem->phy_cap_info[0] |= 659 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 660 else 661 he_cap_elem->phy_cap_info[0] |= 662 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 663 664 he_cap_elem->phy_cap_info[1] |= 665 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 666 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 667 he_cap_elem->phy_cap_info[3] |= 668 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 669 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 670 he_cap_elem->phy_cap_info[6] |= 671 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 672 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 673 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 674 he_cap_elem->phy_cap_info[7] |= 675 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 676 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 677 he_cap_elem->phy_cap_info[8] |= 678 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 679 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 680 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 681 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 682 he_cap_elem->phy_cap_info[9] |= 683 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 684 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 685 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 686 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 687 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 688 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 689 break; 690 } 691 692 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 693 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 694 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 695 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 696 he_mcs->rx_mcs_80p80 = cpu_to_le16(mcs_map); 697 he_mcs->tx_mcs_80p80 = cpu_to_le16(mcs_map); 698 699 mt7996_set_stream_he_txbf_caps(phy, he_cap, i); 700 701 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 702 if (he_cap_elem->phy_cap_info[6] & 703 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 704 mt7996_gen_ppe_thresh(he_cap->ppe_thres, nss); 705 } else { 706 he_cap_elem->phy_cap_info[9] |= 707 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US; 708 } 709 710 if (band == NL80211_BAND_6GHZ) { 711 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 712 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 713 714 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 715 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 716 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 717 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 718 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 719 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 720 721 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 722 } 723 724 idx++; 725 } 726 727 return idx; 728 } 729 730 void mt7996_set_stream_he_caps(struct mt7996_phy *phy) 731 { 732 struct ieee80211_sband_iftype_data *data; 733 struct ieee80211_supported_band *band; 734 int n; 735 736 if (phy->mt76->cap.has_2ghz) { 737 data = phy->iftype[NL80211_BAND_2GHZ]; 738 n = mt7996_init_he_caps(phy, NL80211_BAND_2GHZ, data); 739 740 band = &phy->mt76->sband_2g.sband; 741 band->iftype_data = data; 742 band->n_iftype_data = n; 743 } 744 745 if (phy->mt76->cap.has_5ghz) { 746 data = phy->iftype[NL80211_BAND_5GHZ]; 747 n = mt7996_init_he_caps(phy, NL80211_BAND_5GHZ, data); 748 749 band = &phy->mt76->sband_5g.sband; 750 band->iftype_data = data; 751 band->n_iftype_data = n; 752 } 753 754 if (phy->mt76->cap.has_6ghz) { 755 data = phy->iftype[NL80211_BAND_6GHZ]; 756 n = mt7996_init_he_caps(phy, NL80211_BAND_6GHZ, data); 757 758 band = &phy->mt76->sband_6g.sband; 759 band->iftype_data = data; 760 band->n_iftype_data = n; 761 } 762 } 763 764 int mt7996_register_device(struct mt7996_dev *dev) 765 { 766 struct ieee80211_hw *hw = mt76_hw(dev); 767 int ret; 768 769 dev->phy.dev = dev; 770 dev->phy.mt76 = &dev->mt76.phy; 771 dev->mt76.phy.priv = &dev->phy; 772 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 773 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 774 INIT_LIST_HEAD(&dev->sta_rc_list); 775 INIT_LIST_HEAD(&dev->sta_poll_list); 776 INIT_LIST_HEAD(&dev->twt_list); 777 spin_lock_init(&dev->sta_poll_lock); 778 779 init_waitqueue_head(&dev->reset_wait); 780 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 781 782 ret = mt7996_init_hardware(dev); 783 if (ret) 784 return ret; 785 786 mt7996_init_wiphy(hw); 787 788 /* init led callbacks */ 789 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 790 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 791 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 792 } 793 794 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 795 ARRAY_SIZE(mt76_rates)); 796 if (ret) 797 return ret; 798 799 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 800 801 ret = mt7996_register_phy(dev, mt7996_phy2(dev), MT_BAND1); 802 if (ret) 803 return ret; 804 805 ret = mt7996_register_phy(dev, mt7996_phy3(dev), MT_BAND2); 806 if (ret) 807 return ret; 808 809 return mt7996_init_debugfs(&dev->phy); 810 } 811 812 void mt7996_unregister_device(struct mt7996_dev *dev) 813 { 814 mt7996_unregister_phy(mt7996_phy3(dev), MT_BAND2); 815 mt7996_unregister_phy(mt7996_phy2(dev), MT_BAND1); 816 mt76_unregister_device(&dev->mt76); 817 mt7996_mcu_exit(dev); 818 mt7996_tx_token_put(dev); 819 mt7996_dma_cleanup(dev); 820 tasklet_disable(&dev->irq_tasklet); 821 822 mt76_free_device(&dev->mt76); 823 } 824