1*6db1b497SLorenzo Bianconi /* SPDX-License-Identifier: ISC */ 2*6db1b497SLorenzo Bianconi /* Copyright (C) 2023 MediaTek Inc. */ 3*6db1b497SLorenzo Bianconi 4*6db1b497SLorenzo Bianconi #ifndef __MT792X_REGS_H 5*6db1b497SLorenzo Bianconi #define __MT792X_REGS_H 6*6db1b497SLorenzo Bianconi 7*6db1b497SLorenzo Bianconi /* MCU WFDMA1 */ 8*6db1b497SLorenzo Bianconi #define MT_MCU_WFDMA1_BASE 0x3000 9*6db1b497SLorenzo Bianconi #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 10*6db1b497SLorenzo Bianconi 11*6db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108) 12*6db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 13*6db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 14*6db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 15*6db1b497SLorenzo Bianconi #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 16*6db1b497SLorenzo Bianconi 17*6db1b497SLorenzo Bianconi #define MT_PLE_BASE 0x820c0000 18*6db1b497SLorenzo Bianconi #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 19*6db1b497SLorenzo Bianconi 20*6db1b497SLorenzo Bianconi #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0) 21*6db1b497SLorenzo Bianconi #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4) 22*6db1b497SLorenzo Bianconi #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8) 23*6db1b497SLorenzo Bianconi #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec) 24*6db1b497SLorenzo Bianconi 25*6db1b497SLorenzo Bianconi #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n)) 26*6db1b497SLorenzo Bianconi #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 27*6db1b497SLorenzo Bianconi 28*6db1b497SLorenzo Bianconi /* TMAC: band 0(0x21000), band 1(0xa1000) */ 29*6db1b497SLorenzo Bianconi #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 30*6db1b497SLorenzo Bianconi #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 31*6db1b497SLorenzo Bianconi 32*6db1b497SLorenzo Bianconi #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 33*6db1b497SLorenzo Bianconi #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 34*6db1b497SLorenzo Bianconi 35*6db1b497SLorenzo Bianconi #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090) 36*6db1b497SLorenzo Bianconi #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094) 37*6db1b497SLorenzo Bianconi #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 38*6db1b497SLorenzo Bianconi #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 39*6db1b497SLorenzo Bianconi 40*6db1b497SLorenzo Bianconi #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4) 41*6db1b497SLorenzo Bianconi #define MT_IFS_EIFS GENMASK(8, 0) 42*6db1b497SLorenzo Bianconi #define MT_IFS_RIFS GENMASK(14, 10) 43*6db1b497SLorenzo Bianconi #define MT_IFS_SIFS GENMASK(22, 16) 44*6db1b497SLorenzo Bianconi #define MT_IFS_SLOT GENMASK(30, 24) 45*6db1b497SLorenzo Bianconi 46*6db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4) 47*6db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 48*6db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 49*6db1b497SLorenzo Bianconi #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 50*6db1b497SLorenzo Bianconi 51*6db1b497SLorenzo Bianconi #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c) 52*6db1b497SLorenzo Bianconi #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0) 53*6db1b497SLorenzo Bianconi 54*6db1b497SLorenzo Bianconi #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 55*6db1b497SLorenzo Bianconi #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 56*6db1b497SLorenzo Bianconi 57*6db1b497SLorenzo Bianconi #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 58*6db1b497SLorenzo Bianconi #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 59*6db1b497SLorenzo Bianconi #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 60*6db1b497SLorenzo Bianconi 61*6db1b497SLorenzo Bianconi /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */ 62*6db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000) 63*6db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP(_band, ofs) (MT_WTBLOFF_TOP_BASE(_band) + (ofs)) 64*6db1b497SLorenzo Bianconi 65*6db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008) 66*6db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30) 67*6db1b497SLorenzo Bianconi #define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24) 68*6db1b497SLorenzo Bianconi 69*6db1b497SLorenzo Bianconi /* LPON: band 0(0x24200), band 1(0xa4200) */ 70*6db1b497SLorenzo Bianconi #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 71*6db1b497SLorenzo Bianconi #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 72*6db1b497SLorenzo Bianconi 73*6db1b497SLorenzo Bianconi #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080) 74*6db1b497SLorenzo Bianconi #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084) 75*6db1b497SLorenzo Bianconi 76*6db1b497SLorenzo Bianconi #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4) 77*6db1b497SLorenzo Bianconi #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 78*6db1b497SLorenzo Bianconi #define MT_LPON_TCR_SW_WRITE BIT(0) 79*6db1b497SLorenzo Bianconi 80*6db1b497SLorenzo Bianconi /* ETBF: band 0(0x24000), band 1(0xa4000) */ 81*6db1b497SLorenzo Bianconi #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 82*6db1b497SLorenzo Bianconi #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 83*6db1b497SLorenzo Bianconi 84*6db1b497SLorenzo Bianconi #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x150) 85*6db1b497SLorenzo Bianconi #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 86*6db1b497SLorenzo Bianconi #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 87*6db1b497SLorenzo Bianconi 88*6db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x158) 89*6db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 90*6db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 91*6db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 92*6db1b497SLorenzo Bianconi #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 93*6db1b497SLorenzo Bianconi 94*6db1b497SLorenzo Bianconi /* MIB: band 0(0x24800), band 1(0xa4800) */ 95*6db1b497SLorenzo Bianconi #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 96*6db1b497SLorenzo Bianconi #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 97*6db1b497SLorenzo Bianconi 98*6db1b497SLorenzo Bianconi #define MT_MIB_SCR1(_band) MT_WF_MIB(_band, 0x004) 99*6db1b497SLorenzo Bianconi #define MT_MIB_TXDUR_EN BIT(8) 100*6db1b497SLorenzo Bianconi #define MT_MIB_RXDUR_EN BIT(9) 101*6db1b497SLorenzo Bianconi 102*6db1b497SLorenzo Bianconi #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x698) 103*6db1b497SLorenzo Bianconi #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(31, 16) 104*6db1b497SLorenzo Bianconi 105*6db1b497SLorenzo Bianconi #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x780) 106*6db1b497SLorenzo Bianconi 107*6db1b497SLorenzo Bianconi #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) 108*6db1b497SLorenzo Bianconi #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) 109*6db1b497SLorenzo Bianconi 110*6db1b497SLorenzo Bianconi #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, 0x558) 111*6db1b497SLorenzo Bianconi #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x564) 112*6db1b497SLorenzo Bianconi #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x568) 113*6db1b497SLorenzo Bianconi 114*6db1b497SLorenzo Bianconi #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) 115*6db1b497SLorenzo Bianconi #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) 116*6db1b497SLorenzo Bianconi 117*6db1b497SLorenzo Bianconi #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, 0x770) 118*6db1b497SLorenzo Bianconi #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, 0x774) 119*6db1b497SLorenzo Bianconi #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, 0x55c) 120*6db1b497SLorenzo Bianconi 121*6db1b497SLorenzo Bianconi #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, 0x7a8) 122*6db1b497SLorenzo Bianconi #define MT_MIB_SDR9_IBF_CNT_MASK GENMASK(31, 16) 123*6db1b497SLorenzo Bianconi #define MT_MIB_SDR9_EBF_CNT_MASK GENMASK(15, 0) 124*6db1b497SLorenzo Bianconi 125*6db1b497SLorenzo Bianconi #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090) 126*6db1b497SLorenzo Bianconi #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 127*6db1b497SLorenzo Bianconi 128*6db1b497SLorenzo Bianconi #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x054) 129*6db1b497SLorenzo Bianconi #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) 130*6db1b497SLorenzo Bianconi #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x058) 131*6db1b497SLorenzo Bianconi #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) 132*6db1b497SLorenzo Bianconi 133*6db1b497SLorenzo Bianconi #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0) 134*6db1b497SLorenzo Bianconi #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4) 135*6db1b497SLorenzo Bianconi #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc) 136*6db1b497SLorenzo Bianconi 137*6db1b497SLorenzo Bianconi #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) 138*6db1b497SLorenzo Bianconi #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 139*6db1b497SLorenzo Bianconi 140*6db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR0(_band) MT_WF_MIB(_band, 0x688) 141*6db1b497SLorenzo Bianconi #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 142*6db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR1(_band) MT_WF_MIB(_band, 0x690) 143*6db1b497SLorenzo Bianconi #define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0) 144*6db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR2(_band) MT_WF_MIB(_band, 0x518) 145*6db1b497SLorenzo Bianconi #define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0) 146*6db1b497SLorenzo Bianconi #define MT_MIB_MB_BSDR3(_band) MT_WF_MIB(_band, 0x520) 147*6db1b497SLorenzo Bianconi #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0) 148*6db1b497SLorenzo Bianconi 149*6db1b497SLorenzo Bianconi #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4)) 150*6db1b497SLorenzo Bianconi #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0) 151*6db1b497SLorenzo Bianconi 152*6db1b497SLorenzo Bianconi #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x7dc + ((n) << 2)) 153*6db1b497SLorenzo Bianconi #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x7ec + ((n) << 2)) 154*6db1b497SLorenzo Bianconi #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 155*6db1b497SLorenzo Bianconi #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 156*6db1b497SLorenzo Bianconi 157*6db1b497SLorenzo Bianconi #define MT_WTBLON_TOP_BASE 0x820d4000 158*6db1b497SLorenzo Bianconi #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 159*6db1b497SLorenzo Bianconi 160*6db1b497SLorenzo Bianconi #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x230) 161*6db1b497SLorenzo Bianconi #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 162*6db1b497SLorenzo Bianconi #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 163*6db1b497SLorenzo Bianconi #define MT_WTBL_UPDATE_BUSY BIT(31) 164*6db1b497SLorenzo Bianconi 165*6db1b497SLorenzo Bianconi #define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0) 166*6db1b497SLorenzo Bianconi #define MT_WTBL_ITCR_WR BIT(16) 167*6db1b497SLorenzo Bianconi #define MT_WTBL_ITCR_EXEC BIT(31) 168*6db1b497SLorenzo Bianconi #define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8) 169*6db1b497SLorenzo Bianconi #define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc) 170*6db1b497SLorenzo Bianconi #define MT_WTBL_SPE_IDX_SEL BIT(6) 171*6db1b497SLorenzo Bianconi 172*6db1b497SLorenzo Bianconi #define MT_WTBL_BASE 0x820d8000 173*6db1b497SLorenzo Bianconi #define MT_WTBL_LMAC_ID GENMASK(14, 8) 174*6db1b497SLorenzo Bianconi #define MT_WTBL_LMAC_DW GENMASK(7, 2) 175*6db1b497SLorenzo Bianconi #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 176*6db1b497SLorenzo Bianconi FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 177*6db1b497SLorenzo Bianconi FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 178*6db1b497SLorenzo Bianconi 179*6db1b497SLorenzo Bianconi /* AGG: band 0(0x20800), band 1(0xa0800) */ 180*6db1b497SLorenzo Bianconi #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 181*6db1b497SLorenzo Bianconi #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 182*6db1b497SLorenzo Bianconi 183*6db1b497SLorenzo Bianconi #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4) 184*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4) 185*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_MM_PROT BIT(0) 186*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_GF_PROT BIT(1) 187*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_BW20_PROT BIT(2) 188*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_BW40_PROT BIT(4) 189*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_BW80_PROT BIT(6) 190*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 191*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_VHT_PROT BIT(13) 192*6db1b497SLorenzo Bianconi #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 193*6db1b497SLorenzo Bianconi 194*6db1b497SLorenzo Bianconi #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 195*6db1b497SLorenzo Bianconi #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 196*6db1b497SLorenzo Bianconi 197*6db1b497SLorenzo Bianconi #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084) 198*6db1b497SLorenzo Bianconi #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 199*6db1b497SLorenzo Bianconi #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 200*6db1b497SLorenzo Bianconi 201*6db1b497SLorenzo Bianconi #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098) 202*6db1b497SLorenzo Bianconi #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 203*6db1b497SLorenzo Bianconi #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 204*6db1b497SLorenzo Bianconi #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 205*6db1b497SLorenzo Bianconi #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 206*6db1b497SLorenzo Bianconi 207*6db1b497SLorenzo Bianconi #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0) 208*6db1b497SLorenzo Bianconi #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4) 209*6db1b497SLorenzo Bianconi 210*6db1b497SLorenzo Bianconi /* ARB: band 0(0x20c00), band 1(0xa0c00) */ 211*6db1b497SLorenzo Bianconi #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 212*6db1b497SLorenzo Bianconi #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 213*6db1b497SLorenzo Bianconi 214*6db1b497SLorenzo Bianconi #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080) 215*6db1b497SLorenzo Bianconi #define MT_ARB_SCR_TX_DISABLE BIT(8) 216*6db1b497SLorenzo Bianconi #define MT_ARB_SCR_RX_DISABLE BIT(9) 217*6db1b497SLorenzo Bianconi 218*6db1b497SLorenzo Bianconi #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4) 219*6db1b497SLorenzo Bianconi 220*6db1b497SLorenzo Bianconi /* RMAC: band 0(0x21400), band 1(0xa1400) */ 221*6db1b497SLorenzo Bianconi #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 222*6db1b497SLorenzo Bianconi #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 223*6db1b497SLorenzo Bianconi 224*6db1b497SLorenzo Bianconi #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 225*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 226*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 227*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_VERSION BIT(3) 228*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 229*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_MCAST BIT(5) 230*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_BCAST BIT(6) 231*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 232*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 233*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 234*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 235*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 236*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 237*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 238*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_CTS BIT(14) 239*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_RTS BIT(15) 240*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 241*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 242*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 243*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 244*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_NDPA BIT(20) 245*6db1b497SLorenzo Bianconi #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 246*6db1b497SLorenzo Bianconi 247*6db1b497SLorenzo Bianconi #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 248*6db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_ACK BIT(4) 249*6db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 250*6db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_BA BIT(6) 251*6db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_CFEND BIT(7) 252*6db1b497SLorenzo Bianconi #define MT_WF_RFCR1_DROP_CFACK BIT(8) 253*6db1b497SLorenzo Bianconi 254*6db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4) 255*6db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 256*6db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30) 257*6db1b497SLorenzo Bianconi 258*6db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8) 259*6db1b497SLorenzo Bianconi #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0) 260*6db1b497SLorenzo Bianconi #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 261*6db1b497SLorenzo Bianconi 262*6db1b497SLorenzo Bianconi /* WFDMA0 */ 263*6db1b497SLorenzo Bianconi #define MT_WFDMA0_BASE 0xd4000 264*6db1b497SLorenzo Bianconi #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 265*6db1b497SLorenzo Bianconi 266*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RST MT_WFDMA0(0x100) 267*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 268*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 269*6db1b497SLorenzo Bianconi 270*6db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 271*6db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 272*6db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 273*6db1b497SLorenzo Bianconi #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 274*6db1b497SLorenzo Bianconi 275*6db1b497SLorenzo Bianconi #define MT_MCU_CMD MT_WFDMA0(0x1f0) 276*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_WAKE_RX_PCIE BIT(0) 277*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 278*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_STOP_DMA BIT(2) 279*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_RESET_DONE BIT(3) 280*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 281*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_NORMAL_STATE BIT(5) 282*6db1b497SLorenzo Bianconi #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 283*6db1b497SLorenzo Bianconi 284*6db1b497SLorenzo Bianconi #define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4) 285*6db1b497SLorenzo Bianconi 286*6db1b497SLorenzo Bianconi #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200) 287*6db1b497SLorenzo Bianconi #define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */ 288*6db1b497SLorenzo Bianconi #define HOST_RX_DONE_INT_STS2 BIT(2) /* Rx data */ 289*6db1b497SLorenzo Bianconi #define HOST_RX_DONE_INT_STS4 BIT(22) /* Rx mcu after fw downloaded */ 290*6db1b497SLorenzo Bianconi #define HOST_TX_DONE_INT_STS16 BIT(26) 291*6db1b497SLorenzo Bianconi #define HOST_TX_DONE_INT_STS17 BIT(27) /* MCU tx done*/ 292*6db1b497SLorenzo Bianconi 293*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 294*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 295*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1) 296*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 297*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3) 298*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6) 299*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL BIT(9) 300*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) 301*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15) 302*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 303*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 304*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 305*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30) 306*6db1b497SLorenzo Bianconi 307*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 308*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RST_DRX_PTR MT_WFDMA0(0x280) 309*6db1b497SLorenzo Bianconi #define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 310*6db1b497SLorenzo Bianconi #define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE BIT(6) 311*6db1b497SLorenzo Bianconi #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 312*6db1b497SLorenzo Bianconi 313*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600) 314*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604) 315*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608) 316*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c) 317*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610) 318*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614) 319*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618) 320*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING15_EXT_CTRL MT_WFDMA0(0x63c) 321*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640) 322*6db1b497SLorenzo Bianconi #define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644) 323*6db1b497SLorenzo Bianconi 324*6db1b497SLorenzo Bianconi #define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0) 325*6db1b497SLorenzo Bianconi #define MT_WPDMA0_BASE_PTR_MASK GENMASK(31, 16) 326*6db1b497SLorenzo Bianconi 327*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680) 328*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684) 329*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688) 330*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c) 331*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690) 332*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694) 333*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING6_EXT_CTRL MT_WFDMA0(0x698) 334*6db1b497SLorenzo Bianconi #define MT_WFDMA0_RX_RING7_EXT_CTRL MT_WFDMA0(0x69c) 335*6db1b497SLorenzo Bianconi 336*6db1b497SLorenzo Bianconi #define MT_TX_RING_BASE MT_WFDMA0(0x300) 337*6db1b497SLorenzo Bianconi #define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500) 338*6db1b497SLorenzo Bianconi 339*6db1b497SLorenzo Bianconi /* WFDMA CSR */ 340*6db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR_BASE 0xd7000 341*6db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 342*6db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 343*6db1b497SLorenzo Bianconi #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 344*6db1b497SLorenzo Bianconi 345*6db1b497SLorenzo Bianconi #define MT_SWDEF_BASE 0x41f200 346*6db1b497SLorenzo Bianconi #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 347*6db1b497SLorenzo Bianconi #define MT_SWDEF_MODE MT_SWDEF(0x3c) 348*6db1b497SLorenzo Bianconi #define MT_SWDEF_NORMAL_MODE 0 349*6db1b497SLorenzo Bianconi #define MT_SWDEF_ICAP_MODE 1 350*6db1b497SLorenzo Bianconi #define MT_SWDEF_SPECTRUM_MODE 2 351*6db1b497SLorenzo Bianconi 352*6db1b497SLorenzo Bianconi #define MT_TOP_BASE 0x18060000 353*6db1b497SLorenzo Bianconi #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 354*6db1b497SLorenzo Bianconi 355*6db1b497SLorenzo Bianconi #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10) 356*6db1b497SLorenzo Bianconi #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 357*6db1b497SLorenzo Bianconi #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 358*6db1b497SLorenzo Bianconi 359*6db1b497SLorenzo Bianconi #define MT_TOP_MISC MT_TOP(0xf0) 360*6db1b497SLorenzo Bianconi #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 361*6db1b497SLorenzo Bianconi 362*6db1b497SLorenzo Bianconi #define MT_MCU_WPDMA0_BASE 0x54000000 363*6db1b497SLorenzo Bianconi #define MT_MCU_WPDMA0(ofs) (MT_MCU_WPDMA0_BASE + (ofs)) 364*6db1b497SLorenzo Bianconi 365*6db1b497SLorenzo Bianconi #define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120) 366*6db1b497SLorenzo Bianconi #define MT_WFDMA_NEED_REINIT BIT(1) 367*6db1b497SLorenzo Bianconi 368*6db1b497SLorenzo Bianconi #define MT_CBTOP_RGU(ofs) (0x70002000 + (ofs)) 369*6db1b497SLorenzo Bianconi #define MT_CBTOP_RGU_WF_SUBSYS_RST MT_CBTOP_RGU(0x600) 370*6db1b497SLorenzo Bianconi #define MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH BIT(0) 371*6db1b497SLorenzo Bianconi 372*6db1b497SLorenzo Bianconi #define MT_HW_BOUND 0x70010020 373*6db1b497SLorenzo Bianconi #define MT_HW_CHIPID 0x70010200 374*6db1b497SLorenzo Bianconi #define MT_HW_REV 0x70010204 375*6db1b497SLorenzo Bianconi 376*6db1b497SLorenzo Bianconi #define MT_PCIE_MAC_BASE 0x10000 377*6db1b497SLorenzo Bianconi #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 378*6db1b497SLorenzo Bianconi #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 379*6db1b497SLorenzo Bianconi #define MT_PCIE_MAC_PM MT_PCIE_MAC(0x194) 380*6db1b497SLorenzo Bianconi #define MT_PCIE_MAC_PM_L0S_DIS BIT(8) 381*6db1b497SLorenzo Bianconi 382*6db1b497SLorenzo Bianconi #define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs)) 383*6db1b497SLorenzo Bianconi #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004) 384*6db1b497SLorenzo Bianconi #define MT_DMASHDL_DMASHDL_BYPASS BIT(28) 385*6db1b497SLorenzo Bianconi #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008) 386*6db1b497SLorenzo Bianconi #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c) 387*6db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_SEQ_ORDER BIT(16) 388*6db1b497SLorenzo Bianconi #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010) 389*6db1b497SLorenzo Bianconi #define MT_DMASHDL_REFILL_MASK GENMASK(31, 16) 390*6db1b497SLorenzo Bianconi #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c) 391*6db1b497SLorenzo Bianconi #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0) 392*6db1b497SLorenzo Bianconi #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16) 393*6db1b497SLorenzo Bianconi 394*6db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2)) 395*6db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0) 396*6db1b497SLorenzo Bianconi #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16) 397*6db1b497SLorenzo Bianconi 398*6db1b497SLorenzo Bianconi #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2)) 399*6db1b497SLorenzo Bianconi #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0) 400*6db1b497SLorenzo Bianconi #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8)) 401*6db1b497SLorenzo Bianconi 402*6db1b497SLorenzo Bianconi #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2)) 403*6db1b497SLorenzo Bianconi 404*6db1b497SLorenzo Bianconi #define MT_WFDMA_HOST_CONFIG 0x7c027030 405*6db1b497SLorenzo Bianconi #define MT_WFDMA_HOST_CONFIG_USB_RXEVT_EP4_EN BIT(6) 406*6db1b497SLorenzo Bianconi 407*6db1b497SLorenzo Bianconi #define MT_UMAC(ofs) (0x74000000 + (ofs)) 408*6db1b497SLorenzo Bianconi #define MT_UDMA_TX_QSEL MT_UMAC(0x008) 409*6db1b497SLorenzo Bianconi #define MT_FW_DL_EN BIT(3) 410*6db1b497SLorenzo Bianconi 411*6db1b497SLorenzo Bianconi #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c) 412*6db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0) 413*6db1b497SLorenzo Bianconi #define MT_WL_TX_TMOUT_LMT GENMASK(27, 8) 414*6db1b497SLorenzo Bianconi 415*6db1b497SLorenzo Bianconi #define MT_UDMA_WLCFG_0 MT_UMAC(0x18) 416*6db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_TO GENMASK(7, 0) 417*6db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_LMT GENMASK(15, 8) 418*6db1b497SLorenzo Bianconi #define MT_WL_TX_TMOUT_FUNC_EN BIT(16) 419*6db1b497SLorenzo Bianconi #define MT_WL_TX_DPH_CHK_EN BIT(17) 420*6db1b497SLorenzo Bianconi #define MT_WL_RX_MPSZ_PAD0 BIT(18) 421*6db1b497SLorenzo Bianconi #define MT_WL_RX_FLUSH BIT(19) 422*6db1b497SLorenzo Bianconi #define MT_TICK_1US_EN BIT(20) 423*6db1b497SLorenzo Bianconi #define MT_WL_RX_AGG_EN BIT(21) 424*6db1b497SLorenzo Bianconi #define MT_WL_RX_EN BIT(22) 425*6db1b497SLorenzo Bianconi #define MT_WL_TX_EN BIT(23) 426*6db1b497SLorenzo Bianconi #define MT_WL_RX_BUSY BIT(30) 427*6db1b497SLorenzo Bianconi #define MT_WL_TX_BUSY BIT(31) 428*6db1b497SLorenzo Bianconi 429*6db1b497SLorenzo Bianconi #define MT_UDMA_CONN_INFRA_STATUS MT_UMAC(0xa20) 430*6db1b497SLorenzo Bianconi #define MT_UDMA_CONN_WFSYS_INIT_DONE BIT(22) 431*6db1b497SLorenzo Bianconi #define MT_UDMA_CONN_INFRA_STATUS_SEL MT_UMAC(0xa24) 432*6db1b497SLorenzo Bianconi 433*6db1b497SLorenzo Bianconi #define MT_SSUSB_EPCTL_CSR(ofs) (0x74011800 + (ofs)) 434*6db1b497SLorenzo Bianconi #define MT_SSUSB_EPCTL_CSR_EP_RST_OPT MT_SSUSB_EPCTL_CSR(0x090) 435*6db1b497SLorenzo Bianconi 436*6db1b497SLorenzo Bianconi #define MT_UWFDMA0(ofs) (0x7c024000 + (ofs)) 437*6db1b497SLorenzo Bianconi #define MT_UWFDMA0_GLO_CFG MT_UWFDMA0(0x208) 438*6db1b497SLorenzo Bianconi #define MT_UWFDMA0_GLO_CFG_EXT0 MT_UWFDMA0(0x2b0) 439*6db1b497SLorenzo Bianconi #define MT_UWFDMA0_GLO_CFG_EXT1 MT_UWFDMA0(0x2b4) 440*6db1b497SLorenzo Bianconi #define MT_UWFDMA0_TX_RING_EXT_CTRL(_n) MT_UWFDMA0(0x600 + ((_n) << 2)) 441*6db1b497SLorenzo Bianconi 442*6db1b497SLorenzo Bianconi #define MT_CONN_STATUS 0x7c053c10 443*6db1b497SLorenzo Bianconi #define MT_WIFI_PATCH_DL_STATE BIT(0) 444*6db1b497SLorenzo Bianconi 445*6db1b497SLorenzo Bianconi #define MT_CONN_ON_LPCTL 0x7c060010 446*6db1b497SLorenzo Bianconi #define PCIE_LPCR_HOST_SET_OWN BIT(0) 447*6db1b497SLorenzo Bianconi #define PCIE_LPCR_HOST_CLR_OWN BIT(1) 448*6db1b497SLorenzo Bianconi #define PCIE_LPCR_HOST_OWN_SYNC BIT(2) 449*6db1b497SLorenzo Bianconi 450*6db1b497SLorenzo Bianconi #define MT_CONN_ON_MISC 0x7c0600f0 451*6db1b497SLorenzo Bianconi #define MT_TOP_MISC2_FW_PWR_ON BIT(0) 452*6db1b497SLorenzo Bianconi #define MT_TOP_MISC2_FW_N9_ON BIT(1) 453*6db1b497SLorenzo Bianconi #define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0) 454*6db1b497SLorenzo Bianconi 455*6db1b497SLorenzo Bianconi #define MT_WF_SW_DEF_CR(ofs) (0x401a00 + (ofs)) 456*6db1b497SLorenzo Bianconi #define MT_WF_SW_DEF_CR_USB_MCU_EVENT MT_WF_SW_DEF_CR(0x028) 457*6db1b497SLorenzo Bianconi #define MT_WF_SW_SER_TRIGGER_SUSPEND BIT(6) 458*6db1b497SLorenzo Bianconi #define MT_WF_SW_SER_DONE_SUSPEND BIT(7) 459*6db1b497SLorenzo Bianconi 460*6db1b497SLorenzo Bianconi #endif /* __MT792X_REGS_H */ 461