1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7921_REGS_H 5 #define __MT7921_REGS_H 6 7 /* MCU WFDMA1 */ 8 #define MT_MCU_WFDMA1_BASE 0x3000 9 #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 10 11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108) 12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 13 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 14 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 15 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 16 17 #define MT_PLE_BASE 0x8000 18 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 19 20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0) 21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4) 22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8) 23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc) 24 25 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \ 26 ((n) << 2)) 27 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 28 29 #define MT_MDP_BASE 0xf000 30 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 31 32 #define MT_MDP_DCR0 MT_MDP(0x000) 33 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 34 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19) 35 36 #define MT_MDP_DCR1 MT_MDP(0x004) 37 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 38 39 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8)) 40 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 41 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 42 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 43 44 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8)) 45 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 46 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 47 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 48 #define MT_MDP_TO_HIF 0 49 #define MT_MDP_TO_WM 1 50 51 /* TMAC: band 0(0x21000), band 1(0xa1000) */ 52 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000) 53 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 54 55 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 56 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 57 58 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090) 59 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094) 60 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 61 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 62 63 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4) 64 #define MT_IFS_EIFS GENMASK(8, 0) 65 #define MT_IFS_RIFS GENMASK(14, 10) 66 #define MT_IFS_SIFS GENMASK(22, 16) 67 #define MT_IFS_SLOT GENMASK(30, 24) 68 69 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4) 70 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 71 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 72 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 73 74 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c) 75 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0) 76 77 #define MT_WF_DMA_BASE(_band) ((_band) ? 0xa1e00 : 0x21e00) 78 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 79 80 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 81 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 82 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 83 84 /* LPON: band 0(0x24200), band 1(0xa4200) */ 85 #define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200) 86 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 87 88 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080) 89 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084) 90 91 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4) 92 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 93 #define MT_LPON_TCR_SW_WRITE BIT(0) 94 95 /* MIB: band 0(0x24800), band 1(0xa4800) */ 96 #define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800) 97 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 98 99 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014) 100 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 101 102 #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) 103 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) 104 105 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) 106 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) 107 108 #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090) 109 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 110 111 #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098) 112 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) 113 #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c) 114 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) 115 116 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0) 117 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4) 118 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc) 119 120 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) 121 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 122 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 123 124 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4)) 125 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 126 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 127 128 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4)) 129 #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0) 130 131 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2)) 132 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2)) 133 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2)) 134 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 135 136 #define MT_WTBLON_TOP_BASE 0x34000 137 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 138 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0) 139 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 140 141 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030) 142 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 143 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 144 #define MT_WTBL_UPDATE_BUSY BIT(31) 145 146 #define MT_WTBL_BASE 0x38000 147 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 148 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 149 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 150 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 151 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 152 153 /* AGG: band 0(0x20800), band 1(0xa0800) */ 154 #define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800) 155 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 156 157 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4) 158 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4) 159 #define MT_AGG_PCR0_MM_PROT BIT(0) 160 #define MT_AGG_PCR0_GF_PROT BIT(1) 161 #define MT_AGG_PCR0_BW20_PROT BIT(2) 162 #define MT_AGG_PCR0_BW40_PROT BIT(4) 163 #define MT_AGG_PCR0_BW80_PROT BIT(6) 164 #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 165 #define MT_AGG_PCR0_VHT_PROT BIT(13) 166 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 167 168 #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 169 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 170 171 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084) 172 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 173 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 174 175 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098) 176 #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 177 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 178 #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 179 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 180 181 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0) 182 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4) 183 184 /* ARB: band 0(0x20c00), band 1(0xa0c00) */ 185 #define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00) 186 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 187 188 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080) 189 #define MT_ARB_SCR_TX_DISABLE BIT(8) 190 #define MT_ARB_SCR_RX_DISABLE BIT(9) 191 192 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4) 193 194 /* RMAC: band 0(0x21400), band 1(0xa1400) */ 195 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400) 196 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 197 198 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 199 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 200 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 201 #define MT_WF_RFCR_DROP_VERSION BIT(3) 202 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 203 #define MT_WF_RFCR_DROP_MCAST BIT(5) 204 #define MT_WF_RFCR_DROP_BCAST BIT(6) 205 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 206 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 207 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 208 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 209 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 210 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 211 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 212 #define MT_WF_RFCR_DROP_CTS BIT(14) 213 #define MT_WF_RFCR_DROP_RTS BIT(15) 214 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 215 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 216 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 217 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 218 #define MT_WF_RFCR_DROP_NDPA BIT(20) 219 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 220 221 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 222 #define MT_WF_RFCR1_DROP_ACK BIT(4) 223 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 224 #define MT_WF_RFCR1_DROP_BA BIT(6) 225 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 226 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 227 228 #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4) 229 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 230 #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30) 231 232 #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8) 233 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0) 234 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 235 236 /* WFDMA0 */ 237 #define MT_WFDMA0_BASE 0xd4000 238 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 239 240 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 241 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 242 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 243 244 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 245 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 246 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 247 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 248 249 #define MT_MCU_CMD MT_WFDMA0(0x1f0) 250 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 251 #define MT_MCU_CMD_STOP_DMA BIT(2) 252 #define MT_MCU_CMD_RESET_DONE BIT(3) 253 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 254 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 255 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 256 257 #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200) 258 #define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */ 259 #define HOST_RX_DONE_INT_STS2 BIT(2) /* Rx data */ 260 #define HOST_RX_DONE_INT_STS4 BIT(22) /* Rx mcu after fw downloaded */ 261 #define HOST_TX_DONE_INT_STS16 BIT(26) 262 #define HOST_TX_DONE_INT_STS17 BIT(27) /* MCU tx done*/ 263 264 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204) 265 #define HOST_RX_DONE_INT_ENA0 BIT(0) 266 #define HOST_RX_DONE_INT_ENA1 BIT(1) 267 #define HOST_RX_DONE_INT_ENA2 BIT(2) 268 #define HOST_RX_DONE_INT_ENA3 BIT(3) 269 #define HOST_TX_DONE_INT_ENA0 BIT(4) 270 #define HOST_TX_DONE_INT_ENA1 BIT(5) 271 #define HOST_TX_DONE_INT_ENA2 BIT(6) 272 #define HOST_TX_DONE_INT_ENA3 BIT(7) 273 #define HOST_TX_DONE_INT_ENA4 BIT(8) 274 #define HOST_TX_DONE_INT_ENA5 BIT(9) 275 #define HOST_TX_DONE_INT_ENA6 BIT(10) 276 #define HOST_TX_DONE_INT_ENA7 BIT(11) 277 #define HOST_TX_DONE_INT_ENA8 BIT(12) 278 #define HOST_TX_DONE_INT_ENA9 BIT(13) 279 #define HOST_TX_DONE_INT_ENA10 BIT(14) 280 #define HOST_TX_DONE_INT_ENA11 BIT(15) 281 #define HOST_TX_DONE_INT_ENA12 BIT(16) 282 #define HOST_TX_DONE_INT_ENA13 BIT(17) 283 #define HOST_TX_DONE_INT_ENA14 BIT(18) 284 #define HOST_RX_COHERENT_EN BIT(20) 285 #define HOST_TX_COHERENT_EN BIT(21) 286 #define HOST_RX_DONE_INT_ENA4 BIT(22) 287 #define HOST_RX_DONE_INT_ENA5 BIT(23) 288 #define HOST_TX_DONE_INT_ENA16 BIT(26) 289 #define HOST_TX_DONE_INT_ENA17 BIT(27) 290 #define MCU2HOST_SW_INT_ENA BIT(29) 291 #define HOST_TX_DONE_INT_ENA18 BIT(30) 292 293 /* WFDMA interrupt */ 294 #define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2 295 #define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0 296 #define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA4 297 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \ 298 MT_INT_RX_DONE_WM | \ 299 MT_INT_RX_DONE_WM2) 300 #define MT_INT_TX_DONE_MCU_WM HOST_TX_DONE_INT_ENA17 301 #define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16 302 #define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0 303 #define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA 304 305 #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \ 306 MT_INT_TX_DONE_FWDL) 307 #define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \ 308 MT_INT_TX_DONE_BAND0 | \ 309 GENMASK(18, 4)) 310 311 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 312 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 313 #define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1) 314 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 315 #define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3) 316 #define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6) 317 #define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) 318 #define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15) 319 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 320 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 321 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 322 #define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30) 323 324 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 325 #define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 326 #define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE BIT(6) 327 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 328 329 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520) 330 331 #define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600) 332 #define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604) 333 #define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608) 334 #define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c) 335 #define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610) 336 #define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614) 337 #define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618) 338 #define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640) 339 #define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644) 340 341 #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680) 342 #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684) 343 #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688) 344 #define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c) 345 #define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690) 346 #define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694) 347 348 #define MT_TX_RING_BASE MT_WFDMA0(0x300) 349 #define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500) 350 351 /* WFDMA CSR */ 352 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 353 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 354 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 355 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 356 357 #define MT_INFRA_CFG_BASE 0xfe000 358 #define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs)) 359 360 #define MT_HIF_REMAP_L1 MT_INFRA(0x260) 361 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 362 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 363 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 364 #define MT_HIF_REMAP_BASE_L1 0xe0000 365 366 #define MT_SWDEF_BASE 0x41f200 367 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 368 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 369 #define MT_SWDEF_NORMAL_MODE 0 370 #define MT_SWDEF_ICAP_MODE 1 371 #define MT_SWDEF_SPECTRUM_MODE 2 372 373 #define MT_TOP_BASE 0x18060000 374 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 375 376 #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10) 377 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 378 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 379 380 #define MT_TOP_MISC MT_TOP(0xf0) 381 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 382 383 #define MT_HW_BOUND 0x70010020 384 #define MT_HW_CHIPID 0x70010200 385 #define MT_HW_REV 0x70010204 386 387 #define MT_PCIE_MAC_BASE 0x74030000 388 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 389 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 390 391 #define MT_DMA_SHDL(ofs) (0xd6000 + (ofs)) 392 #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004) 393 #define MT_DMASHDL_DMASHDL_BYPASS BIT(28) 394 #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008) 395 #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c) 396 #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010) 397 #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c) 398 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0) 399 #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16) 400 401 #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2)) 402 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0) 403 #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16) 404 405 #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2)) 406 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0) 407 #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8)) 408 409 #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2)) 410 411 #define MT_CONN_ON_LPCTL 0x7c060010 412 #define PCIE_LPCR_HOST_OWN_SYNC BIT(2) 413 #define PCIE_LPCR_HOST_CLR_OWN BIT(1) 414 #define PCIE_LPCR_HOST_SET_OWN BIT(0) 415 416 #define MT_CONN_ON_MISC 0x7c0600f0 417 #define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0) 418 419 #endif 420