1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7921_REGS_H 5 #define __MT7921_REGS_H 6 7 /* MCU WFDMA1 */ 8 #define MT_MCU_WFDMA1_BASE 0x3000 9 #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 10 11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108) 12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 13 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 14 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 15 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 16 17 #define MT_PLE_BASE 0x820c0000 18 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 19 20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0) 21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4) 22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8) 23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec) 24 25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n)) 26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 27 28 #define MT_MDP_BASE 0x820cd000 29 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 30 31 #define MT_MDP_DCR0 MT_MDP(0x000) 32 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 33 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19) 34 35 #define MT_MDP_DCR1 MT_MDP(0x004) 36 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 37 38 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8)) 39 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 40 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 41 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 42 43 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8)) 44 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 45 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 46 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 47 #define MT_MDP_TO_HIF 0 48 #define MT_MDP_TO_WM 1 49 50 /* TMAC: band 0(0x21000), band 1(0xa1000) */ 51 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 52 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 53 54 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 55 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 56 57 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090) 58 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094) 59 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 60 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 61 62 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4) 63 #define MT_IFS_EIFS GENMASK(8, 0) 64 #define MT_IFS_RIFS GENMASK(14, 10) 65 #define MT_IFS_SIFS GENMASK(22, 16) 66 #define MT_IFS_SLOT GENMASK(30, 24) 67 68 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4) 69 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 70 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 71 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 72 73 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c) 74 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0) 75 76 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 77 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 78 79 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 80 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 81 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 82 83 /* LPON: band 0(0x24200), band 1(0xa4200) */ 84 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 85 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 86 87 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080) 88 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084) 89 90 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4) 91 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 92 #define MT_LPON_TCR_SW_WRITE BIT(0) 93 94 /* ETBF: band 0(0x24000), band 1(0xa4000) */ 95 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 96 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 97 98 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x150) 99 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 100 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 101 102 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x158) 103 #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 104 #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 105 #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 106 #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 107 108 /* MIB: band 0(0x24800), band 1(0xa4800) */ 109 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 110 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 111 112 #define MT_MIB_SCR1(_band) MT_WF_MIB(_band, 0x004) 113 #define MT_MIB_TXDUR_EN BIT(8) 114 #define MT_MIB_RXDUR_EN BIT(9) 115 116 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x698) 117 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(31, 16) 118 119 #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x780) 120 121 #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) 122 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) 123 124 #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, 0x558) 125 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x564) 126 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x568) 127 128 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) 129 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) 130 131 #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, 0x770) 132 #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, 0x774) 133 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, 0x55c) 134 135 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, 0x7a8) 136 #define MT_MIB_SDR9_IBF_CNT_MASK GENMASK(31, 16) 137 #define MT_MIB_SDR9_EBF_CNT_MASK GENMASK(15, 0) 138 139 #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090) 140 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 141 142 #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x054) 143 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) 144 #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x058) 145 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) 146 147 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0) 148 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4) 149 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc) 150 151 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) 152 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 153 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 154 155 #define MT_MIB_MB_BSDR0(_band) MT_WF_MIB(_band, 0x688) 156 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 157 #define MT_MIB_MB_BSDR1(_band) MT_WF_MIB(_band, 0x690) 158 #define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0) 159 #define MT_MIB_MB_BSDR2(_band) MT_WF_MIB(_band, 0x518) 160 #define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0) 161 #define MT_MIB_MB_BSDR3(_band) MT_WF_MIB(_band, 0x520) 162 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0) 163 164 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4)) 165 #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0) 166 167 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x7dc + ((n) << 2)) 168 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x7ec + ((n) << 2)) 169 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2)) 170 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 171 172 #define MT_WTBLON_TOP_BASE 0x820d4000 173 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 174 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x200) 175 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 176 177 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x230) 178 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 179 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 180 #define MT_WTBL_UPDATE_BUSY BIT(31) 181 182 #define MT_WTBL_BASE 0x820d8000 183 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 184 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 185 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 186 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 187 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 188 189 /* AGG: band 0(0x20800), band 1(0xa0800) */ 190 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 191 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 192 193 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4) 194 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4) 195 #define MT_AGG_PCR0_MM_PROT BIT(0) 196 #define MT_AGG_PCR0_GF_PROT BIT(1) 197 #define MT_AGG_PCR0_BW20_PROT BIT(2) 198 #define MT_AGG_PCR0_BW40_PROT BIT(4) 199 #define MT_AGG_PCR0_BW80_PROT BIT(6) 200 #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 201 #define MT_AGG_PCR0_VHT_PROT BIT(13) 202 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 203 204 #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 205 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 206 207 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084) 208 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 209 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 210 211 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098) 212 #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 213 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 214 #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 215 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 216 217 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0) 218 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4) 219 220 /* ARB: band 0(0x20c00), band 1(0xa0c00) */ 221 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 222 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 223 224 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080) 225 #define MT_ARB_SCR_TX_DISABLE BIT(8) 226 #define MT_ARB_SCR_RX_DISABLE BIT(9) 227 228 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4) 229 230 /* RMAC: band 0(0x21400), band 1(0xa1400) */ 231 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 232 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 233 234 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 235 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 236 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 237 #define MT_WF_RFCR_DROP_VERSION BIT(3) 238 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 239 #define MT_WF_RFCR_DROP_MCAST BIT(5) 240 #define MT_WF_RFCR_DROP_BCAST BIT(6) 241 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 242 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 243 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 244 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 245 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 246 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 247 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 248 #define MT_WF_RFCR_DROP_CTS BIT(14) 249 #define MT_WF_RFCR_DROP_RTS BIT(15) 250 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 251 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 252 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 253 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 254 #define MT_WF_RFCR_DROP_NDPA BIT(20) 255 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 256 257 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 258 #define MT_WF_RFCR1_DROP_ACK BIT(4) 259 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 260 #define MT_WF_RFCR1_DROP_BA BIT(6) 261 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 262 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 263 264 #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4) 265 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 266 #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30) 267 268 #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8) 269 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0) 270 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 271 272 /* WFDMA0 */ 273 #define MT_WFDMA0_BASE 0xd4000 274 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 275 276 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 277 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 278 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 279 280 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 281 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 282 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 283 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 284 285 #define MT_MCU_CMD MT_WFDMA0(0x1f0) 286 #define MT_MCU_CMD_WAKE_RX_PCIE BIT(0) 287 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 288 #define MT_MCU_CMD_STOP_DMA BIT(2) 289 #define MT_MCU_CMD_RESET_DONE BIT(3) 290 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 291 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 292 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 293 294 #define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4) 295 296 #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200) 297 #define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */ 298 #define HOST_RX_DONE_INT_STS2 BIT(2) /* Rx data */ 299 #define HOST_RX_DONE_INT_STS4 BIT(22) /* Rx mcu after fw downloaded */ 300 #define HOST_TX_DONE_INT_STS16 BIT(26) 301 #define HOST_TX_DONE_INT_STS17 BIT(27) /* MCU tx done*/ 302 303 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204) 304 #define HOST_RX_DONE_INT_ENA0 BIT(0) 305 #define HOST_RX_DONE_INT_ENA1 BIT(1) 306 #define HOST_RX_DONE_INT_ENA2 BIT(2) 307 #define HOST_RX_DONE_INT_ENA3 BIT(3) 308 #define HOST_TX_DONE_INT_ENA0 BIT(4) 309 #define HOST_TX_DONE_INT_ENA1 BIT(5) 310 #define HOST_TX_DONE_INT_ENA2 BIT(6) 311 #define HOST_TX_DONE_INT_ENA3 BIT(7) 312 #define HOST_TX_DONE_INT_ENA4 BIT(8) 313 #define HOST_TX_DONE_INT_ENA5 BIT(9) 314 #define HOST_TX_DONE_INT_ENA6 BIT(10) 315 #define HOST_TX_DONE_INT_ENA7 BIT(11) 316 #define HOST_TX_DONE_INT_ENA8 BIT(12) 317 #define HOST_TX_DONE_INT_ENA9 BIT(13) 318 #define HOST_TX_DONE_INT_ENA10 BIT(14) 319 #define HOST_TX_DONE_INT_ENA11 BIT(15) 320 #define HOST_TX_DONE_INT_ENA12 BIT(16) 321 #define HOST_TX_DONE_INT_ENA13 BIT(17) 322 #define HOST_TX_DONE_INT_ENA14 BIT(18) 323 #define HOST_RX_COHERENT_EN BIT(20) 324 #define HOST_TX_COHERENT_EN BIT(21) 325 #define HOST_RX_DONE_INT_ENA4 BIT(22) 326 #define HOST_RX_DONE_INT_ENA5 BIT(23) 327 #define HOST_TX_DONE_INT_ENA16 BIT(26) 328 #define HOST_TX_DONE_INT_ENA17 BIT(27) 329 #define MCU2HOST_SW_INT_ENA BIT(29) 330 #define HOST_TX_DONE_INT_ENA18 BIT(30) 331 332 /* WFDMA interrupt */ 333 #define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2 334 #define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0 335 #define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA4 336 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \ 337 MT_INT_RX_DONE_WM | \ 338 MT_INT_RX_DONE_WM2) 339 #define MT_INT_TX_DONE_MCU_WM HOST_TX_DONE_INT_ENA17 340 #define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16 341 #define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0 342 #define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA 343 344 #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \ 345 MT_INT_TX_DONE_FWDL) 346 #define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \ 347 MT_INT_TX_DONE_BAND0 | \ 348 GENMASK(18, 4)) 349 350 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 351 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 352 #define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1) 353 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 354 #define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3) 355 #define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6) 356 #define MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL BIT(9) 357 #define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) 358 #define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15) 359 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 360 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 361 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 362 #define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30) 363 364 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 365 #define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 366 #define MT_WFDMA0_CSR_TX_DMASHDL_ENABLE BIT(6) 367 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 368 369 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520) 370 371 #define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600) 372 #define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604) 373 #define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608) 374 #define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c) 375 #define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610) 376 #define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614) 377 #define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618) 378 #define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640) 379 #define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644) 380 381 #define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0) 382 #define MT_WPDMA0_BASE_PTR_MASK GENMASK(31, 16) 383 384 #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680) 385 #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684) 386 #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688) 387 #define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c) 388 #define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690) 389 #define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694) 390 391 #define MT_TX_RING_BASE MT_WFDMA0(0x300) 392 #define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500) 393 394 /* WFDMA CSR */ 395 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 396 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 397 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 398 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 399 400 #define MT_INFRA_CFG_BASE 0xfe000 401 #define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs)) 402 403 #define MT_HIF_REMAP_L1 MT_INFRA(0x24c) 404 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 405 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 406 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 407 #define MT_HIF_REMAP_BASE_L1 0x40000 408 409 #define MT_SWDEF_BASE 0x41f200 410 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 411 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 412 #define MT_SWDEF_NORMAL_MODE 0 413 #define MT_SWDEF_ICAP_MODE 1 414 #define MT_SWDEF_SPECTRUM_MODE 2 415 416 #define MT_TOP_BASE 0x18060000 417 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 418 419 #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10) 420 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 421 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 422 423 #define MT_TOP_MISC MT_TOP(0xf0) 424 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 425 426 #define MT_MCU_WPDMA0_BASE 0x54000000 427 #define MT_MCU_WPDMA0(ofs) (MT_MCU_WPDMA0_BASE + (ofs)) 428 429 #define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120) 430 #define MT_WFDMA_NEED_REINIT BIT(1) 431 432 #define MT_CBTOP_RGU(ofs) (0x70002000 + (ofs)) 433 #define MT_CBTOP_RGU_WF_SUBSYS_RST MT_CBTOP_RGU(0x600) 434 #define MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH BIT(0) 435 436 #define MT_HW_BOUND 0x70010020 437 #define MT_HW_CHIPID 0x70010200 438 #define MT_HW_REV 0x70010204 439 440 #define MT_PCIE_MAC_BASE 0x10000 441 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 442 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 443 444 #define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs)) 445 #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004) 446 #define MT_DMASHDL_DMASHDL_BYPASS BIT(28) 447 #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008) 448 #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c) 449 #define MT_DMASHDL_GROUP_SEQ_ORDER BIT(16) 450 #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010) 451 #define MT_DMASHDL_REFILL_MASK GENMASK(31, 16) 452 #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c) 453 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0) 454 #define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16) 455 456 #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2)) 457 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0) 458 #define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16) 459 460 #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2)) 461 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0) 462 #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8)) 463 464 #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2)) 465 466 #define MT_WFDMA_HOST_CONFIG 0x7c027030 467 #define MT_WFDMA_HOST_CONFIG_USB_RXEVT_EP4_EN BIT(6) 468 469 #define MT_UMAC(ofs) (0x74000000 + (ofs)) 470 #define MT_UDMA_TX_QSEL MT_UMAC(0x008) 471 #define MT_FW_DL_EN BIT(3) 472 473 #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c) 474 #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0) 475 #define MT_WL_TX_TMOUT_LMT GENMASK(27, 8) 476 477 #define MT_UDMA_WLCFG_0 MT_UMAC(0x18) 478 #define MT_WL_RX_AGG_TO GENMASK(7, 0) 479 #define MT_WL_RX_AGG_LMT GENMASK(15, 8) 480 #define MT_WL_TX_TMOUT_FUNC_EN BIT(16) 481 #define MT_WL_TX_DPH_CHK_EN BIT(17) 482 #define MT_WL_RX_MPSZ_PAD0 BIT(18) 483 #define MT_WL_RX_FLUSH BIT(19) 484 #define MT_TICK_1US_EN BIT(20) 485 #define MT_WL_RX_AGG_EN BIT(21) 486 #define MT_WL_RX_EN BIT(22) 487 #define MT_WL_TX_EN BIT(23) 488 #define MT_WL_RX_BUSY BIT(30) 489 #define MT_WL_TX_BUSY BIT(31) 490 491 #define MT_UDMA_CONN_INFRA_STATUS MT_UMAC(0xa20) 492 #define MT_UDMA_CONN_WFSYS_INIT_DONE BIT(22) 493 #define MT_UDMA_CONN_INFRA_STATUS_SEL MT_UMAC(0xa24) 494 495 #define MT_SSUSB_EPCTL_CSR(ofs) (0x74011800 + (ofs)) 496 #define MT_SSUSB_EPCTL_CSR_EP_RST_OPT MT_SSUSB_EPCTL_CSR(0x090) 497 498 #define MT_UWFDMA0(ofs) (0x7c024000 + (ofs)) 499 #define MT_UWFDMA0_GLO_CFG MT_UWFDMA0(0x208) 500 #define MT_UWFDMA0_GLO_CFG_EXT0 MT_UWFDMA0(0x2b0) 501 #define MT_UWFDMA0_TX_RING_EXT_CTRL(_n) MT_UWFDMA0(0x600 + ((_n) << 2)) 502 503 #define MT_CONN_STATUS 0x7c053c10 504 #define MT_WIFI_PATCH_DL_STATE BIT(0) 505 506 #define MT_CONN_ON_LPCTL 0x7c060010 507 #define PCIE_LPCR_HOST_OWN_SYNC BIT(2) 508 #define PCIE_LPCR_HOST_CLR_OWN BIT(1) 509 #define PCIE_LPCR_HOST_SET_OWN BIT(0) 510 511 #define MT_WFSYS_SW_RST_B 0x18000140 512 #define WFSYS_SW_RST_B BIT(0) 513 #define WFSYS_SW_INIT_DONE BIT(4) 514 515 #define MT_CONN_ON_MISC 0x7c0600f0 516 #define MT_TOP_MISC2_FW_PWR_ON BIT(0) 517 #define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0) 518 519 #endif 520