1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 10 #include "mt7921.h" 11 #include "mac.h" 12 #include "mcu.h" 13 #include "../trace.h" 14 15 static const struct pci_device_id mt7921_pci_device_table[] = { 16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) }, 17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) }, 18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) }, 19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) }, 20 { }, 21 }; 22 23 static bool mt7921_disable_aspm; 24 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 25 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 26 27 static void 28 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 29 { 30 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 31 32 if (q == MT_RXQ_MAIN) 33 mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA); 34 else if (q == MT_RXQ_MCU_WA) 35 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2); 36 else 37 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM); 38 } 39 40 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance) 41 { 42 struct mt7921_dev *dev = dev_instance; 43 44 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 45 46 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 47 return IRQ_NONE; 48 49 tasklet_schedule(&dev->irq_tasklet); 50 51 return IRQ_HANDLED; 52 } 53 54 static void mt7921_irq_tasklet(unsigned long data) 55 { 56 struct mt7921_dev *dev = (struct mt7921_dev *)data; 57 u32 intr, mask = 0; 58 59 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 60 61 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA); 62 intr &= dev->mt76.mmio.irqmask; 63 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr); 64 65 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 66 67 mask |= intr & MT_INT_RX_DONE_ALL; 68 if (intr & MT_INT_TX_DONE_MCU) 69 mask |= MT_INT_TX_DONE_MCU; 70 71 if (intr & MT_INT_MCU_CMD) { 72 u32 intr_sw; 73 74 intr_sw = mt76_rr(dev, MT_MCU_CMD); 75 /* ack MCU2HOST_SW_INT_STA */ 76 mt76_wr(dev, MT_MCU_CMD, intr_sw); 77 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) { 78 mask |= MT_INT_RX_DONE_DATA; 79 intr |= MT_INT_RX_DONE_DATA; 80 } 81 } 82 83 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0); 84 85 if (intr & MT_INT_TX_DONE_ALL) 86 napi_schedule(&dev->mt76.tx_napi); 87 88 if (intr & MT_INT_RX_DONE_WM) 89 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 90 91 if (intr & MT_INT_RX_DONE_WM2) 92 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 93 94 if (intr & MT_INT_RX_DONE_DATA) 95 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 96 } 97 98 static int mt7921e_init_reset(struct mt7921_dev *dev) 99 { 100 return mt7921_wpdma_reset(dev, true); 101 } 102 103 static void mt7921e_unregister_device(struct mt7921_dev *dev) 104 { 105 int i; 106 struct mt76_connac_pm *pm = &dev->pm; 107 108 cancel_work_sync(&dev->init_work); 109 mt76_unregister_device(&dev->mt76); 110 mt76_for_each_q_rx(&dev->mt76, i) 111 napi_disable(&dev->mt76.napi[i]); 112 cancel_delayed_work_sync(&pm->ps_work); 113 cancel_work_sync(&pm->wake_work); 114 115 mt7921_tx_token_put(dev); 116 mt7921_mcu_drv_pmctrl(dev); 117 mt7921_dma_cleanup(dev); 118 mt7921_wfsys_reset(dev); 119 mt7921_mcu_exit(dev); 120 121 tasklet_disable(&dev->irq_tasklet); 122 } 123 124 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr) 125 { 126 static const struct { 127 u32 phys; 128 u32 mapped; 129 u32 size; 130 } fixed_map[] = { 131 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 132 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 133 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 134 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 135 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 136 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 137 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 138 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 139 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 140 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 141 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 142 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 143 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 144 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 145 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 146 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 147 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 148 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 149 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 150 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 151 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 152 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 153 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ 154 { 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */ 155 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 156 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 157 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 158 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 159 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 160 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 161 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 162 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 163 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 164 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 165 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 166 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 167 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 168 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 169 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 170 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 171 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 172 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 173 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 174 }; 175 int i; 176 177 if (addr < 0x100000) 178 return addr; 179 180 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 181 u32 ofs; 182 183 if (addr < fixed_map[i].phys) 184 continue; 185 186 ofs = addr - fixed_map[i].phys; 187 if (ofs > fixed_map[i].size) 188 continue; 189 190 return fixed_map[i].mapped + ofs; 191 } 192 193 if ((addr >= 0x18000000 && addr < 0x18c00000) || 194 (addr >= 0x70000000 && addr < 0x78000000) || 195 (addr >= 0x7c000000 && addr < 0x7c400000)) 196 return mt7921_reg_map_l1(dev, addr); 197 198 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 199 addr); 200 201 return 0; 202 } 203 204 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 205 { 206 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 207 u32 addr = __mt7921_reg_addr(dev, offset); 208 209 return dev->bus_ops->rr(mdev, addr); 210 } 211 212 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 213 { 214 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 215 u32 addr = __mt7921_reg_addr(dev, offset); 216 217 dev->bus_ops->wr(mdev, addr, val); 218 } 219 220 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 221 { 222 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 223 u32 addr = __mt7921_reg_addr(dev, offset); 224 225 return dev->bus_ops->rmw(mdev, addr, mask, val); 226 } 227 228 static int mt7921_pci_probe(struct pci_dev *pdev, 229 const struct pci_device_id *id) 230 { 231 static const struct mt76_driver_ops drv_ops = { 232 /* txwi_size = txd size + txp size */ 233 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7921_txp_common), 234 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ, 235 .survey_flags = SURVEY_INFO_TIME_TX | 236 SURVEY_INFO_TIME_RX | 237 SURVEY_INFO_TIME_BSS_RX, 238 .token_size = MT7921_TOKEN_SIZE, 239 .tx_prepare_skb = mt7921e_tx_prepare_skb, 240 .tx_complete_skb = mt7921e_tx_complete_skb, 241 .rx_check = mt7921e_rx_check, 242 .rx_skb = mt7921e_queue_rx_skb, 243 .rx_poll_complete = mt7921_rx_poll_complete, 244 .sta_ps = mt7921_sta_ps, 245 .sta_add = mt7921_mac_sta_add, 246 .sta_assoc = mt7921_mac_sta_assoc, 247 .sta_remove = mt7921_mac_sta_remove, 248 .update_survey = mt7921_update_channel, 249 }; 250 251 static const struct mt7921_hif_ops mt7921_pcie_ops = { 252 .init_reset = mt7921e_init_reset, 253 .reset = mt7921e_mac_reset, 254 .mcu_init = mt7921e_mcu_init, 255 .drv_own = mt7921e_mcu_drv_pmctrl, 256 .fw_own = mt7921e_mcu_fw_pmctrl, 257 }; 258 259 struct mt76_bus_ops *bus_ops; 260 struct mt7921_dev *dev; 261 struct mt76_dev *mdev; 262 int ret; 263 264 ret = pcim_enable_device(pdev); 265 if (ret) 266 return ret; 267 268 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 269 if (ret) 270 return ret; 271 272 pci_set_master(pdev); 273 274 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 275 if (ret < 0) 276 return ret; 277 278 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 279 if (ret) 280 goto err_free_pci_vec; 281 282 if (mt7921_disable_aspm) 283 mt76_pci_disable_aspm(pdev); 284 285 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops, 286 &drv_ops); 287 if (!mdev) { 288 ret = -ENOMEM; 289 goto err_free_pci_vec; 290 } 291 292 dev = container_of(mdev, struct mt7921_dev, mt76); 293 dev->hif_ops = &mt7921_pcie_ops; 294 295 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 296 tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev); 297 298 dev->phy.dev = dev; 299 dev->phy.mt76 = &dev->mt76.phy; 300 dev->mt76.phy.priv = &dev->phy; 301 dev->bus_ops = dev->mt76.bus; 302 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 303 GFP_KERNEL); 304 if (!bus_ops) { 305 ret = -ENOMEM; 306 goto err_free_dev; 307 } 308 309 bus_ops->rr = mt7921_rr; 310 bus_ops->wr = mt7921_wr; 311 bus_ops->rmw = mt7921_rmw; 312 dev->mt76.bus = bus_ops; 313 314 ret = __mt7921e_mcu_drv_pmctrl(dev); 315 if (ret) 316 goto err_free_dev; 317 318 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) | 319 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 320 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 321 322 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 323 324 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 325 326 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler, 327 IRQF_SHARED, KBUILD_MODNAME, dev); 328 if (ret) 329 goto err_free_dev; 330 331 ret = mt7921_dma_init(dev); 332 if (ret) 333 goto err_free_irq; 334 335 ret = mt7921_register_device(dev); 336 if (ret) 337 goto err_free_irq; 338 339 return 0; 340 341 err_free_irq: 342 devm_free_irq(&pdev->dev, pdev->irq, dev); 343 err_free_dev: 344 mt76_free_device(&dev->mt76); 345 err_free_pci_vec: 346 pci_free_irq_vectors(pdev); 347 348 return ret; 349 } 350 351 static void mt7921_pci_remove(struct pci_dev *pdev) 352 { 353 struct mt76_dev *mdev = pci_get_drvdata(pdev); 354 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 355 356 mt7921e_unregister_device(dev); 357 devm_free_irq(&pdev->dev, pdev->irq, dev); 358 mt76_free_device(&dev->mt76); 359 pci_free_irq_vectors(pdev); 360 } 361 362 #ifdef CONFIG_PM 363 static int mt7921_pci_suspend(struct pci_dev *pdev, pm_message_t state) 364 { 365 struct mt76_dev *mdev = pci_get_drvdata(pdev); 366 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 367 struct mt76_connac_pm *pm = &dev->pm; 368 int i, err; 369 370 pm->suspended = true; 371 cancel_delayed_work_sync(&pm->ps_work); 372 cancel_work_sync(&pm->wake_work); 373 374 err = mt7921_mcu_drv_pmctrl(dev); 375 if (err < 0) 376 goto restore_suspend; 377 378 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 379 if (err) 380 goto restore_suspend; 381 382 /* always enable deep sleep during suspend to reduce 383 * power consumption 384 */ 385 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 386 387 napi_disable(&mdev->tx_napi); 388 mt76_worker_disable(&mdev->tx_worker); 389 390 mt76_for_each_q_rx(mdev, i) { 391 napi_disable(&mdev->napi[i]); 392 } 393 394 pci_enable_wake(pdev, pci_choose_state(pdev, state), true); 395 396 /* wait until dma is idle */ 397 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 398 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 399 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 400 401 /* put dma disabled */ 402 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 403 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 404 405 /* disable interrupt */ 406 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 407 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 408 synchronize_irq(pdev->irq); 409 tasklet_kill(&dev->irq_tasklet); 410 411 err = mt7921_mcu_fw_pmctrl(dev); 412 if (err) 413 goto restore_napi; 414 415 pci_save_state(pdev); 416 err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); 417 if (err) 418 goto restore_napi; 419 420 return 0; 421 422 restore_napi: 423 mt76_for_each_q_rx(mdev, i) { 424 napi_enable(&mdev->napi[i]); 425 } 426 napi_enable(&mdev->tx_napi); 427 428 if (!pm->ds_enable) 429 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 430 431 mt76_connac_mcu_set_hif_suspend(mdev, false); 432 433 restore_suspend: 434 pm->suspended = false; 435 436 return err; 437 } 438 439 static int mt7921_pci_resume(struct pci_dev *pdev) 440 { 441 struct mt76_dev *mdev = pci_get_drvdata(pdev); 442 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 443 struct mt76_connac_pm *pm = &dev->pm; 444 int i, err; 445 446 err = pci_set_power_state(pdev, PCI_D0); 447 if (err) 448 return err; 449 450 pci_restore_state(pdev); 451 452 err = mt7921_mcu_drv_pmctrl(dev); 453 if (err < 0) 454 return err; 455 456 mt7921_wpdma_reinit_cond(dev); 457 458 /* enable interrupt */ 459 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 460 mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 461 MT_INT_MCU_CMD); 462 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 463 464 /* put dma enabled */ 465 mt76_set(dev, MT_WFDMA0_GLO_CFG, 466 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 467 468 mt76_worker_enable(&mdev->tx_worker); 469 470 local_bh_disable(); 471 mt76_for_each_q_rx(mdev, i) { 472 napi_enable(&mdev->napi[i]); 473 napi_schedule(&mdev->napi[i]); 474 } 475 napi_enable(&mdev->tx_napi); 476 napi_schedule(&mdev->tx_napi); 477 local_bh_enable(); 478 479 /* restore previous ds setting */ 480 if (!pm->ds_enable) 481 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 482 483 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 484 if (err) 485 return err; 486 487 pm->suspended = false; 488 489 return err; 490 } 491 #endif /* CONFIG_PM */ 492 493 struct pci_driver mt7921_pci_driver = { 494 .name = KBUILD_MODNAME, 495 .id_table = mt7921_pci_device_table, 496 .probe = mt7921_pci_probe, 497 .remove = mt7921_pci_remove, 498 #ifdef CONFIG_PM 499 .suspend = mt7921_pci_suspend, 500 .resume = mt7921_pci_resume, 501 #endif /* CONFIG_PM */ 502 }; 503 504 module_pci_driver(mt7921_pci_driver); 505 506 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 507 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 508 MODULE_FIRMWARE(MT7921_ROM_PATCH); 509 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 510 MODULE_FIRMWARE(MT7922_ROM_PATCH); 511 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 512 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 513 MODULE_LICENSE("Dual BSD/GPL"); 514