1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 10 #include "mt7921.h" 11 #include "mac.h" 12 #include "mcu.h" 13 #include "../trace.h" 14 15 static const struct pci_device_id mt7921_pci_device_table[] = { 16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) }, 17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) }, 18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) }, 19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) }, 20 { }, 21 }; 22 23 static bool mt7921_disable_aspm; 24 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 25 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 26 27 static void 28 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 29 { 30 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 31 32 if (q == MT_RXQ_MAIN) 33 mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA); 34 else if (q == MT_RXQ_MCU_WA) 35 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2); 36 else 37 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM); 38 } 39 40 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance) 41 { 42 struct mt7921_dev *dev = dev_instance; 43 44 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 45 46 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 47 return IRQ_NONE; 48 49 tasklet_schedule(&dev->irq_tasklet); 50 51 return IRQ_HANDLED; 52 } 53 54 static void mt7921_irq_tasklet(unsigned long data) 55 { 56 struct mt7921_dev *dev = (struct mt7921_dev *)data; 57 u32 intr, mask = 0; 58 59 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 60 61 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA); 62 intr &= dev->mt76.mmio.irqmask; 63 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr); 64 65 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 66 67 mask |= intr & MT_INT_RX_DONE_ALL; 68 if (intr & MT_INT_TX_DONE_MCU) 69 mask |= MT_INT_TX_DONE_MCU; 70 71 if (intr & MT_INT_MCU_CMD) { 72 u32 intr_sw; 73 74 intr_sw = mt76_rr(dev, MT_MCU_CMD); 75 /* ack MCU2HOST_SW_INT_STA */ 76 mt76_wr(dev, MT_MCU_CMD, intr_sw); 77 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) { 78 mask |= MT_INT_RX_DONE_DATA; 79 intr |= MT_INT_RX_DONE_DATA; 80 } 81 } 82 83 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0); 84 85 if (intr & MT_INT_TX_DONE_ALL) 86 napi_schedule(&dev->mt76.tx_napi); 87 88 if (intr & MT_INT_RX_DONE_WM) 89 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 90 91 if (intr & MT_INT_RX_DONE_WM2) 92 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 93 94 if (intr & MT_INT_RX_DONE_DATA) 95 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 96 } 97 98 static int mt7921e_init_reset(struct mt7921_dev *dev) 99 { 100 return mt7921_wpdma_reset(dev, true); 101 } 102 103 static void mt7921e_unregister_device(struct mt7921_dev *dev) 104 { 105 int i; 106 struct mt76_connac_pm *pm = &dev->pm; 107 108 cancel_work_sync(&dev->init_work); 109 mt76_unregister_device(&dev->mt76); 110 mt76_for_each_q_rx(&dev->mt76, i) 111 napi_disable(&dev->mt76.napi[i]); 112 cancel_delayed_work_sync(&pm->ps_work); 113 cancel_work_sync(&pm->wake_work); 114 115 mt7921_tx_token_put(dev); 116 mt7921_mcu_drv_pmctrl(dev); 117 mt7921_dma_cleanup(dev); 118 mt7921_wfsys_reset(dev); 119 mt7921_mcu_exit(dev); 120 121 tasklet_disable(&dev->irq_tasklet); 122 mt76_free_device(&dev->mt76); 123 } 124 125 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr) 126 { 127 static const struct { 128 u32 phys; 129 u32 mapped; 130 u32 size; 131 } fixed_map[] = { 132 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 133 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 134 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 135 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 136 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 137 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 138 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 139 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 140 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 141 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 142 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 143 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 144 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 145 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 146 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 147 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 148 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 149 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 150 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 151 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 152 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 153 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 154 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ 155 { 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */ 156 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 157 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 158 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 159 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 160 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 161 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 162 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 163 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 164 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 165 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 166 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 167 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 168 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 169 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 170 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 171 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 172 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 173 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 174 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 175 }; 176 int i; 177 178 if (addr < 0x100000) 179 return addr; 180 181 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 182 u32 ofs; 183 184 if (addr < fixed_map[i].phys) 185 continue; 186 187 ofs = addr - fixed_map[i].phys; 188 if (ofs > fixed_map[i].size) 189 continue; 190 191 return fixed_map[i].mapped + ofs; 192 } 193 194 if ((addr >= 0x18000000 && addr < 0x18c00000) || 195 (addr >= 0x70000000 && addr < 0x78000000) || 196 (addr >= 0x7c000000 && addr < 0x7c400000)) 197 return mt7921_reg_map_l1(dev, addr); 198 199 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 200 addr); 201 202 return 0; 203 } 204 205 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 206 { 207 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 208 u32 addr = __mt7921_reg_addr(dev, offset); 209 210 return dev->bus_ops->rr(mdev, addr); 211 } 212 213 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 214 { 215 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 216 u32 addr = __mt7921_reg_addr(dev, offset); 217 218 dev->bus_ops->wr(mdev, addr, val); 219 } 220 221 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 222 { 223 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 224 u32 addr = __mt7921_reg_addr(dev, offset); 225 226 return dev->bus_ops->rmw(mdev, addr, mask, val); 227 } 228 229 static int mt7921_pci_probe(struct pci_dev *pdev, 230 const struct pci_device_id *id) 231 { 232 static const struct mt76_driver_ops drv_ops = { 233 /* txwi_size = txd size + txp size */ 234 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7921_txp_common), 235 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ, 236 .survey_flags = SURVEY_INFO_TIME_TX | 237 SURVEY_INFO_TIME_RX | 238 SURVEY_INFO_TIME_BSS_RX, 239 .token_size = MT7921_TOKEN_SIZE, 240 .tx_prepare_skb = mt7921e_tx_prepare_skb, 241 .tx_complete_skb = mt7921e_tx_complete_skb, 242 .rx_check = mt7921e_rx_check, 243 .rx_skb = mt7921e_queue_rx_skb, 244 .rx_poll_complete = mt7921_rx_poll_complete, 245 .sta_ps = mt7921_sta_ps, 246 .sta_add = mt7921_mac_sta_add, 247 .sta_assoc = mt7921_mac_sta_assoc, 248 .sta_remove = mt7921_mac_sta_remove, 249 .update_survey = mt7921_update_channel, 250 }; 251 252 static const struct mt7921_hif_ops mt7921_pcie_ops = { 253 .init_reset = mt7921e_init_reset, 254 .reset = mt7921e_mac_reset, 255 .mcu_init = mt7921e_mcu_init, 256 .drv_own = mt7921e_mcu_drv_pmctrl, 257 .fw_own = mt7921e_mcu_fw_pmctrl, 258 }; 259 260 struct mt76_bus_ops *bus_ops; 261 struct mt7921_dev *dev; 262 struct mt76_dev *mdev; 263 int ret; 264 265 ret = pcim_enable_device(pdev); 266 if (ret) 267 return ret; 268 269 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 270 if (ret) 271 return ret; 272 273 pci_set_master(pdev); 274 275 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 276 if (ret < 0) 277 return ret; 278 279 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 280 if (ret) 281 goto err_free_pci_vec; 282 283 if (mt7921_disable_aspm) 284 mt76_pci_disable_aspm(pdev); 285 286 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops, 287 &drv_ops); 288 if (!mdev) { 289 ret = -ENOMEM; 290 goto err_free_pci_vec; 291 } 292 293 dev = container_of(mdev, struct mt7921_dev, mt76); 294 dev->hif_ops = &mt7921_pcie_ops; 295 296 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 297 tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev); 298 299 dev->phy.dev = dev; 300 dev->phy.mt76 = &dev->mt76.phy; 301 dev->mt76.phy.priv = &dev->phy; 302 dev->bus_ops = dev->mt76.bus; 303 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 304 GFP_KERNEL); 305 if (!bus_ops) 306 return -ENOMEM; 307 308 bus_ops->rr = mt7921_rr; 309 bus_ops->wr = mt7921_wr; 310 bus_ops->rmw = mt7921_rmw; 311 dev->mt76.bus = bus_ops; 312 313 ret = __mt7921e_mcu_drv_pmctrl(dev); 314 if (ret) 315 return ret; 316 317 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) | 318 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 319 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 320 321 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 322 323 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 324 325 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler, 326 IRQF_SHARED, KBUILD_MODNAME, dev); 327 if (ret) 328 goto err_free_dev; 329 330 ret = mt7921_dma_init(dev); 331 if (ret) 332 goto err_free_irq; 333 334 ret = mt7921_register_device(dev); 335 if (ret) 336 goto err_free_irq; 337 338 return 0; 339 340 err_free_irq: 341 devm_free_irq(&pdev->dev, pdev->irq, dev); 342 err_free_dev: 343 mt76_free_device(&dev->mt76); 344 err_free_pci_vec: 345 pci_free_irq_vectors(pdev); 346 347 return ret; 348 } 349 350 static void mt7921_pci_remove(struct pci_dev *pdev) 351 { 352 struct mt76_dev *mdev = pci_get_drvdata(pdev); 353 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 354 355 mt7921e_unregister_device(dev); 356 devm_free_irq(&pdev->dev, pdev->irq, dev); 357 pci_free_irq_vectors(pdev); 358 } 359 360 #ifdef CONFIG_PM 361 static int mt7921_pci_suspend(struct pci_dev *pdev, pm_message_t state) 362 { 363 struct mt76_dev *mdev = pci_get_drvdata(pdev); 364 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 365 struct mt76_connac_pm *pm = &dev->pm; 366 int i, err; 367 368 pm->suspended = true; 369 cancel_delayed_work_sync(&pm->ps_work); 370 cancel_work_sync(&pm->wake_work); 371 372 err = mt7921_mcu_drv_pmctrl(dev); 373 if (err < 0) 374 goto restore_suspend; 375 376 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 377 if (err) 378 goto restore_suspend; 379 380 /* always enable deep sleep during suspend to reduce 381 * power consumption 382 */ 383 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 384 385 napi_disable(&mdev->tx_napi); 386 mt76_worker_disable(&mdev->tx_worker); 387 388 mt76_for_each_q_rx(mdev, i) { 389 napi_disable(&mdev->napi[i]); 390 } 391 392 pci_enable_wake(pdev, pci_choose_state(pdev, state), true); 393 394 /* wait until dma is idle */ 395 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 396 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 397 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 398 399 /* put dma disabled */ 400 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 401 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 402 403 /* disable interrupt */ 404 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 405 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 406 synchronize_irq(pdev->irq); 407 tasklet_kill(&dev->irq_tasklet); 408 409 err = mt7921_mcu_fw_pmctrl(dev); 410 if (err) 411 goto restore_napi; 412 413 pci_save_state(pdev); 414 err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); 415 if (err) 416 goto restore_napi; 417 418 return 0; 419 420 restore_napi: 421 mt76_for_each_q_rx(mdev, i) { 422 napi_enable(&mdev->napi[i]); 423 } 424 napi_enable(&mdev->tx_napi); 425 426 if (!pm->ds_enable) 427 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 428 429 mt76_connac_mcu_set_hif_suspend(mdev, false); 430 431 restore_suspend: 432 pm->suspended = false; 433 434 return err; 435 } 436 437 static int mt7921_pci_resume(struct pci_dev *pdev) 438 { 439 struct mt76_dev *mdev = pci_get_drvdata(pdev); 440 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 441 struct mt76_connac_pm *pm = &dev->pm; 442 int i, err; 443 444 err = pci_set_power_state(pdev, PCI_D0); 445 if (err) 446 return err; 447 448 pci_restore_state(pdev); 449 450 err = mt7921_mcu_drv_pmctrl(dev); 451 if (err < 0) 452 return err; 453 454 mt7921_wpdma_reinit_cond(dev); 455 456 /* enable interrupt */ 457 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 458 mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 459 MT_INT_MCU_CMD); 460 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 461 462 /* put dma enabled */ 463 mt76_set(dev, MT_WFDMA0_GLO_CFG, 464 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 465 466 mt76_worker_enable(&mdev->tx_worker); 467 468 local_bh_disable(); 469 mt76_for_each_q_rx(mdev, i) { 470 napi_enable(&mdev->napi[i]); 471 napi_schedule(&mdev->napi[i]); 472 } 473 napi_enable(&mdev->tx_napi); 474 napi_schedule(&mdev->tx_napi); 475 local_bh_enable(); 476 477 /* restore previous ds setting */ 478 if (!pm->ds_enable) 479 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 480 481 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 482 if (err) 483 return err; 484 485 pm->suspended = false; 486 487 return err; 488 } 489 #endif /* CONFIG_PM */ 490 491 struct pci_driver mt7921_pci_driver = { 492 .name = KBUILD_MODNAME, 493 .id_table = mt7921_pci_device_table, 494 .probe = mt7921_pci_probe, 495 .remove = mt7921_pci_remove, 496 #ifdef CONFIG_PM 497 .suspend = mt7921_pci_suspend, 498 .resume = mt7921_pci_resume, 499 #endif /* CONFIG_PM */ 500 }; 501 502 module_pci_driver(mt7921_pci_driver); 503 504 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 505 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 506 MODULE_FIRMWARE(MT7921_ROM_PATCH); 507 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 508 MODULE_FIRMWARE(MT7922_ROM_PATCH); 509 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 510 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 511 MODULE_LICENSE("Dual BSD/GPL"); 512