1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 10 #include "mt7921.h" 11 #include "../mt76_connac2_mac.h" 12 #include "mcu.h" 13 #include "../trace.h" 14 15 static const struct pci_device_id mt7921_pci_device_table[] = { 16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961), 17 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922), 19 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608), 21 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616), 23 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 24 { }, 25 }; 26 27 static bool mt7921_disable_aspm; 28 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 29 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 30 31 static void 32 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 33 { 34 if (q == MT_RXQ_MAIN) 35 mt76_connac_irq_enable(mdev, MT_INT_RX_DONE_DATA); 36 else if (q == MT_RXQ_MCU_WA) 37 mt76_connac_irq_enable(mdev, MT_INT_RX_DONE_WM2); 38 else 39 mt76_connac_irq_enable(mdev, MT_INT_RX_DONE_WM); 40 } 41 42 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance) 43 { 44 struct mt7921_dev *dev = dev_instance; 45 46 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 47 48 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 49 return IRQ_NONE; 50 51 tasklet_schedule(&dev->mt76.irq_tasklet); 52 53 return IRQ_HANDLED; 54 } 55 56 static void mt7921_irq_tasklet(unsigned long data) 57 { 58 struct mt7921_dev *dev = (struct mt7921_dev *)data; 59 u32 intr, mask = 0; 60 61 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 62 63 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA); 64 intr &= dev->mt76.mmio.irqmask; 65 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr); 66 67 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 68 69 mask |= intr & MT_INT_RX_DONE_ALL; 70 if (intr & MT_INT_TX_DONE_MCU) 71 mask |= MT_INT_TX_DONE_MCU; 72 73 if (intr & MT_INT_MCU_CMD) { 74 u32 intr_sw; 75 76 intr_sw = mt76_rr(dev, MT_MCU_CMD); 77 /* ack MCU2HOST_SW_INT_STA */ 78 mt76_wr(dev, MT_MCU_CMD, intr_sw); 79 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) { 80 mask |= MT_INT_RX_DONE_DATA; 81 intr |= MT_INT_RX_DONE_DATA; 82 } 83 } 84 85 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0); 86 87 if (intr & MT_INT_TX_DONE_ALL) 88 napi_schedule(&dev->mt76.tx_napi); 89 90 if (intr & MT_INT_RX_DONE_WM) 91 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 92 93 if (intr & MT_INT_RX_DONE_WM2) 94 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 95 96 if (intr & MT_INT_RX_DONE_DATA) 97 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 98 } 99 100 static int mt7921e_init_reset(struct mt7921_dev *dev) 101 { 102 return mt7921_wpdma_reset(dev, true); 103 } 104 105 static void mt7921e_unregister_device(struct mt7921_dev *dev) 106 { 107 int i; 108 struct mt76_connac_pm *pm = &dev->pm; 109 110 cancel_work_sync(&dev->init_work); 111 mt76_unregister_device(&dev->mt76); 112 mt76_for_each_q_rx(&dev->mt76, i) 113 napi_disable(&dev->mt76.napi[i]); 114 cancel_delayed_work_sync(&pm->ps_work); 115 cancel_work_sync(&pm->wake_work); 116 cancel_work_sync(&dev->reset_work); 117 118 mt7921_tx_token_put(dev); 119 __mt7921_mcu_drv_pmctrl(dev); 120 mt7921_dma_cleanup(dev); 121 mt7921_wfsys_reset(dev); 122 skb_queue_purge(&dev->mt76.mcu.res_q); 123 124 tasklet_disable(&dev->mt76.irq_tasklet); 125 } 126 127 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr) 128 { 129 static const struct mt76_connac_reg_map fixed_map[] = { 130 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 131 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 132 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 133 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 134 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 135 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 136 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 137 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 138 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 139 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 140 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 141 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 142 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 143 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 144 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 145 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 146 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 147 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 148 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 149 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 150 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 151 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 152 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ 153 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ 154 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ 155 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 156 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 157 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 158 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 159 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 160 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 161 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 162 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 163 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 164 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 165 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 166 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 167 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 168 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 169 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 170 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 171 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 172 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 173 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 174 }; 175 int i; 176 177 if (addr < 0x100000) 178 return addr; 179 180 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 181 u32 ofs; 182 183 if (addr < fixed_map[i].phys) 184 continue; 185 186 ofs = addr - fixed_map[i].phys; 187 if (ofs > fixed_map[i].size) 188 continue; 189 190 return fixed_map[i].maps + ofs; 191 } 192 193 if ((addr >= 0x18000000 && addr < 0x18c00000) || 194 (addr >= 0x70000000 && addr < 0x78000000) || 195 (addr >= 0x7c000000 && addr < 0x7c400000)) 196 return mt7921_reg_map_l1(dev, addr); 197 198 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 199 addr); 200 201 return 0; 202 } 203 204 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 205 { 206 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 207 u32 addr = __mt7921_reg_addr(dev, offset); 208 209 return dev->bus_ops->rr(mdev, addr); 210 } 211 212 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 213 { 214 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 215 u32 addr = __mt7921_reg_addr(dev, offset); 216 217 dev->bus_ops->wr(mdev, addr, val); 218 } 219 220 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 221 { 222 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 223 u32 addr = __mt7921_reg_addr(dev, offset); 224 225 return dev->bus_ops->rmw(mdev, addr, mask, val); 226 } 227 228 static int mt7921_pci_probe(struct pci_dev *pdev, 229 const struct pci_device_id *id) 230 { 231 static const struct mt76_driver_ops drv_ops = { 232 /* txwi_size = txd size + txp size */ 233 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 234 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 235 MT_DRV_AMSDU_OFFLOAD, 236 .survey_flags = SURVEY_INFO_TIME_TX | 237 SURVEY_INFO_TIME_RX | 238 SURVEY_INFO_TIME_BSS_RX, 239 .token_size = MT7921_TOKEN_SIZE, 240 .tx_prepare_skb = mt7921e_tx_prepare_skb, 241 .tx_complete_skb = mt76_connac_tx_complete_skb, 242 .rx_check = mt7921_rx_check, 243 .rx_skb = mt7921_queue_rx_skb, 244 .rx_poll_complete = mt7921_rx_poll_complete, 245 .sta_add = mt7921_mac_sta_add, 246 .sta_assoc = mt7921_mac_sta_assoc, 247 .sta_remove = mt7921_mac_sta_remove, 248 .update_survey = mt7921_update_channel, 249 }; 250 static const struct mt7921_hif_ops mt7921_pcie_ops = { 251 .init_reset = mt7921e_init_reset, 252 .reset = mt7921e_mac_reset, 253 .mcu_init = mt7921e_mcu_init, 254 .drv_own = mt7921e_mcu_drv_pmctrl, 255 .fw_own = mt7921e_mcu_fw_pmctrl, 256 }; 257 struct ieee80211_ops *ops; 258 struct mt76_bus_ops *bus_ops; 259 struct mt7921_dev *dev; 260 struct mt76_dev *mdev; 261 u8 features; 262 int ret; 263 u16 cmd; 264 265 ret = pcim_enable_device(pdev); 266 if (ret) 267 return ret; 268 269 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 270 if (ret) 271 return ret; 272 273 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 274 if (!(cmd & PCI_COMMAND_MEMORY)) { 275 cmd |= PCI_COMMAND_MEMORY; 276 pci_write_config_word(pdev, PCI_COMMAND, cmd); 277 } 278 pci_set_master(pdev); 279 280 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 281 if (ret < 0) 282 return ret; 283 284 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 285 if (ret) 286 goto err_free_pci_vec; 287 288 if (mt7921_disable_aspm) 289 mt76_pci_disable_aspm(pdev); 290 291 ops = mt7921_get_mac80211_ops(&pdev->dev, (void *)id->driver_data, 292 &features); 293 if (!ops) { 294 ret = -ENOMEM; 295 goto err_free_pci_vec; 296 } 297 298 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops); 299 if (!mdev) { 300 ret = -ENOMEM; 301 goto err_free_pci_vec; 302 } 303 304 pci_set_drvdata(pdev, mdev); 305 306 dev = container_of(mdev, struct mt7921_dev, mt76); 307 dev->fw_features = features; 308 dev->hif_ops = &mt7921_pcie_ops; 309 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 310 tasklet_init(&mdev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev); 311 312 dev->phy.dev = dev; 313 dev->phy.mt76 = &dev->mt76.phy; 314 dev->mt76.phy.priv = &dev->phy; 315 dev->bus_ops = dev->mt76.bus; 316 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 317 GFP_KERNEL); 318 if (!bus_ops) { 319 ret = -ENOMEM; 320 goto err_free_dev; 321 } 322 323 bus_ops->rr = mt7921_rr; 324 bus_ops->wr = mt7921_wr; 325 bus_ops->rmw = mt7921_rmw; 326 dev->mt76.bus = bus_ops; 327 328 ret = __mt7921e_mcu_drv_pmctrl(dev); 329 if (ret) 330 goto err_free_dev; 331 332 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) | 333 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 334 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 335 336 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 337 338 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 339 340 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler, 341 IRQF_SHARED, KBUILD_MODNAME, dev); 342 if (ret) 343 goto err_free_dev; 344 345 ret = mt7921_dma_init(dev); 346 if (ret) 347 goto err_free_irq; 348 349 ret = mt7921_register_device(dev); 350 if (ret) 351 goto err_free_irq; 352 353 return 0; 354 355 err_free_irq: 356 devm_free_irq(&pdev->dev, pdev->irq, dev); 357 err_free_dev: 358 mt76_free_device(&dev->mt76); 359 err_free_pci_vec: 360 pci_free_irq_vectors(pdev); 361 362 return ret; 363 } 364 365 static void mt7921_pci_remove(struct pci_dev *pdev) 366 { 367 struct mt76_dev *mdev = pci_get_drvdata(pdev); 368 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 369 370 mt7921e_unregister_device(dev); 371 devm_free_irq(&pdev->dev, pdev->irq, dev); 372 mt76_free_device(&dev->mt76); 373 pci_free_irq_vectors(pdev); 374 } 375 376 static int mt7921_pci_suspend(struct device *device) 377 { 378 struct pci_dev *pdev = to_pci_dev(device); 379 struct mt76_dev *mdev = pci_get_drvdata(pdev); 380 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 381 struct mt76_connac_pm *pm = &dev->pm; 382 int i, err; 383 384 pm->suspended = true; 385 flush_work(&dev->reset_work); 386 cancel_delayed_work_sync(&pm->ps_work); 387 cancel_work_sync(&pm->wake_work); 388 389 err = mt7921_mcu_drv_pmctrl(dev); 390 if (err < 0) 391 goto restore_suspend; 392 393 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 394 if (err) 395 goto restore_suspend; 396 397 /* always enable deep sleep during suspend to reduce 398 * power consumption 399 */ 400 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 401 402 napi_disable(&mdev->tx_napi); 403 mt76_worker_disable(&mdev->tx_worker); 404 405 mt76_for_each_q_rx(mdev, i) { 406 napi_disable(&mdev->napi[i]); 407 } 408 409 /* wait until dma is idle */ 410 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 411 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 412 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 413 414 /* put dma disabled */ 415 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 416 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 417 418 /* disable interrupt */ 419 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 420 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 421 synchronize_irq(pdev->irq); 422 tasklet_kill(&mdev->irq_tasklet); 423 424 err = mt7921_mcu_fw_pmctrl(dev); 425 if (err) 426 goto restore_napi; 427 428 return 0; 429 430 restore_napi: 431 mt76_for_each_q_rx(mdev, i) { 432 napi_enable(&mdev->napi[i]); 433 } 434 napi_enable(&mdev->tx_napi); 435 436 if (!pm->ds_enable) 437 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 438 439 mt76_connac_mcu_set_hif_suspend(mdev, false); 440 441 restore_suspend: 442 pm->suspended = false; 443 444 if (err < 0) 445 mt7921_reset(&dev->mt76); 446 447 return err; 448 } 449 450 static int mt7921_pci_resume(struct device *device) 451 { 452 struct pci_dev *pdev = to_pci_dev(device); 453 struct mt76_dev *mdev = pci_get_drvdata(pdev); 454 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 455 struct mt76_connac_pm *pm = &dev->pm; 456 int i, err; 457 458 err = mt7921_mcu_drv_pmctrl(dev); 459 if (err < 0) 460 goto failed; 461 462 mt7921_wpdma_reinit_cond(dev); 463 464 /* enable interrupt */ 465 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 466 mt76_connac_irq_enable(&dev->mt76, 467 MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 468 MT_INT_MCU_CMD); 469 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 470 471 /* put dma enabled */ 472 mt76_set(dev, MT_WFDMA0_GLO_CFG, 473 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 474 475 mt76_worker_enable(&mdev->tx_worker); 476 477 local_bh_disable(); 478 mt76_for_each_q_rx(mdev, i) { 479 napi_enable(&mdev->napi[i]); 480 napi_schedule(&mdev->napi[i]); 481 } 482 napi_enable(&mdev->tx_napi); 483 napi_schedule(&mdev->tx_napi); 484 local_bh_enable(); 485 486 /* restore previous ds setting */ 487 if (!pm->ds_enable) 488 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 489 490 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 491 failed: 492 pm->suspended = false; 493 494 if (err < 0) 495 mt7921_reset(&dev->mt76); 496 497 return err; 498 } 499 500 static void mt7921_pci_shutdown(struct pci_dev *pdev) 501 { 502 mt7921_pci_remove(pdev); 503 } 504 505 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume); 506 507 static struct pci_driver mt7921_pci_driver = { 508 .name = KBUILD_MODNAME, 509 .id_table = mt7921_pci_device_table, 510 .probe = mt7921_pci_probe, 511 .remove = mt7921_pci_remove, 512 .shutdown = mt7921_pci_shutdown, 513 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops), 514 }; 515 516 module_pci_driver(mt7921_pci_driver); 517 518 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 519 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 520 MODULE_FIRMWARE(MT7921_ROM_PATCH); 521 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 522 MODULE_FIRMWARE(MT7922_ROM_PATCH); 523 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 524 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 525 MODULE_LICENSE("Dual BSD/GPL"); 526