1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/devcoredump.h> 5 #include <linux/etherdevice.h> 6 #include <linux/timekeeping.h> 7 #include "mt7921.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 13 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 14 IEEE80211_RADIOTAP_HE_##f) 15 16 static struct mt76_wcid *mt7921_rx_get_wcid(struct mt7921_dev *dev, 17 u16 idx, bool unicast) 18 { 19 struct mt7921_sta *sta; 20 struct mt76_wcid *wcid; 21 22 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 23 return NULL; 24 25 wcid = rcu_dereference(dev->mt76.wcid[idx]); 26 if (unicast || !wcid) 27 return wcid; 28 29 if (!wcid->sta) 30 return NULL; 31 32 sta = container_of(wcid, struct mt7921_sta, wcid); 33 if (!sta->vif) 34 return NULL; 35 36 return &sta->vif->sta.wcid; 37 } 38 39 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 40 { 41 } 42 EXPORT_SYMBOL_GPL(mt7921_sta_ps); 43 44 bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask) 45 { 46 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 47 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 48 49 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 50 0, 5000); 51 } 52 53 void mt7921_mac_sta_poll(struct mt7921_dev *dev) 54 { 55 static const u8 ac_to_tid[] = { 56 [IEEE80211_AC_BE] = 0, 57 [IEEE80211_AC_BK] = 1, 58 [IEEE80211_AC_VI] = 4, 59 [IEEE80211_AC_VO] = 6 60 }; 61 struct ieee80211_sta *sta; 62 struct mt7921_sta *msta; 63 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 64 LIST_HEAD(sta_poll_list); 65 struct rate_info *rate; 66 int i; 67 68 spin_lock_bh(&dev->sta_poll_lock); 69 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 70 spin_unlock_bh(&dev->sta_poll_lock); 71 72 while (true) { 73 bool clear = false; 74 u32 addr, val; 75 u16 idx; 76 u8 bw; 77 78 spin_lock_bh(&dev->sta_poll_lock); 79 if (list_empty(&sta_poll_list)) { 80 spin_unlock_bh(&dev->sta_poll_lock); 81 break; 82 } 83 msta = list_first_entry(&sta_poll_list, 84 struct mt7921_sta, poll_list); 85 list_del_init(&msta->poll_list); 86 spin_unlock_bh(&dev->sta_poll_lock); 87 88 idx = msta->wcid.idx; 89 addr = mt7921_mac_wtbl_lmac_addr(idx, MT_WTBL_AC0_CTT_OFFSET); 90 91 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 92 u32 tx_last = msta->airtime_ac[i]; 93 u32 rx_last = msta->airtime_ac[i + 4]; 94 95 msta->airtime_ac[i] = mt76_rr(dev, addr); 96 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 97 98 tx_time[i] = msta->airtime_ac[i] - tx_last; 99 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 100 101 if ((tx_last | rx_last) & BIT(30)) 102 clear = true; 103 104 addr += 8; 105 } 106 107 if (clear) { 108 mt7921_mac_wtbl_update(dev, idx, 109 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 110 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 111 } 112 113 if (!msta->wcid.sta) 114 continue; 115 116 sta = container_of((void *)msta, struct ieee80211_sta, 117 drv_priv); 118 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 119 u8 q = mt76_connac_lmac_mapping(i); 120 u32 tx_cur = tx_time[q]; 121 u32 rx_cur = rx_time[q]; 122 u8 tid = ac_to_tid[i]; 123 124 if (!tx_cur && !rx_cur) 125 continue; 126 127 ieee80211_sta_register_airtime(sta, tid, tx_cur, 128 rx_cur); 129 } 130 131 /* We don't support reading GI info from txs packets. 132 * For accurate tx status reporting and AQL improvement, 133 * we need to make sure that flags match so polling GI 134 * from per-sta counters directly. 135 */ 136 rate = &msta->wcid.rate; 137 addr = mt7921_mac_wtbl_lmac_addr(idx, 138 MT_WTBL_TXRX_CAP_RATE_OFFSET); 139 val = mt76_rr(dev, addr); 140 141 switch (rate->bw) { 142 case RATE_INFO_BW_160: 143 bw = IEEE80211_STA_RX_BW_160; 144 break; 145 case RATE_INFO_BW_80: 146 bw = IEEE80211_STA_RX_BW_80; 147 break; 148 case RATE_INFO_BW_40: 149 bw = IEEE80211_STA_RX_BW_40; 150 break; 151 default: 152 bw = IEEE80211_STA_RX_BW_20; 153 break; 154 } 155 156 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 157 u8 offs = MT_WTBL_TXRX_RATE_G2_HE + 2 * bw; 158 159 rate->he_gi = (val & (0x3 << offs)) >> offs; 160 } else if (rate->flags & 161 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 162 if (val & BIT(MT_WTBL_TXRX_RATE_G2 + bw)) 163 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 164 else 165 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 166 } 167 } 168 } 169 EXPORT_SYMBOL_GPL(mt7921_mac_sta_poll); 170 171 static void 172 mt7921_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 173 struct ieee80211_radiotap_he *he, 174 __le32 *rxv) 175 { 176 u32 ru_h, ru_l; 177 u8 ru, offs = 0; 178 179 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0])); 180 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1])); 181 ru = (u8)(ru_l | ru_h << 4); 182 183 status->bw = RATE_INFO_BW_HE_RU; 184 185 switch (ru) { 186 case 0 ... 36: 187 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 188 offs = ru; 189 break; 190 case 37 ... 52: 191 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 192 offs = ru - 37; 193 break; 194 case 53 ... 60: 195 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 196 offs = ru - 53; 197 break; 198 case 61 ... 64: 199 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 200 offs = ru - 61; 201 break; 202 case 65 ... 66: 203 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 204 offs = ru - 65; 205 break; 206 case 67: 207 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 208 break; 209 case 68: 210 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 211 break; 212 } 213 214 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 215 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 216 le16_encode_bits(offs, 217 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 218 } 219 220 static void 221 mt7921_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv) 222 { 223 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 224 static const struct ieee80211_radiotap_he_mu mu_known = { 225 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 226 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 227 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 228 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN) | 229 HE_BITS(MU_FLAGS1_SIG_B_COMP_KNOWN), 230 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN) | 231 HE_BITS(MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN), 232 }; 233 struct ieee80211_radiotap_he_mu *he_mu; 234 235 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 236 237 he_mu = skb_push(skb, sizeof(mu_known)); 238 memcpy(he_mu, &mu_known, sizeof(mu_known)); 239 240 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 241 242 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 243 if (status->he_dcm) 244 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 245 246 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 247 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 248 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 249 250 he_mu->ru_ch1[0] = FIELD_GET(MT_CRXV_HE_RU0, le32_to_cpu(rxv[3])); 251 252 if (status->bw >= RATE_INFO_BW_40) { 253 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 254 he_mu->ru_ch2[0] = 255 FIELD_GET(MT_CRXV_HE_RU1, le32_to_cpu(rxv[3])); 256 } 257 258 if (status->bw >= RATE_INFO_BW_80) { 259 he_mu->ru_ch1[1] = 260 FIELD_GET(MT_CRXV_HE_RU2, le32_to_cpu(rxv[3])); 261 he_mu->ru_ch2[1] = 262 FIELD_GET(MT_CRXV_HE_RU3, le32_to_cpu(rxv[3])); 263 } 264 } 265 266 static void 267 mt7921_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u32 mode) 268 { 269 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 270 static const struct ieee80211_radiotap_he known = { 271 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 272 HE_BITS(DATA1_DATA_DCM_KNOWN) | 273 HE_BITS(DATA1_STBC_KNOWN) | 274 HE_BITS(DATA1_CODING_KNOWN) | 275 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 276 HE_BITS(DATA1_DOPPLER_KNOWN) | 277 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 278 HE_BITS(DATA1_BSS_COLOR_KNOWN), 279 .data2 = HE_BITS(DATA2_GI_KNOWN) | 280 HE_BITS(DATA2_TXBF_KNOWN) | 281 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 282 HE_BITS(DATA2_TXOP_KNOWN), 283 }; 284 struct ieee80211_radiotap_he *he = NULL; 285 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 286 287 status->flag |= RX_FLAG_RADIOTAP_HE; 288 289 he = skb_push(skb, sizeof(known)); 290 memcpy(he, &known, sizeof(known)); 291 292 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 293 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 294 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 295 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 296 le16_encode_bits(ltf_size, 297 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 298 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 299 he->data5 |= HE_BITS(DATA5_TXBF); 300 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 301 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 302 303 switch (mode) { 304 case MT_PHY_TYPE_HE_SU: 305 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 306 HE_BITS(DATA1_UL_DL_KNOWN) | 307 HE_BITS(DATA1_BEAM_CHANGE_KNOWN); 308 309 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 310 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 311 break; 312 case MT_PHY_TYPE_HE_EXT_SU: 313 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 314 HE_BITS(DATA1_UL_DL_KNOWN); 315 316 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 317 break; 318 case MT_PHY_TYPE_HE_MU: 319 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 320 HE_BITS(DATA1_UL_DL_KNOWN); 321 322 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 323 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 324 325 mt7921_mac_decode_he_radiotap_ru(status, he, rxv); 326 mt7921_mac_decode_he_mu_radiotap(skb, rxv); 327 break; 328 case MT_PHY_TYPE_HE_TB: 329 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 330 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 331 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 332 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 333 334 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 335 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 336 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 337 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 338 339 mt7921_mac_decode_he_radiotap_ru(status, he, rxv); 340 break; 341 default: 342 break; 343 } 344 } 345 346 static void 347 mt7921_get_status_freq_info(struct mt7921_dev *dev, struct mt76_phy *mphy, 348 struct mt76_rx_status *status, u8 chfreq) 349 { 350 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 351 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 352 !test_bit(MT76_STATE_ROC, &mphy->state)) { 353 status->freq = mphy->chandef.chan->center_freq; 354 status->band = mphy->chandef.chan->band; 355 return; 356 } 357 358 if (chfreq > 180) { 359 status->band = NL80211_BAND_6GHZ; 360 chfreq = (chfreq - 181) * 4 + 1; 361 } else if (chfreq > 14) { 362 status->band = NL80211_BAND_5GHZ; 363 } else { 364 status->band = NL80211_BAND_2GHZ; 365 } 366 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 367 } 368 369 static void 370 mt7921_mac_rssi_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 371 { 372 struct sk_buff *skb = priv; 373 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 374 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 375 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 376 377 if (status->signal > 0) 378 return; 379 380 if (!ether_addr_equal(vif->addr, hdr->addr1)) 381 return; 382 383 ewma_rssi_add(&mvif->rssi, -status->signal); 384 } 385 386 static void 387 mt7921_mac_assoc_rssi(struct mt7921_dev *dev, struct sk_buff *skb) 388 { 389 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 390 391 if (!ieee80211_is_assoc_resp(hdr->frame_control) && 392 !ieee80211_is_auth(hdr->frame_control)) 393 return; 394 395 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 396 IEEE80211_IFACE_ITER_RESUME_ALL, 397 mt7921_mac_rssi_iter, skb); 398 } 399 400 /* The HW does not translate the mac header to 802.3 for mesh point */ 401 static int mt7921_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 402 { 403 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 404 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 405 struct mt7921_sta *msta = (struct mt7921_sta *)status->wcid; 406 __le32 *rxd = (__le32 *)skb->data; 407 struct ieee80211_sta *sta; 408 struct ieee80211_vif *vif; 409 struct ieee80211_hdr hdr; 410 __le32 qos_ctrl, ht_ctrl; 411 412 if (FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, le32_to_cpu(rxd[3])) != 413 MT_RXD3_NORMAL_U2M) 414 return -EINVAL; 415 416 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 417 return -EINVAL; 418 419 if (!msta || !msta->vif) 420 return -EINVAL; 421 422 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 423 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 424 425 /* store the info from RXD and ethhdr to avoid being overridden */ 426 hdr.frame_control = FIELD_GET(MT_RXD6_FRAME_CONTROL, rxd[6]); 427 hdr.seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, rxd[8]); 428 qos_ctrl = FIELD_GET(MT_RXD8_QOS_CTL, rxd[8]); 429 ht_ctrl = FIELD_GET(MT_RXD9_HT_CONTROL, rxd[9]); 430 431 hdr.duration_id = 0; 432 ether_addr_copy(hdr.addr1, vif->addr); 433 ether_addr_copy(hdr.addr2, sta->addr); 434 switch (le16_to_cpu(hdr.frame_control) & 435 (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) { 436 case 0: 437 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 438 break; 439 case IEEE80211_FCTL_FROMDS: 440 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 441 break; 442 case IEEE80211_FCTL_TODS: 443 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 444 break; 445 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 446 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 447 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 448 break; 449 default: 450 break; 451 } 452 453 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 454 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 455 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 456 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 457 else if (eth_hdr->h_proto >= cpu_to_be16(ETH_P_802_3_MIN)) 458 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 459 else 460 skb_pull(skb, 2); 461 462 if (ieee80211_has_order(hdr.frame_control)) 463 memcpy(skb_push(skb, 2), &ht_ctrl, 2); 464 if (ieee80211_is_data_qos(hdr.frame_control)) 465 memcpy(skb_push(skb, 2), &qos_ctrl, 2); 466 if (ieee80211_has_a4(hdr.frame_control)) 467 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 468 else 469 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 470 471 return 0; 472 } 473 474 static int 475 mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) 476 { 477 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 478 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 479 bool hdr_trans, unicast, insert_ccmp_hdr = false; 480 u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info; 481 u16 hdr_gap; 482 __le32 *rxv = NULL, *rxd = (__le32 *)skb->data; 483 struct mt76_phy *mphy = &dev->mt76.phy; 484 struct mt7921_phy *phy = &dev->phy; 485 struct ieee80211_supported_band *sband; 486 u32 rxd0 = le32_to_cpu(rxd[0]); 487 u32 rxd1 = le32_to_cpu(rxd[1]); 488 u32 rxd2 = le32_to_cpu(rxd[2]); 489 u32 rxd3 = le32_to_cpu(rxd[3]); 490 u32 rxd4 = le32_to_cpu(rxd[4]); 491 u16 seq_ctrl = 0; 492 __le16 fc = 0; 493 u32 mode = 0; 494 int i, idx; 495 496 memset(status, 0, sizeof(*status)); 497 498 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) 499 return -EINVAL; 500 501 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 502 return -EINVAL; 503 504 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 505 return -EINVAL; 506 507 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 508 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 509 return -EINVAL; 510 511 /* ICV error or CCMP/BIP/WPI MIC error */ 512 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 513 status->flag |= RX_FLAG_ONLY_MONITOR; 514 515 chfreq = FIELD_GET(MT_RXD3_NORMAL_CH_FREQ, rxd3); 516 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 517 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 518 status->wcid = mt7921_rx_get_wcid(dev, idx, unicast); 519 520 if (status->wcid) { 521 struct mt7921_sta *msta; 522 523 msta = container_of(status->wcid, struct mt7921_sta, wcid); 524 spin_lock_bh(&dev->sta_poll_lock); 525 if (list_empty(&msta->poll_list)) 526 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 527 spin_unlock_bh(&dev->sta_poll_lock); 528 } 529 530 mt7921_get_status_freq_info(dev, mphy, status, chfreq); 531 532 switch (status->band) { 533 case NL80211_BAND_5GHZ: 534 sband = &mphy->sband_5g.sband; 535 break; 536 case NL80211_BAND_6GHZ: 537 sband = &mphy->sband_6g.sband; 538 break; 539 default: 540 sband = &mphy->sband_2g.sband; 541 break; 542 } 543 544 if (!sband->channels) 545 return -EINVAL; 546 547 if ((rxd0 & csum_mask) == csum_mask) 548 skb->ip_summed = CHECKSUM_UNNECESSARY; 549 550 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 551 status->flag |= RX_FLAG_FAILED_FCS_CRC; 552 553 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 554 status->flag |= RX_FLAG_MMIC_ERROR; 555 556 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 557 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 558 status->flag |= RX_FLAG_DECRYPTED; 559 status->flag |= RX_FLAG_IV_STRIPPED; 560 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 561 } 562 563 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 564 565 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 566 return -EINVAL; 567 568 rxd += 6; 569 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 570 u32 v0 = le32_to_cpu(rxd[0]); 571 u32 v2 = le32_to_cpu(rxd[2]); 572 573 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 574 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 575 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 576 577 rxd += 4; 578 if ((u8 *)rxd - skb->data >= skb->len) 579 return -EINVAL; 580 } 581 582 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 583 u8 *data = (u8 *)rxd; 584 585 if (status->flag & RX_FLAG_DECRYPTED) { 586 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 587 case MT_CIPHER_AES_CCMP: 588 case MT_CIPHER_CCMP_CCX: 589 case MT_CIPHER_CCMP_256: 590 insert_ccmp_hdr = 591 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 592 fallthrough; 593 case MT_CIPHER_TKIP: 594 case MT_CIPHER_TKIP_NO_MIC: 595 case MT_CIPHER_GCMP: 596 case MT_CIPHER_GCMP_256: 597 status->iv[0] = data[5]; 598 status->iv[1] = data[4]; 599 status->iv[2] = data[3]; 600 status->iv[3] = data[2]; 601 status->iv[4] = data[1]; 602 status->iv[5] = data[0]; 603 break; 604 default: 605 break; 606 } 607 } 608 rxd += 4; 609 if ((u8 *)rxd - skb->data >= skb->len) 610 return -EINVAL; 611 } 612 613 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 614 status->timestamp = le32_to_cpu(rxd[0]); 615 status->flag |= RX_FLAG_MACTIME_START; 616 617 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 618 status->flag |= RX_FLAG_AMPDU_DETAILS; 619 620 /* all subframes of an A-MPDU have the same timestamp */ 621 if (phy->rx_ampdu_ts != status->timestamp) { 622 if (!++phy->ampdu_ref) 623 phy->ampdu_ref++; 624 } 625 phy->rx_ampdu_ts = status->timestamp; 626 627 status->ampdu_ref = phy->ampdu_ref; 628 } 629 630 rxd += 2; 631 if ((u8 *)rxd - skb->data >= skb->len) 632 return -EINVAL; 633 } 634 635 /* RXD Group 3 - P-RXV */ 636 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 637 u8 stbc, gi; 638 u32 v0, v1; 639 bool cck; 640 641 rxv = rxd; 642 rxd += 2; 643 if ((u8 *)rxd - skb->data >= skb->len) 644 return -EINVAL; 645 646 v0 = le32_to_cpu(rxv[0]); 647 v1 = le32_to_cpu(rxv[1]); 648 649 if (v0 & MT_PRXV_HT_AD_CODE) 650 status->enc_flags |= RX_ENC_FLAG_LDPC; 651 652 status->chains = mphy->antenna_mask; 653 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 654 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 655 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 656 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 657 status->signal = -128; 658 for (i = 0; i < hweight8(mphy->antenna_mask); i++) { 659 if (!(status->chains & BIT(i)) || 660 status->chain_signal[i] >= 0) 661 continue; 662 663 status->signal = max(status->signal, 664 status->chain_signal[i]); 665 } 666 667 if (status->signal == -128) 668 status->flag |= RX_FLAG_NO_SIGNAL_VAL; 669 670 stbc = FIELD_GET(MT_PRXV_STBC, v0); 671 gi = FIELD_GET(MT_PRXV_SGI, v0); 672 cck = false; 673 674 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 675 mode = FIELD_GET(MT_PRXV_TX_MODE, v0); 676 677 switch (mode) { 678 case MT_PHY_TYPE_CCK: 679 cck = true; 680 fallthrough; 681 case MT_PHY_TYPE_OFDM: 682 i = mt76_get_rate(&dev->mt76, sband, i, cck); 683 break; 684 case MT_PHY_TYPE_HT_GF: 685 case MT_PHY_TYPE_HT: 686 status->encoding = RX_ENC_HT; 687 if (i > 31) 688 return -EINVAL; 689 break; 690 case MT_PHY_TYPE_VHT: 691 status->nss = 692 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 693 status->encoding = RX_ENC_VHT; 694 if (i > 9) 695 return -EINVAL; 696 break; 697 case MT_PHY_TYPE_HE_MU: 698 case MT_PHY_TYPE_HE_SU: 699 case MT_PHY_TYPE_HE_EXT_SU: 700 case MT_PHY_TYPE_HE_TB: 701 status->nss = 702 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 703 status->encoding = RX_ENC_HE; 704 i &= GENMASK(3, 0); 705 706 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 707 status->he_gi = gi; 708 709 status->he_dcm = !!(idx & MT_PRXV_TX_DCM); 710 break; 711 default: 712 return -EINVAL; 713 } 714 715 status->rate_idx = i; 716 717 switch (FIELD_GET(MT_PRXV_FRAME_MODE, v0)) { 718 case IEEE80211_STA_RX_BW_20: 719 break; 720 case IEEE80211_STA_RX_BW_40: 721 if (mode & MT_PHY_TYPE_HE_EXT_SU && 722 (idx & MT_PRXV_TX_ER_SU_106T)) { 723 status->bw = RATE_INFO_BW_HE_RU; 724 status->he_ru = 725 NL80211_RATE_INFO_HE_RU_ALLOC_106; 726 } else { 727 status->bw = RATE_INFO_BW_40; 728 } 729 break; 730 case IEEE80211_STA_RX_BW_80: 731 status->bw = RATE_INFO_BW_80; 732 break; 733 case IEEE80211_STA_RX_BW_160: 734 status->bw = RATE_INFO_BW_160; 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 741 if (mode < MT_PHY_TYPE_HE_SU && gi) 742 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 743 744 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 745 rxd += 18; 746 if ((u8 *)rxd - skb->data >= skb->len) 747 return -EINVAL; 748 } 749 } 750 751 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 752 status->amsdu = !!amsdu_info; 753 if (status->amsdu) { 754 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 755 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 756 } 757 758 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 759 if (hdr_trans && ieee80211_has_morefrags(fc)) { 760 if (mt7921_reverse_frag0_hdr_trans(skb, hdr_gap)) 761 return -EINVAL; 762 hdr_trans = false; 763 } else { 764 skb_pull(skb, hdr_gap); 765 if (!hdr_trans && status->amsdu) { 766 memmove(skb->data + 2, skb->data, 767 ieee80211_get_hdrlen_from_skb(skb)); 768 skb_pull(skb, 2); 769 } 770 } 771 772 if (!hdr_trans) { 773 struct ieee80211_hdr *hdr; 774 775 if (insert_ccmp_hdr) { 776 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 777 778 mt76_insert_ccmp_hdr(skb, key_id); 779 } 780 781 hdr = mt76_skb_get_hdr(skb); 782 fc = hdr->frame_control; 783 if (ieee80211_is_data_qos(fc)) { 784 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 785 qos_ctl = *ieee80211_get_qos_ctl(hdr); 786 } 787 } else { 788 status->flag |= RX_FLAG_8023; 789 } 790 791 mt7921_mac_assoc_rssi(dev, skb); 792 793 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 794 mt7921_mac_decode_he_radiotap(skb, rxv, mode); 795 796 if (!status->wcid || !ieee80211_is_data_qos(fc)) 797 return 0; 798 799 status->aggr = unicast && !ieee80211_is_qos_nullfunc(fc); 800 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 801 status->qos_ctl = qos_ctl; 802 803 return 0; 804 } 805 806 static void 807 mt7921_mac_write_txwi_8023(struct mt7921_dev *dev, __le32 *txwi, 808 struct sk_buff *skb, struct mt76_wcid *wcid) 809 { 810 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 811 u8 fc_type, fc_stype; 812 bool wmm = false; 813 u32 val; 814 815 if (wcid->sta) { 816 struct ieee80211_sta *sta; 817 818 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 819 wmm = sta->wme; 820 } 821 822 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 823 FIELD_PREP(MT_TXD1_TID, tid); 824 825 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 826 val |= MT_TXD1_ETH_802_3; 827 828 txwi[1] |= cpu_to_le32(val); 829 830 fc_type = IEEE80211_FTYPE_DATA >> 2; 831 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 832 833 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 834 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 835 836 txwi[2] |= cpu_to_le32(val); 837 838 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 839 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 840 txwi[7] |= cpu_to_le32(val); 841 } 842 843 static void 844 mt7921_mac_write_txwi_80211(struct mt7921_dev *dev, __le32 *txwi, 845 struct sk_buff *skb, struct ieee80211_key_conf *key) 846 { 847 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 848 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 849 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 850 bool multicast = is_multicast_ether_addr(hdr->addr1); 851 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 852 __le16 fc = hdr->frame_control; 853 u8 fc_type, fc_stype; 854 u32 val; 855 856 if (ieee80211_is_action(fc) && 857 mgmt->u.action.category == WLAN_CATEGORY_BACK && 858 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 859 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 860 861 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 862 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 863 } else if (ieee80211_is_back_req(hdr->frame_control)) { 864 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 865 u16 control = le16_to_cpu(bar->control); 866 867 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 868 } 869 870 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 871 FIELD_PREP(MT_TXD1_HDR_INFO, 872 ieee80211_get_hdrlen_from_skb(skb) / 2) | 873 FIELD_PREP(MT_TXD1_TID, tid); 874 txwi[1] |= cpu_to_le32(val); 875 876 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 877 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 878 879 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 880 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 881 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 882 883 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 884 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 885 val |= MT_TXD2_BIP; 886 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 887 } 888 889 if (!ieee80211_is_data(fc) || multicast || 890 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 891 val |= MT_TXD2_FIX_RATE; 892 893 txwi[2] |= cpu_to_le32(val); 894 895 if (ieee80211_is_beacon(fc)) { 896 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 897 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 898 } 899 900 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 901 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 902 903 if (ieee80211_is_back_req(hdr->frame_control)) { 904 struct ieee80211_bar *bar; 905 906 bar = (struct ieee80211_bar *)skb->data; 907 seqno = le16_to_cpu(bar->start_seq_num); 908 } 909 910 val = MT_TXD3_SN_VALID | 911 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 912 txwi[3] |= cpu_to_le32(val); 913 } 914 915 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 916 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 917 txwi[7] |= cpu_to_le32(val); 918 } 919 920 void mt7921_mac_write_txwi(struct mt7921_dev *dev, __le32 *txwi, 921 struct sk_buff *skb, struct mt76_wcid *wcid, 922 struct ieee80211_key_conf *key, int pid, 923 bool beacon) 924 { 925 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 926 struct ieee80211_vif *vif = info->control.vif; 927 struct mt76_phy *mphy = &dev->mphy; 928 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 929 bool is_mmio = mt76_is_mmio(&dev->mt76); 930 u32 sz_txd = is_mmio ? MT_TXD_SIZE : MT_SDIO_TXD_SIZE; 931 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 932 u16 tx_count = 15; 933 u32 val; 934 935 if (vif) { 936 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 937 938 omac_idx = mvif->omac_idx; 939 wmm_idx = mvif->wmm_idx; 940 } 941 942 if (beacon) { 943 p_fmt = MT_TX_TYPE_FW; 944 q_idx = MT_LMAC_BCN0; 945 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 946 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 947 q_idx = MT_LMAC_ALTX0; 948 } else { 949 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 950 q_idx = wmm_idx * MT7921_MAX_WMM_SETS + 951 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 952 } 953 954 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 955 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 956 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 957 txwi[0] = cpu_to_le32(val); 958 959 val = MT_TXD1_LONG_FORMAT | 960 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 961 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 962 963 txwi[1] = cpu_to_le32(val); 964 txwi[2] = 0; 965 966 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 967 if (key) 968 val |= MT_TXD3_PROTECT_FRAME; 969 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 970 val |= MT_TXD3_NO_ACK; 971 972 txwi[3] = cpu_to_le32(val); 973 txwi[4] = 0; 974 975 val = FIELD_PREP(MT_TXD5_PID, pid); 976 if (pid >= MT_PACKET_ID_FIRST) 977 val |= MT_TXD5_TX_STATUS_HOST; 978 txwi[5] = cpu_to_le32(val); 979 980 txwi[6] = 0; 981 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 982 983 if (is_8023) 984 mt7921_mac_write_txwi_8023(dev, txwi, skb, wcid); 985 else 986 mt7921_mac_write_txwi_80211(dev, txwi, skb, key); 987 988 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 989 int rateidx = vif ? ffs(vif->bss_conf.basic_rates) - 1 : 0; 990 u16 rate, mode; 991 992 /* hardware won't add HTC for mgmt/ctrl frame */ 993 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 994 995 rate = mt76_calculate_default_rate(mphy, rateidx); 996 mode = rate >> 8; 997 rate &= GENMASK(7, 0); 998 rate |= FIELD_PREP(MT_TX_RATE_MODE, mode); 999 1000 val = MT_TXD6_FIXED_BW | 1001 FIELD_PREP(MT_TXD6_TX_RATE, rate); 1002 txwi[6] |= cpu_to_le32(val); 1003 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1004 } 1005 } 1006 EXPORT_SYMBOL_GPL(mt7921_mac_write_txwi); 1007 1008 void mt7921_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1009 { 1010 struct mt7921_sta *msta; 1011 u16 fc, tid; 1012 u32 val; 1013 1014 if (!sta || !(sta->ht_cap.ht_supported || sta->he_cap.has_he)) 1015 return; 1016 1017 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1])); 1018 if (tid >= 6) /* skip VO queue */ 1019 return; 1020 1021 val = le32_to_cpu(txwi[2]); 1022 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1023 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1024 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1025 return; 1026 1027 msta = (struct mt7921_sta *)sta->drv_priv; 1028 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1029 ieee80211_start_tx_ba_session(sta, tid, 0); 1030 } 1031 EXPORT_SYMBOL_GPL(mt7921_tx_check_aggr); 1032 1033 static bool 1034 mt7921_mac_add_txs_skb(struct mt7921_dev *dev, struct mt76_wcid *wcid, int pid, 1035 __le32 *txs_data) 1036 { 1037 struct mt7921_sta *msta = container_of(wcid, struct mt7921_sta, wcid); 1038 struct mt76_sta_stats *stats = &msta->stats; 1039 struct ieee80211_supported_band *sband; 1040 struct mt76_dev *mdev = &dev->mt76; 1041 struct ieee80211_tx_info *info; 1042 struct rate_info rate = {}; 1043 struct sk_buff_head list; 1044 u32 txrate, txs, mode; 1045 struct sk_buff *skb; 1046 bool cck = false; 1047 1048 mt76_tx_status_lock(mdev, &list); 1049 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1050 if (!skb) 1051 goto out; 1052 1053 info = IEEE80211_SKB_CB(skb); 1054 txs = le32_to_cpu(txs_data[0]); 1055 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1056 info->flags |= IEEE80211_TX_STAT_ACK; 1057 1058 info->status.ampdu_len = 1; 1059 info->status.ampdu_ack_len = !!(info->flags & 1060 IEEE80211_TX_STAT_ACK); 1061 1062 info->status.rates[0].idx = -1; 1063 1064 if (!wcid->sta) 1065 goto out; 1066 1067 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1068 1069 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1070 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1071 1072 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1073 stats->tx_nss[rate.nss - 1]++; 1074 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1075 stats->tx_mcs[rate.mcs]++; 1076 1077 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1078 switch (mode) { 1079 case MT_PHY_TYPE_CCK: 1080 cck = true; 1081 fallthrough; 1082 case MT_PHY_TYPE_OFDM: 1083 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) 1084 sband = &dev->mphy.sband_5g.sband; 1085 else 1086 sband = &dev->mphy.sband_2g.sband; 1087 1088 rate.mcs = mt76_get_rate(dev->mphy.dev, sband, rate.mcs, cck); 1089 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1090 break; 1091 case MT_PHY_TYPE_HT: 1092 case MT_PHY_TYPE_HT_GF: 1093 if (rate.mcs > 31) 1094 goto out; 1095 1096 rate.flags = RATE_INFO_FLAGS_MCS; 1097 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1098 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1099 break; 1100 case MT_PHY_TYPE_VHT: 1101 if (rate.mcs > 9) 1102 goto out; 1103 1104 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1105 break; 1106 case MT_PHY_TYPE_HE_SU: 1107 case MT_PHY_TYPE_HE_EXT_SU: 1108 case MT_PHY_TYPE_HE_TB: 1109 case MT_PHY_TYPE_HE_MU: 1110 if (rate.mcs > 11) 1111 goto out; 1112 1113 rate.he_gi = wcid->rate.he_gi; 1114 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1115 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1116 break; 1117 default: 1118 goto out; 1119 } 1120 stats->tx_mode[mode]++; 1121 1122 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1123 case IEEE80211_STA_RX_BW_160: 1124 rate.bw = RATE_INFO_BW_160; 1125 stats->tx_bw[3]++; 1126 break; 1127 case IEEE80211_STA_RX_BW_80: 1128 rate.bw = RATE_INFO_BW_80; 1129 stats->tx_bw[2]++; 1130 break; 1131 case IEEE80211_STA_RX_BW_40: 1132 rate.bw = RATE_INFO_BW_40; 1133 stats->tx_bw[1]++; 1134 break; 1135 default: 1136 rate.bw = RATE_INFO_BW_20; 1137 stats->tx_bw[0]++; 1138 break; 1139 } 1140 wcid->rate = rate; 1141 1142 out: 1143 if (skb) 1144 mt76_tx_status_skb_done(mdev, skb, &list); 1145 mt76_tx_status_unlock(mdev, &list); 1146 1147 return !!skb; 1148 } 1149 1150 void mt7921_mac_add_txs(struct mt7921_dev *dev, void *data) 1151 { 1152 struct mt7921_sta *msta = NULL; 1153 struct mt76_wcid *wcid; 1154 __le32 *txs_data = data; 1155 u16 wcidx; 1156 u32 txs; 1157 u8 pid; 1158 1159 txs = le32_to_cpu(txs_data[0]); 1160 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) 1161 return; 1162 1163 txs = le32_to_cpu(txs_data[2]); 1164 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1165 1166 txs = le32_to_cpu(txs_data[3]); 1167 pid = FIELD_GET(MT_TXS3_PID, txs); 1168 1169 if (pid < MT_PACKET_ID_FIRST) 1170 return; 1171 1172 if (wcidx >= MT7921_WTBL_SIZE) 1173 return; 1174 1175 rcu_read_lock(); 1176 1177 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1178 if (!wcid) 1179 goto out; 1180 1181 mt7921_mac_add_txs_skb(dev, wcid, pid, txs_data); 1182 1183 if (!wcid->sta) 1184 goto out; 1185 1186 msta = container_of(wcid, struct mt7921_sta, wcid); 1187 spin_lock_bh(&dev->sta_poll_lock); 1188 if (list_empty(&msta->poll_list)) 1189 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1190 spin_unlock_bh(&dev->sta_poll_lock); 1191 1192 out: 1193 rcu_read_unlock(); 1194 } 1195 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs); 1196 1197 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1198 struct sk_buff *skb) 1199 { 1200 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1201 __le32 *rxd = (__le32 *)skb->data; 1202 __le32 *end = (__le32 *)&skb->data[skb->len]; 1203 enum rx_pkt_type type; 1204 u16 flag; 1205 1206 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1207 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0])); 1208 1209 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1210 type = PKT_TYPE_NORMAL_MCU; 1211 1212 switch (type) { 1213 case PKT_TYPE_RX_EVENT: 1214 mt7921_mcu_rx_event(dev, skb); 1215 break; 1216 case PKT_TYPE_TXS: 1217 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1218 mt7921_mac_add_txs(dev, rxd); 1219 dev_kfree_skb(skb); 1220 break; 1221 case PKT_TYPE_NORMAL_MCU: 1222 case PKT_TYPE_NORMAL: 1223 if (!mt7921_mac_fill_rx(dev, skb)) { 1224 mt76_rx(&dev->mt76, q, skb); 1225 return; 1226 } 1227 fallthrough; 1228 default: 1229 dev_kfree_skb(skb); 1230 break; 1231 } 1232 } 1233 EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb); 1234 1235 void mt7921_mac_reset_counters(struct mt7921_phy *phy) 1236 { 1237 struct mt7921_dev *dev = phy->dev; 1238 int i; 1239 1240 for (i = 0; i < 4; i++) { 1241 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1242 mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1243 } 1244 1245 dev->mt76.phy.survey_time = ktime_get_boottime(); 1246 memset(&dev->mt76.aggr_stats[0], 0, sizeof(dev->mt76.aggr_stats) / 2); 1247 1248 /* reset airtime counters */ 1249 mt76_rr(dev, MT_MIB_SDR9(0)); 1250 mt76_rr(dev, MT_MIB_SDR36(0)); 1251 mt76_rr(dev, MT_MIB_SDR37(0)); 1252 1253 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1254 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1255 } 1256 1257 void mt7921_mac_set_timing(struct mt7921_phy *phy) 1258 { 1259 s16 coverage_class = phy->coverage_class; 1260 struct mt7921_dev *dev = phy->dev; 1261 u32 val, reg_offset; 1262 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1263 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1264 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1265 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1266 bool is_2ghz = phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ; 1267 int sifs = is_2ghz ? 10 : 16, offset; 1268 1269 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1270 return; 1271 1272 mt76_set(dev, MT_ARB_SCR(0), 1273 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1274 udelay(1); 1275 1276 offset = 3 * coverage_class; 1277 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1278 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1279 1280 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset); 1281 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset); 1282 mt76_wr(dev, MT_TMAC_ICR0(0), 1283 FIELD_PREP(MT_IFS_EIFS, 360) | 1284 FIELD_PREP(MT_IFS_RIFS, 2) | 1285 FIELD_PREP(MT_IFS_SIFS, sifs) | 1286 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1287 1288 if (phy->slottime < 20 || !is_2ghz) 1289 val = MT7921_CFEND_RATE_DEFAULT; 1290 else 1291 val = MT7921_CFEND_RATE_11B; 1292 1293 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val); 1294 mt76_clear(dev, MT_ARB_SCR(0), 1295 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1296 } 1297 1298 static u8 1299 mt7921_phy_get_nf(struct mt7921_phy *phy, int idx) 1300 { 1301 return 0; 1302 } 1303 1304 static void 1305 mt7921_phy_update_channel(struct mt76_phy *mphy, int idx) 1306 { 1307 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 1308 struct mt7921_phy *phy = (struct mt7921_phy *)mphy->priv; 1309 struct mt76_channel_state *state; 1310 u64 busy_time, tx_time, rx_time, obss_time; 1311 int nf; 1312 1313 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1314 MT_MIB_SDR9_BUSY_MASK); 1315 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1316 MT_MIB_SDR36_TXTIME_MASK); 1317 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1318 MT_MIB_SDR37_RXTIME_MASK); 1319 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx), 1320 MT_MIB_OBSSTIME_MASK); 1321 1322 nf = mt7921_phy_get_nf(phy, idx); 1323 if (!phy->noise) 1324 phy->noise = nf << 4; 1325 else if (nf) 1326 phy->noise += nf - (phy->noise >> 4); 1327 1328 state = mphy->chan_state; 1329 state->cc_busy += busy_time; 1330 state->cc_tx += tx_time; 1331 state->cc_rx += rx_time + obss_time; 1332 state->cc_bss_rx += rx_time; 1333 state->noise = -(phy->noise >> 4); 1334 } 1335 1336 void mt7921_update_channel(struct mt76_phy *mphy) 1337 { 1338 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 1339 1340 if (mt76_connac_pm_wake(mphy, &dev->pm)) 1341 return; 1342 1343 mt7921_phy_update_channel(mphy, 0); 1344 /* reset obss airtime */ 1345 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1346 1347 mt76_connac_power_save_sched(mphy, &dev->pm); 1348 } 1349 EXPORT_SYMBOL_GPL(mt7921_update_channel); 1350 1351 static void 1352 mt7921_vif_connect_iter(void *priv, u8 *mac, 1353 struct ieee80211_vif *vif) 1354 { 1355 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 1356 struct mt7921_dev *dev = mvif->phy->dev; 1357 1358 if (vif->type == NL80211_IFTYPE_STATION) 1359 ieee80211_disconnect(vif, true); 1360 1361 mt76_connac_mcu_uni_add_dev(&dev->mphy, vif, &mvif->sta.wcid, true); 1362 mt7921_mcu_set_tx(dev, vif); 1363 } 1364 1365 /* system error recovery */ 1366 void mt7921_mac_reset_work(struct work_struct *work) 1367 { 1368 struct mt7921_dev *dev = container_of(work, struct mt7921_dev, 1369 reset_work); 1370 struct ieee80211_hw *hw = mt76_hw(dev); 1371 struct mt76_connac_pm *pm = &dev->pm; 1372 int i; 1373 1374 dev_err(dev->mt76.dev, "chip reset\n"); 1375 dev->hw_full_reset = true; 1376 ieee80211_stop_queues(hw); 1377 1378 cancel_delayed_work_sync(&dev->mphy.mac_work); 1379 cancel_delayed_work_sync(&pm->ps_work); 1380 cancel_work_sync(&pm->wake_work); 1381 1382 mutex_lock(&dev->mt76.mutex); 1383 for (i = 0; i < 10; i++) 1384 if (!mt7921_dev_reset(dev)) 1385 break; 1386 mutex_unlock(&dev->mt76.mutex); 1387 1388 if (i == 10) 1389 dev_err(dev->mt76.dev, "chip reset failed\n"); 1390 1391 if (test_and_clear_bit(MT76_HW_SCANNING, &dev->mphy.state)) { 1392 struct cfg80211_scan_info info = { 1393 .aborted = true, 1394 }; 1395 1396 ieee80211_scan_completed(dev->mphy.hw, &info); 1397 } 1398 1399 dev->hw_full_reset = false; 1400 pm->suspended = false; 1401 ieee80211_wake_queues(hw); 1402 ieee80211_iterate_active_interfaces(hw, 1403 IEEE80211_IFACE_ITER_RESUME_ALL, 1404 mt7921_vif_connect_iter, NULL); 1405 mt76_connac_power_save_sched(&dev->mt76.phy, pm); 1406 } 1407 1408 void mt7921_reset(struct mt76_dev *mdev) 1409 { 1410 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1411 1412 if (!dev->hw_init_done) 1413 return; 1414 1415 if (dev->hw_full_reset) 1416 return; 1417 1418 queue_work(dev->mt76.wq, &dev->reset_work); 1419 } 1420 1421 void mt7921_mac_update_mib_stats(struct mt7921_phy *phy) 1422 { 1423 struct mt7921_dev *dev = phy->dev; 1424 struct mib_stats *mib = &phy->mib; 1425 int i, aggr0 = 0, aggr1; 1426 u32 val; 1427 1428 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0), 1429 MT_MIB_SDR3_FCS_ERR_MASK); 1430 mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0), 1431 MT_MIB_ACK_FAIL_COUNT_MASK); 1432 mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0), 1433 MT_MIB_BA_FAIL_COUNT_MASK); 1434 mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0), 1435 MT_MIB_RTS_COUNT_MASK); 1436 mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0), 1437 MT_MIB_RTS_FAIL_COUNT_MASK); 1438 1439 mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0)); 1440 mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0)); 1441 mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0)); 1442 1443 val = mt76_rr(dev, MT_MIB_SDR32(0)); 1444 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR9_EBF_CNT_MASK, val); 1445 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR9_IBF_CNT_MASK, val); 1446 1447 val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0)); 1448 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, val); 1449 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, val); 1450 1451 val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0)); 1452 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, val); 1453 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, val); 1454 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, val); 1455 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, val); 1456 1457 mib->rx_mpdu_cnt += mt76_rr(dev, MT_MIB_SDR5(0)); 1458 mib->rx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR22(0)); 1459 mib->rx_ampdu_bytes_cnt += mt76_rr(dev, MT_MIB_SDR23(0)); 1460 mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0)); 1461 1462 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1463 val = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1464 mib->tx_amsdu[i] += val; 1465 mib->tx_amsdu_cnt += val; 1466 } 1467 1468 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 1469 u32 val2; 1470 1471 val = mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1472 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1473 1474 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 1475 dev->mt76.aggr_stats[aggr0++] += val >> 16; 1476 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff; 1477 dev->mt76.aggr_stats[aggr1++] += val2 >> 16; 1478 } 1479 } 1480 1481 void mt7921_mac_work(struct work_struct *work) 1482 { 1483 struct mt7921_phy *phy; 1484 struct mt76_phy *mphy; 1485 1486 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1487 mac_work.work); 1488 phy = mphy->priv; 1489 1490 mt7921_mutex_acquire(phy->dev); 1491 1492 mt76_update_survey(mphy); 1493 if (++mphy->mac_work_count == 2) { 1494 mphy->mac_work_count = 0; 1495 1496 mt7921_mac_update_mib_stats(phy); 1497 } 1498 1499 mt7921_mutex_release(phy->dev); 1500 1501 mt76_tx_status_check(mphy->dev, false); 1502 ieee80211_queue_delayed_work(phy->mt76->hw, &mphy->mac_work, 1503 MT7921_WATCHDOG_TIME); 1504 } 1505 1506 void mt7921_pm_wake_work(struct work_struct *work) 1507 { 1508 struct mt7921_dev *dev; 1509 struct mt76_phy *mphy; 1510 1511 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1512 pm.wake_work); 1513 mphy = dev->phy.mt76; 1514 1515 if (!mt7921_mcu_drv_pmctrl(dev)) { 1516 struct mt76_dev *mdev = &dev->mt76; 1517 int i; 1518 1519 if (mt76_is_sdio(mdev)) { 1520 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1521 mt76_worker_schedule(&mdev->sdio.txrx_worker); 1522 } else { 1523 mt76_for_each_q_rx(mdev, i) 1524 napi_schedule(&mdev->napi[i]); 1525 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1526 mt7921_mcu_tx_cleanup(dev); 1527 } 1528 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) 1529 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1530 MT7921_WATCHDOG_TIME); 1531 } 1532 1533 ieee80211_wake_queues(mphy->hw); 1534 wake_up(&dev->pm.wait); 1535 } 1536 1537 void mt7921_pm_power_save_work(struct work_struct *work) 1538 { 1539 struct mt7921_dev *dev; 1540 unsigned long delta; 1541 struct mt76_phy *mphy; 1542 1543 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1544 pm.ps_work.work); 1545 mphy = dev->phy.mt76; 1546 1547 delta = dev->pm.idle_timeout; 1548 if (test_bit(MT76_HW_SCANNING, &mphy->state) || 1549 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) || 1550 dev->fw_assert) 1551 goto out; 1552 1553 if (mutex_is_locked(&dev->mt76.mutex)) 1554 /* if mt76 mutex is held we should not put the device 1555 * to sleep since we are currently accessing device 1556 * register map. We need to wait for the next power_save 1557 * trigger. 1558 */ 1559 goto out; 1560 1561 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 1562 delta = dev->pm.last_activity + delta - jiffies; 1563 goto out; 1564 } 1565 1566 if (!mt7921_mcu_fw_pmctrl(dev)) { 1567 cancel_delayed_work_sync(&mphy->mac_work); 1568 return; 1569 } 1570 out: 1571 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 1572 } 1573 1574 void mt7921_coredump_work(struct work_struct *work) 1575 { 1576 struct mt7921_dev *dev; 1577 char *dump, *data; 1578 1579 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1580 coredump.work.work); 1581 1582 if (time_is_after_jiffies(dev->coredump.last_activity + 1583 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 1584 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 1585 MT76_CONNAC_COREDUMP_TIMEOUT); 1586 return; 1587 } 1588 1589 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 1590 data = dump; 1591 1592 while (true) { 1593 struct sk_buff *skb; 1594 1595 spin_lock_bh(&dev->mt76.lock); 1596 skb = __skb_dequeue(&dev->coredump.msg_list); 1597 spin_unlock_bh(&dev->mt76.lock); 1598 1599 if (!skb) 1600 break; 1601 1602 skb_pull(skb, sizeof(struct mt7921_mcu_rxd)); 1603 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 1604 dev_kfree_skb(skb); 1605 continue; 1606 } 1607 1608 memcpy(data, skb->data, skb->len); 1609 data += skb->len; 1610 1611 dev_kfree_skb(skb); 1612 } 1613 1614 if (dump) 1615 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 1616 GFP_KERNEL); 1617 1618 mt7921_reset(&dev->mt76); 1619 } 1620