1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/devcoredump.h> 5 #include <linux/etherdevice.h> 6 #include <linux/timekeeping.h> 7 #include "mt7921.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 13 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 14 IEEE80211_RADIOTAP_HE_##f) 15 16 static struct mt76_wcid *mt7921_rx_get_wcid(struct mt7921_dev *dev, 17 u16 idx, bool unicast) 18 { 19 struct mt7921_sta *sta; 20 struct mt76_wcid *wcid; 21 22 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 23 return NULL; 24 25 wcid = rcu_dereference(dev->mt76.wcid[idx]); 26 if (unicast || !wcid) 27 return wcid; 28 29 if (!wcid->sta) 30 return NULL; 31 32 sta = container_of(wcid, struct mt7921_sta, wcid); 33 if (!sta->vif) 34 return NULL; 35 36 return &sta->vif->sta.wcid; 37 } 38 39 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 40 { 41 } 42 EXPORT_SYMBOL_GPL(mt7921_sta_ps); 43 44 bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask) 45 { 46 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 47 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 48 49 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 50 0, 5000); 51 } 52 53 void mt7921_mac_sta_poll(struct mt7921_dev *dev) 54 { 55 static const u8 ac_to_tid[] = { 56 [IEEE80211_AC_BE] = 0, 57 [IEEE80211_AC_BK] = 1, 58 [IEEE80211_AC_VI] = 4, 59 [IEEE80211_AC_VO] = 6 60 }; 61 struct ieee80211_sta *sta; 62 struct mt7921_sta *msta; 63 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 64 LIST_HEAD(sta_poll_list); 65 struct rate_info *rate; 66 int i; 67 68 spin_lock_bh(&dev->sta_poll_lock); 69 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 70 spin_unlock_bh(&dev->sta_poll_lock); 71 72 while (true) { 73 bool clear = false; 74 u32 addr, val; 75 u16 idx; 76 u8 bw; 77 78 spin_lock_bh(&dev->sta_poll_lock); 79 if (list_empty(&sta_poll_list)) { 80 spin_unlock_bh(&dev->sta_poll_lock); 81 break; 82 } 83 msta = list_first_entry(&sta_poll_list, 84 struct mt7921_sta, poll_list); 85 list_del_init(&msta->poll_list); 86 spin_unlock_bh(&dev->sta_poll_lock); 87 88 idx = msta->wcid.idx; 89 addr = mt7921_mac_wtbl_lmac_addr(idx, MT_WTBL_AC0_CTT_OFFSET); 90 91 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 92 u32 tx_last = msta->airtime_ac[i]; 93 u32 rx_last = msta->airtime_ac[i + 4]; 94 95 msta->airtime_ac[i] = mt76_rr(dev, addr); 96 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 97 98 tx_time[i] = msta->airtime_ac[i] - tx_last; 99 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 100 101 if ((tx_last | rx_last) & BIT(30)) 102 clear = true; 103 104 addr += 8; 105 } 106 107 if (clear) { 108 mt7921_mac_wtbl_update(dev, idx, 109 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 110 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 111 } 112 113 if (!msta->wcid.sta) 114 continue; 115 116 sta = container_of((void *)msta, struct ieee80211_sta, 117 drv_priv); 118 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 119 u8 q = mt7921_lmac_mapping(dev, i); 120 u32 tx_cur = tx_time[q]; 121 u32 rx_cur = rx_time[q]; 122 u8 tid = ac_to_tid[i]; 123 124 if (!tx_cur && !rx_cur) 125 continue; 126 127 ieee80211_sta_register_airtime(sta, tid, tx_cur, 128 rx_cur); 129 } 130 131 /* We don't support reading GI info from txs packets. 132 * For accurate tx status reporting and AQL improvement, 133 * we need to make sure that flags match so polling GI 134 * from per-sta counters directly. 135 */ 136 rate = &msta->wcid.rate; 137 addr = mt7921_mac_wtbl_lmac_addr(idx, 138 MT_WTBL_TXRX_CAP_RATE_OFFSET); 139 val = mt76_rr(dev, addr); 140 141 switch (rate->bw) { 142 case RATE_INFO_BW_160: 143 bw = IEEE80211_STA_RX_BW_160; 144 break; 145 case RATE_INFO_BW_80: 146 bw = IEEE80211_STA_RX_BW_80; 147 break; 148 case RATE_INFO_BW_40: 149 bw = IEEE80211_STA_RX_BW_40; 150 break; 151 default: 152 bw = IEEE80211_STA_RX_BW_20; 153 break; 154 } 155 156 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 157 u8 offs = MT_WTBL_TXRX_RATE_G2_HE + 2 * bw; 158 159 rate->he_gi = (val & (0x3 << offs)) >> offs; 160 } else if (rate->flags & 161 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 162 if (val & BIT(MT_WTBL_TXRX_RATE_G2 + bw)) 163 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 164 else 165 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 166 } 167 } 168 } 169 EXPORT_SYMBOL_GPL(mt7921_mac_sta_poll); 170 171 static void 172 mt7921_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 173 struct ieee80211_radiotap_he *he, 174 __le32 *rxv) 175 { 176 u32 ru_h, ru_l; 177 u8 ru, offs = 0; 178 179 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0])); 180 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1])); 181 ru = (u8)(ru_l | ru_h << 4); 182 183 status->bw = RATE_INFO_BW_HE_RU; 184 185 switch (ru) { 186 case 0 ... 36: 187 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 188 offs = ru; 189 break; 190 case 37 ... 52: 191 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 192 offs = ru - 37; 193 break; 194 case 53 ... 60: 195 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 196 offs = ru - 53; 197 break; 198 case 61 ... 64: 199 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 200 offs = ru - 61; 201 break; 202 case 65 ... 66: 203 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 204 offs = ru - 65; 205 break; 206 case 67: 207 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 208 break; 209 case 68: 210 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 211 break; 212 } 213 214 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 215 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 216 le16_encode_bits(offs, 217 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 218 } 219 220 static void 221 mt7921_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv) 222 { 223 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 224 static const struct ieee80211_radiotap_he_mu mu_known = { 225 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 226 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 227 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 228 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN) | 229 HE_BITS(MU_FLAGS1_SIG_B_COMP_KNOWN), 230 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN) | 231 HE_BITS(MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN), 232 }; 233 struct ieee80211_radiotap_he_mu *he_mu; 234 235 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 236 237 he_mu = skb_push(skb, sizeof(mu_known)); 238 memcpy(he_mu, &mu_known, sizeof(mu_known)); 239 240 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 241 242 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 243 if (status->he_dcm) 244 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 245 246 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 247 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 248 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 249 250 he_mu->ru_ch1[0] = FIELD_GET(MT_CRXV_HE_RU0, le32_to_cpu(rxv[3])); 251 252 if (status->bw >= RATE_INFO_BW_40) { 253 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 254 he_mu->ru_ch2[0] = 255 FIELD_GET(MT_CRXV_HE_RU1, le32_to_cpu(rxv[3])); 256 } 257 258 if (status->bw >= RATE_INFO_BW_80) { 259 he_mu->ru_ch1[1] = 260 FIELD_GET(MT_CRXV_HE_RU2, le32_to_cpu(rxv[3])); 261 he_mu->ru_ch2[1] = 262 FIELD_GET(MT_CRXV_HE_RU3, le32_to_cpu(rxv[3])); 263 } 264 } 265 266 static void 267 mt7921_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u32 mode) 268 { 269 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 270 static const struct ieee80211_radiotap_he known = { 271 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 272 HE_BITS(DATA1_DATA_DCM_KNOWN) | 273 HE_BITS(DATA1_STBC_KNOWN) | 274 HE_BITS(DATA1_CODING_KNOWN) | 275 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 276 HE_BITS(DATA1_DOPPLER_KNOWN) | 277 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 278 HE_BITS(DATA1_BSS_COLOR_KNOWN), 279 .data2 = HE_BITS(DATA2_GI_KNOWN) | 280 HE_BITS(DATA2_TXBF_KNOWN) | 281 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 282 HE_BITS(DATA2_TXOP_KNOWN), 283 }; 284 struct ieee80211_radiotap_he *he = NULL; 285 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 286 287 status->flag |= RX_FLAG_RADIOTAP_HE; 288 289 he = skb_push(skb, sizeof(known)); 290 memcpy(he, &known, sizeof(known)); 291 292 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 293 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 294 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 295 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 296 le16_encode_bits(ltf_size, 297 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 298 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 299 he->data5 |= HE_BITS(DATA5_TXBF); 300 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 301 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 302 303 switch (mode) { 304 case MT_PHY_TYPE_HE_SU: 305 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 306 HE_BITS(DATA1_UL_DL_KNOWN) | 307 HE_BITS(DATA1_BEAM_CHANGE_KNOWN); 308 309 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 310 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 311 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 312 break; 313 case MT_PHY_TYPE_HE_EXT_SU: 314 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 315 HE_BITS(DATA1_UL_DL_KNOWN); 316 317 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 318 break; 319 case MT_PHY_TYPE_HE_MU: 320 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 321 HE_BITS(DATA1_UL_DL_KNOWN); 322 323 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 324 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 325 326 mt7921_mac_decode_he_radiotap_ru(status, he, rxv); 327 mt7921_mac_decode_he_mu_radiotap(skb, rxv); 328 break; 329 case MT_PHY_TYPE_HE_TB: 330 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 331 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 332 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 333 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 334 335 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 336 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 337 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 338 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 339 340 mt7921_mac_decode_he_radiotap_ru(status, he, rxv); 341 break; 342 default: 343 break; 344 } 345 } 346 347 static void 348 mt7921_get_status_freq_info(struct mt7921_dev *dev, struct mt76_phy *mphy, 349 struct mt76_rx_status *status, u8 chfreq) 350 { 351 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 352 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 353 !test_bit(MT76_STATE_ROC, &mphy->state)) { 354 status->freq = mphy->chandef.chan->center_freq; 355 status->band = mphy->chandef.chan->band; 356 return; 357 } 358 359 if (chfreq > 180) { 360 status->band = NL80211_BAND_6GHZ; 361 chfreq = (chfreq - 181) * 4 + 1; 362 } else if (chfreq > 14) { 363 status->band = NL80211_BAND_5GHZ; 364 } else { 365 status->band = NL80211_BAND_2GHZ; 366 } 367 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 368 } 369 370 static void 371 mt7921_mac_rssi_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 372 { 373 struct sk_buff *skb = priv; 374 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 375 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 376 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 377 378 if (status->signal > 0) 379 return; 380 381 if (!ether_addr_equal(vif->addr, hdr->addr1)) 382 return; 383 384 ewma_rssi_add(&mvif->rssi, -status->signal); 385 } 386 387 static void 388 mt7921_mac_assoc_rssi(struct mt7921_dev *dev, struct sk_buff *skb) 389 { 390 struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb); 391 392 if (!ieee80211_is_assoc_resp(hdr->frame_control) && 393 !ieee80211_is_auth(hdr->frame_control)) 394 return; 395 396 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 397 IEEE80211_IFACE_ITER_RESUME_ALL, 398 mt7921_mac_rssi_iter, skb); 399 } 400 401 /* The HW does not translate the mac header to 802.3 for mesh point */ 402 static int mt7921_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 403 { 404 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 405 struct mt7921_sta *msta = (struct mt7921_sta *)status->wcid; 406 struct ieee80211_sta *sta; 407 struct ieee80211_vif *vif; 408 struct ieee80211_hdr hdr; 409 struct ethhdr eth_hdr; 410 __le32 *rxd = (__le32 *)skb->data; 411 __le32 qos_ctrl, ht_ctrl; 412 413 if (FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, le32_to_cpu(rxd[3])) != 414 MT_RXD3_NORMAL_U2M) 415 return -EINVAL; 416 417 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 418 return -EINVAL; 419 420 if (!msta || !msta->vif) 421 return -EINVAL; 422 423 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 424 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 425 426 /* store the info from RXD and ethhdr to avoid being overridden */ 427 memcpy(ð_hdr, skb->data + hdr_gap, sizeof(eth_hdr)); 428 hdr.frame_control = FIELD_GET(MT_RXD6_FRAME_CONTROL, rxd[6]); 429 hdr.seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, rxd[8]); 430 qos_ctrl = FIELD_GET(MT_RXD8_QOS_CTL, rxd[8]); 431 ht_ctrl = FIELD_GET(MT_RXD9_HT_CONTROL, rxd[9]); 432 433 hdr.duration_id = 0; 434 ether_addr_copy(hdr.addr1, vif->addr); 435 ether_addr_copy(hdr.addr2, sta->addr); 436 switch (le16_to_cpu(hdr.frame_control) & 437 (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) { 438 case 0: 439 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 440 break; 441 case IEEE80211_FCTL_FROMDS: 442 ether_addr_copy(hdr.addr3, eth_hdr.h_source); 443 break; 444 case IEEE80211_FCTL_TODS: 445 ether_addr_copy(hdr.addr3, eth_hdr.h_dest); 446 break; 447 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 448 ether_addr_copy(hdr.addr3, eth_hdr.h_dest); 449 ether_addr_copy(hdr.addr4, eth_hdr.h_source); 450 break; 451 default: 452 break; 453 } 454 455 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 456 if (eth_hdr.h_proto == htons(ETH_P_AARP) || 457 eth_hdr.h_proto == htons(ETH_P_IPX)) 458 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 459 else if (eth_hdr.h_proto >= htons(ETH_P_802_3_MIN)) 460 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 461 else 462 skb_pull(skb, 2); 463 464 if (ieee80211_has_order(hdr.frame_control)) 465 memcpy(skb_push(skb, 2), &ht_ctrl, 2); 466 if (ieee80211_is_data_qos(hdr.frame_control)) 467 memcpy(skb_push(skb, 2), &qos_ctrl, 2); 468 if (ieee80211_has_a4(hdr.frame_control)) 469 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 470 else 471 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 472 473 return 0; 474 } 475 476 static int 477 mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) 478 { 479 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 480 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 481 bool hdr_trans, unicast, insert_ccmp_hdr = false; 482 u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info; 483 u16 hdr_gap; 484 __le32 *rxv = NULL, *rxd = (__le32 *)skb->data; 485 struct mt76_phy *mphy = &dev->mt76.phy; 486 struct mt7921_phy *phy = &dev->phy; 487 struct ieee80211_supported_band *sband; 488 u32 rxd0 = le32_to_cpu(rxd[0]); 489 u32 rxd1 = le32_to_cpu(rxd[1]); 490 u32 rxd2 = le32_to_cpu(rxd[2]); 491 u32 rxd3 = le32_to_cpu(rxd[3]); 492 u32 rxd4 = le32_to_cpu(rxd[4]); 493 u16 seq_ctrl = 0; 494 __le16 fc = 0; 495 u32 mode = 0; 496 int i, idx; 497 498 memset(status, 0, sizeof(*status)); 499 500 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) 501 return -EINVAL; 502 503 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 504 return -EINVAL; 505 506 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 507 return -EINVAL; 508 509 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 510 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 511 return -EINVAL; 512 513 /* ICV error or CCMP/BIP/WPI MIC error */ 514 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 515 status->flag |= RX_FLAG_ONLY_MONITOR; 516 517 chfreq = FIELD_GET(MT_RXD3_NORMAL_CH_FREQ, rxd3); 518 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 519 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 520 status->wcid = mt7921_rx_get_wcid(dev, idx, unicast); 521 522 if (status->wcid) { 523 struct mt7921_sta *msta; 524 525 msta = container_of(status->wcid, struct mt7921_sta, wcid); 526 spin_lock_bh(&dev->sta_poll_lock); 527 if (list_empty(&msta->poll_list)) 528 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 529 spin_unlock_bh(&dev->sta_poll_lock); 530 } 531 532 mt7921_get_status_freq_info(dev, mphy, status, chfreq); 533 534 switch (status->band) { 535 case NL80211_BAND_5GHZ: 536 sband = &mphy->sband_5g.sband; 537 break; 538 case NL80211_BAND_6GHZ: 539 sband = &mphy->sband_6g.sband; 540 break; 541 default: 542 sband = &mphy->sband_2g.sband; 543 break; 544 } 545 546 if (!sband->channels) 547 return -EINVAL; 548 549 if ((rxd0 & csum_mask) == csum_mask) 550 skb->ip_summed = CHECKSUM_UNNECESSARY; 551 552 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 553 status->flag |= RX_FLAG_FAILED_FCS_CRC; 554 555 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 556 status->flag |= RX_FLAG_MMIC_ERROR; 557 558 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 559 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 560 status->flag |= RX_FLAG_DECRYPTED; 561 status->flag |= RX_FLAG_IV_STRIPPED; 562 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 563 } 564 565 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 566 567 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 568 return -EINVAL; 569 570 rxd += 6; 571 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 572 u32 v0 = le32_to_cpu(rxd[0]); 573 u32 v2 = le32_to_cpu(rxd[2]); 574 575 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 576 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 577 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 578 579 rxd += 4; 580 if ((u8 *)rxd - skb->data >= skb->len) 581 return -EINVAL; 582 } 583 584 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 585 u8 *data = (u8 *)rxd; 586 587 if (status->flag & RX_FLAG_DECRYPTED) { 588 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 589 case MT_CIPHER_AES_CCMP: 590 case MT_CIPHER_CCMP_CCX: 591 case MT_CIPHER_CCMP_256: 592 insert_ccmp_hdr = 593 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 594 fallthrough; 595 case MT_CIPHER_TKIP: 596 case MT_CIPHER_TKIP_NO_MIC: 597 case MT_CIPHER_GCMP: 598 case MT_CIPHER_GCMP_256: 599 status->iv[0] = data[5]; 600 status->iv[1] = data[4]; 601 status->iv[2] = data[3]; 602 status->iv[3] = data[2]; 603 status->iv[4] = data[1]; 604 status->iv[5] = data[0]; 605 break; 606 default: 607 break; 608 } 609 } 610 rxd += 4; 611 if ((u8 *)rxd - skb->data >= skb->len) 612 return -EINVAL; 613 } 614 615 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 616 status->timestamp = le32_to_cpu(rxd[0]); 617 status->flag |= RX_FLAG_MACTIME_START; 618 619 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 620 status->flag |= RX_FLAG_AMPDU_DETAILS; 621 622 /* all subframes of an A-MPDU have the same timestamp */ 623 if (phy->rx_ampdu_ts != status->timestamp) { 624 if (!++phy->ampdu_ref) 625 phy->ampdu_ref++; 626 } 627 phy->rx_ampdu_ts = status->timestamp; 628 629 status->ampdu_ref = phy->ampdu_ref; 630 } 631 632 rxd += 2; 633 if ((u8 *)rxd - skb->data >= skb->len) 634 return -EINVAL; 635 } 636 637 /* RXD Group 3 - P-RXV */ 638 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 639 u8 stbc, gi; 640 u32 v0, v1; 641 bool cck; 642 643 rxv = rxd; 644 rxd += 2; 645 if ((u8 *)rxd - skb->data >= skb->len) 646 return -EINVAL; 647 648 v0 = le32_to_cpu(rxv[0]); 649 v1 = le32_to_cpu(rxv[1]); 650 651 if (v0 & MT_PRXV_HT_AD_CODE) 652 status->enc_flags |= RX_ENC_FLAG_LDPC; 653 654 status->chains = mphy->antenna_mask; 655 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 656 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 657 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 658 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 659 status->signal = -128; 660 for (i = 0; i < hweight8(mphy->antenna_mask); i++) { 661 if (!(status->chains & BIT(i)) || 662 status->chain_signal[i] >= 0) 663 continue; 664 665 status->signal = max(status->signal, 666 status->chain_signal[i]); 667 } 668 669 if (status->signal == -128) 670 status->flag |= RX_FLAG_NO_SIGNAL_VAL; 671 672 stbc = FIELD_GET(MT_PRXV_STBC, v0); 673 gi = FIELD_GET(MT_PRXV_SGI, v0); 674 cck = false; 675 676 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 677 mode = FIELD_GET(MT_PRXV_TX_MODE, v0); 678 679 switch (mode) { 680 case MT_PHY_TYPE_CCK: 681 cck = true; 682 fallthrough; 683 case MT_PHY_TYPE_OFDM: 684 i = mt76_get_rate(&dev->mt76, sband, i, cck); 685 break; 686 case MT_PHY_TYPE_HT_GF: 687 case MT_PHY_TYPE_HT: 688 status->encoding = RX_ENC_HT; 689 if (i > 31) 690 return -EINVAL; 691 break; 692 case MT_PHY_TYPE_VHT: 693 status->nss = 694 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 695 status->encoding = RX_ENC_VHT; 696 if (i > 9) 697 return -EINVAL; 698 break; 699 case MT_PHY_TYPE_HE_MU: 700 case MT_PHY_TYPE_HE_SU: 701 case MT_PHY_TYPE_HE_EXT_SU: 702 case MT_PHY_TYPE_HE_TB: 703 status->nss = 704 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 705 status->encoding = RX_ENC_HE; 706 i &= GENMASK(3, 0); 707 708 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 709 status->he_gi = gi; 710 711 status->he_dcm = !!(idx & MT_PRXV_TX_DCM); 712 break; 713 default: 714 return -EINVAL; 715 } 716 717 status->rate_idx = i; 718 719 switch (FIELD_GET(MT_PRXV_FRAME_MODE, v0)) { 720 case IEEE80211_STA_RX_BW_20: 721 break; 722 case IEEE80211_STA_RX_BW_40: 723 if (mode & MT_PHY_TYPE_HE_EXT_SU && 724 (idx & MT_PRXV_TX_ER_SU_106T)) { 725 status->bw = RATE_INFO_BW_HE_RU; 726 status->he_ru = 727 NL80211_RATE_INFO_HE_RU_ALLOC_106; 728 } else { 729 status->bw = RATE_INFO_BW_40; 730 } 731 break; 732 case IEEE80211_STA_RX_BW_80: 733 status->bw = RATE_INFO_BW_80; 734 break; 735 case IEEE80211_STA_RX_BW_160: 736 status->bw = RATE_INFO_BW_160; 737 break; 738 default: 739 return -EINVAL; 740 } 741 742 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 743 if (mode < MT_PHY_TYPE_HE_SU && gi) 744 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 745 746 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 747 rxd += 18; 748 if ((u8 *)rxd - skb->data >= skb->len) 749 return -EINVAL; 750 } 751 } 752 753 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 754 status->amsdu = !!amsdu_info; 755 if (status->amsdu) { 756 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 757 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 758 } 759 760 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 761 if (hdr_trans && ieee80211_has_morefrags(fc)) { 762 if (mt7921_reverse_frag0_hdr_trans(skb, hdr_gap)) 763 return -EINVAL; 764 hdr_trans = false; 765 } else { 766 skb_pull(skb, hdr_gap); 767 if (!hdr_trans && status->amsdu) { 768 memmove(skb->data + 2, skb->data, 769 ieee80211_get_hdrlen_from_skb(skb)); 770 skb_pull(skb, 2); 771 } 772 } 773 774 if (!hdr_trans) { 775 struct ieee80211_hdr *hdr; 776 777 if (insert_ccmp_hdr) { 778 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 779 780 mt76_insert_ccmp_hdr(skb, key_id); 781 } 782 783 hdr = mt76_skb_get_hdr(skb); 784 fc = hdr->frame_control; 785 if (ieee80211_is_data_qos(fc)) { 786 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 787 qos_ctl = *ieee80211_get_qos_ctl(hdr); 788 } 789 } else { 790 status->flag |= RX_FLAG_8023; 791 } 792 793 mt7921_mac_assoc_rssi(dev, skb); 794 795 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 796 mt7921_mac_decode_he_radiotap(skb, rxv, mode); 797 798 if (!status->wcid || !ieee80211_is_data_qos(fc)) 799 return 0; 800 801 status->aggr = unicast && !ieee80211_is_qos_nullfunc(fc); 802 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 803 status->qos_ctl = qos_ctl; 804 805 return 0; 806 } 807 808 static void 809 mt7921_mac_write_txwi_8023(struct mt7921_dev *dev, __le32 *txwi, 810 struct sk_buff *skb, struct mt76_wcid *wcid) 811 { 812 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 813 u8 fc_type, fc_stype; 814 bool wmm = false; 815 u32 val; 816 817 if (wcid->sta) { 818 struct ieee80211_sta *sta; 819 820 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 821 wmm = sta->wme; 822 } 823 824 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 825 FIELD_PREP(MT_TXD1_TID, tid); 826 827 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 828 val |= MT_TXD1_ETH_802_3; 829 830 txwi[1] |= cpu_to_le32(val); 831 832 fc_type = IEEE80211_FTYPE_DATA >> 2; 833 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 834 835 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 836 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 837 838 txwi[2] |= cpu_to_le32(val); 839 840 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 841 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 842 txwi[7] |= cpu_to_le32(val); 843 } 844 845 static void 846 mt7921_mac_write_txwi_80211(struct mt7921_dev *dev, __le32 *txwi, 847 struct sk_buff *skb, struct ieee80211_key_conf *key) 848 { 849 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 850 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 851 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 852 bool multicast = is_multicast_ether_addr(hdr->addr1); 853 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 854 __le16 fc = hdr->frame_control; 855 u8 fc_type, fc_stype; 856 u32 val; 857 858 if (ieee80211_is_action(fc) && 859 mgmt->u.action.category == WLAN_CATEGORY_BACK && 860 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 861 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 862 863 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 864 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 865 } else if (ieee80211_is_back_req(hdr->frame_control)) { 866 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 867 u16 control = le16_to_cpu(bar->control); 868 869 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 870 } 871 872 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 873 FIELD_PREP(MT_TXD1_HDR_INFO, 874 ieee80211_get_hdrlen_from_skb(skb) / 2) | 875 FIELD_PREP(MT_TXD1_TID, tid); 876 txwi[1] |= cpu_to_le32(val); 877 878 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 879 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 880 881 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 882 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 883 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 884 885 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 886 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 887 val |= MT_TXD2_BIP; 888 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 889 } 890 891 if (!ieee80211_is_data(fc) || multicast || 892 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 893 val |= MT_TXD2_FIX_RATE; 894 895 txwi[2] |= cpu_to_le32(val); 896 897 if (ieee80211_is_beacon(fc)) { 898 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 899 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 900 } 901 902 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 903 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 904 905 if (ieee80211_is_back_req(hdr->frame_control)) { 906 struct ieee80211_bar *bar; 907 908 bar = (struct ieee80211_bar *)skb->data; 909 seqno = le16_to_cpu(bar->start_seq_num); 910 } 911 912 val = MT_TXD3_SN_VALID | 913 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 914 txwi[3] |= cpu_to_le32(val); 915 } 916 917 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 918 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 919 txwi[7] |= cpu_to_le32(val); 920 } 921 922 void mt7921_mac_write_txwi(struct mt7921_dev *dev, __le32 *txwi, 923 struct sk_buff *skb, struct mt76_wcid *wcid, 924 struct ieee80211_key_conf *key, int pid, 925 bool beacon) 926 { 927 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 928 struct ieee80211_vif *vif = info->control.vif; 929 struct mt76_phy *mphy = &dev->mphy; 930 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 931 bool is_mmio = mt76_is_mmio(&dev->mt76); 932 u32 sz_txd = is_mmio ? MT_TXD_SIZE : MT_SDIO_TXD_SIZE; 933 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 934 u16 tx_count = 15; 935 u32 val; 936 937 if (vif) { 938 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 939 940 omac_idx = mvif->omac_idx; 941 wmm_idx = mvif->wmm_idx; 942 } 943 944 if (beacon) { 945 p_fmt = MT_TX_TYPE_FW; 946 q_idx = MT_LMAC_BCN0; 947 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 948 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 949 q_idx = MT_LMAC_ALTX0; 950 } else { 951 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 952 q_idx = wmm_idx * MT7921_MAX_WMM_SETS + 953 mt7921_lmac_mapping(dev, skb_get_queue_mapping(skb)); 954 } 955 956 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 957 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 958 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 959 txwi[0] = cpu_to_le32(val); 960 961 val = MT_TXD1_LONG_FORMAT | 962 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 963 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 964 965 txwi[1] = cpu_to_le32(val); 966 txwi[2] = 0; 967 968 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 969 if (key) 970 val |= MT_TXD3_PROTECT_FRAME; 971 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 972 val |= MT_TXD3_NO_ACK; 973 974 txwi[3] = cpu_to_le32(val); 975 txwi[4] = 0; 976 977 val = FIELD_PREP(MT_TXD5_PID, pid); 978 if (pid >= MT_PACKET_ID_FIRST) 979 val |= MT_TXD5_TX_STATUS_HOST; 980 txwi[5] = cpu_to_le32(val); 981 982 txwi[6] = 0; 983 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 984 985 if (is_8023) 986 mt7921_mac_write_txwi_8023(dev, txwi, skb, wcid); 987 else 988 mt7921_mac_write_txwi_80211(dev, txwi, skb, key); 989 990 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 991 int rateidx = vif ? ffs(vif->bss_conf.basic_rates) - 1 : 0; 992 u16 rate, mode; 993 994 /* hardware won't add HTC for mgmt/ctrl frame */ 995 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 996 997 rate = mt76_calculate_default_rate(mphy, rateidx); 998 mode = rate >> 8; 999 rate &= GENMASK(7, 0); 1000 rate |= FIELD_PREP(MT_TX_RATE_MODE, mode); 1001 1002 val = MT_TXD6_FIXED_BW | 1003 FIELD_PREP(MT_TXD6_TX_RATE, rate); 1004 txwi[6] |= cpu_to_le32(val); 1005 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1006 } 1007 } 1008 EXPORT_SYMBOL_GPL(mt7921_mac_write_txwi); 1009 1010 void mt7921_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1011 { 1012 struct mt7921_sta *msta; 1013 u16 fc, tid; 1014 u32 val; 1015 1016 if (!sta || !(sta->ht_cap.ht_supported || sta->he_cap.has_he)) 1017 return; 1018 1019 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1])); 1020 if (tid >= 6) /* skip VO queue */ 1021 return; 1022 1023 val = le32_to_cpu(txwi[2]); 1024 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1025 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1026 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1027 return; 1028 1029 msta = (struct mt7921_sta *)sta->drv_priv; 1030 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1031 ieee80211_start_tx_ba_session(sta, tid, 0); 1032 } 1033 EXPORT_SYMBOL_GPL(mt7921_tx_check_aggr); 1034 1035 static bool 1036 mt7921_mac_add_txs_skb(struct mt7921_dev *dev, struct mt76_wcid *wcid, int pid, 1037 __le32 *txs_data) 1038 { 1039 struct mt7921_sta *msta = container_of(wcid, struct mt7921_sta, wcid); 1040 struct mt76_sta_stats *stats = &msta->stats; 1041 struct ieee80211_supported_band *sband; 1042 struct mt76_dev *mdev = &dev->mt76; 1043 struct ieee80211_tx_info *info; 1044 struct rate_info rate = {}; 1045 struct sk_buff_head list; 1046 u32 txrate, txs, mode; 1047 struct sk_buff *skb; 1048 bool cck = false; 1049 1050 mt76_tx_status_lock(mdev, &list); 1051 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1052 if (!skb) 1053 goto out; 1054 1055 info = IEEE80211_SKB_CB(skb); 1056 txs = le32_to_cpu(txs_data[0]); 1057 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1058 info->flags |= IEEE80211_TX_STAT_ACK; 1059 1060 info->status.ampdu_len = 1; 1061 info->status.ampdu_ack_len = !!(info->flags & 1062 IEEE80211_TX_STAT_ACK); 1063 1064 info->status.rates[0].idx = -1; 1065 1066 if (!wcid->sta) 1067 goto out; 1068 1069 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1070 1071 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1072 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1073 1074 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1075 stats->tx_nss[rate.nss - 1]++; 1076 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1077 stats->tx_mcs[rate.mcs]++; 1078 1079 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1080 switch (mode) { 1081 case MT_PHY_TYPE_CCK: 1082 cck = true; 1083 fallthrough; 1084 case MT_PHY_TYPE_OFDM: 1085 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) 1086 sband = &dev->mphy.sband_5g.sband; 1087 else 1088 sband = &dev->mphy.sband_2g.sband; 1089 1090 rate.mcs = mt76_get_rate(dev->mphy.dev, sband, rate.mcs, cck); 1091 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1092 break; 1093 case MT_PHY_TYPE_HT: 1094 case MT_PHY_TYPE_HT_GF: 1095 rate.mcs += (rate.nss - 1) * 8; 1096 if (rate.mcs > 31) 1097 goto out; 1098 1099 rate.flags = RATE_INFO_FLAGS_MCS; 1100 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1101 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1102 break; 1103 case MT_PHY_TYPE_VHT: 1104 if (rate.mcs > 9) 1105 goto out; 1106 1107 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1108 break; 1109 case MT_PHY_TYPE_HE_SU: 1110 case MT_PHY_TYPE_HE_EXT_SU: 1111 case MT_PHY_TYPE_HE_TB: 1112 case MT_PHY_TYPE_HE_MU: 1113 if (rate.mcs > 11) 1114 goto out; 1115 1116 rate.he_gi = wcid->rate.he_gi; 1117 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1118 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1119 break; 1120 default: 1121 goto out; 1122 } 1123 stats->tx_mode[mode]++; 1124 1125 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1126 case IEEE80211_STA_RX_BW_160: 1127 rate.bw = RATE_INFO_BW_160; 1128 stats->tx_bw[3]++; 1129 break; 1130 case IEEE80211_STA_RX_BW_80: 1131 rate.bw = RATE_INFO_BW_80; 1132 stats->tx_bw[2]++; 1133 break; 1134 case IEEE80211_STA_RX_BW_40: 1135 rate.bw = RATE_INFO_BW_40; 1136 stats->tx_bw[1]++; 1137 break; 1138 default: 1139 rate.bw = RATE_INFO_BW_20; 1140 stats->tx_bw[0]++; 1141 break; 1142 } 1143 wcid->rate = rate; 1144 1145 out: 1146 if (skb) 1147 mt76_tx_status_skb_done(mdev, skb, &list); 1148 mt76_tx_status_unlock(mdev, &list); 1149 1150 return !!skb; 1151 } 1152 1153 void mt7921_mac_add_txs(struct mt7921_dev *dev, void *data) 1154 { 1155 struct mt7921_sta *msta = NULL; 1156 struct mt76_wcid *wcid; 1157 __le32 *txs_data = data; 1158 u16 wcidx; 1159 u32 txs; 1160 u8 pid; 1161 1162 txs = le32_to_cpu(txs_data[0]); 1163 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) 1164 return; 1165 1166 txs = le32_to_cpu(txs_data[2]); 1167 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1168 1169 txs = le32_to_cpu(txs_data[3]); 1170 pid = FIELD_GET(MT_TXS3_PID, txs); 1171 1172 if (pid < MT_PACKET_ID_FIRST) 1173 return; 1174 1175 if (wcidx >= MT7921_WTBL_SIZE) 1176 return; 1177 1178 rcu_read_lock(); 1179 1180 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1181 if (!wcid) 1182 goto out; 1183 1184 mt7921_mac_add_txs_skb(dev, wcid, pid, txs_data); 1185 1186 if (!wcid->sta) 1187 goto out; 1188 1189 msta = container_of(wcid, struct mt7921_sta, wcid); 1190 spin_lock_bh(&dev->sta_poll_lock); 1191 if (list_empty(&msta->poll_list)) 1192 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1193 spin_unlock_bh(&dev->sta_poll_lock); 1194 1195 out: 1196 rcu_read_unlock(); 1197 } 1198 1199 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1200 struct sk_buff *skb) 1201 { 1202 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1203 __le32 *rxd = (__le32 *)skb->data; 1204 __le32 *end = (__le32 *)&skb->data[skb->len]; 1205 enum rx_pkt_type type; 1206 u16 flag; 1207 1208 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1209 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0])); 1210 1211 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1212 type = PKT_TYPE_NORMAL_MCU; 1213 1214 switch (type) { 1215 case PKT_TYPE_RX_EVENT: 1216 mt7921_mcu_rx_event(dev, skb); 1217 break; 1218 case PKT_TYPE_TXS: 1219 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1220 mt7921_mac_add_txs(dev, rxd); 1221 dev_kfree_skb(skb); 1222 break; 1223 case PKT_TYPE_NORMAL_MCU: 1224 case PKT_TYPE_NORMAL: 1225 if (!mt7921_mac_fill_rx(dev, skb)) { 1226 mt76_rx(&dev->mt76, q, skb); 1227 return; 1228 } 1229 fallthrough; 1230 default: 1231 dev_kfree_skb(skb); 1232 break; 1233 } 1234 } 1235 EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb); 1236 1237 void mt7921_mac_reset_counters(struct mt7921_phy *phy) 1238 { 1239 struct mt7921_dev *dev = phy->dev; 1240 int i; 1241 1242 for (i = 0; i < 4; i++) { 1243 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1244 mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1245 } 1246 1247 dev->mt76.phy.survey_time = ktime_get_boottime(); 1248 memset(&dev->mt76.aggr_stats[0], 0, sizeof(dev->mt76.aggr_stats) / 2); 1249 1250 /* reset airtime counters */ 1251 mt76_rr(dev, MT_MIB_SDR9(0)); 1252 mt76_rr(dev, MT_MIB_SDR36(0)); 1253 mt76_rr(dev, MT_MIB_SDR37(0)); 1254 1255 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1256 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1257 } 1258 1259 void mt7921_mac_set_timing(struct mt7921_phy *phy) 1260 { 1261 s16 coverage_class = phy->coverage_class; 1262 struct mt7921_dev *dev = phy->dev; 1263 u32 val, reg_offset; 1264 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1265 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1266 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1267 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1268 bool is_2ghz = phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ; 1269 int sifs = is_2ghz ? 10 : 16, offset; 1270 1271 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1272 return; 1273 1274 mt76_set(dev, MT_ARB_SCR(0), 1275 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1276 udelay(1); 1277 1278 offset = 3 * coverage_class; 1279 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1280 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1281 1282 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset); 1283 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset); 1284 mt76_wr(dev, MT_TMAC_ICR0(0), 1285 FIELD_PREP(MT_IFS_EIFS, 360) | 1286 FIELD_PREP(MT_IFS_RIFS, 2) | 1287 FIELD_PREP(MT_IFS_SIFS, sifs) | 1288 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1289 1290 if (phy->slottime < 20 || !is_2ghz) 1291 val = MT7921_CFEND_RATE_DEFAULT; 1292 else 1293 val = MT7921_CFEND_RATE_11B; 1294 1295 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val); 1296 mt76_clear(dev, MT_ARB_SCR(0), 1297 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1298 } 1299 1300 static u8 1301 mt7921_phy_get_nf(struct mt7921_phy *phy, int idx) 1302 { 1303 return 0; 1304 } 1305 1306 static void 1307 mt7921_phy_update_channel(struct mt76_phy *mphy, int idx) 1308 { 1309 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 1310 struct mt7921_phy *phy = (struct mt7921_phy *)mphy->priv; 1311 struct mt76_channel_state *state; 1312 u64 busy_time, tx_time, rx_time, obss_time; 1313 int nf; 1314 1315 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1316 MT_MIB_SDR9_BUSY_MASK); 1317 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1318 MT_MIB_SDR36_TXTIME_MASK); 1319 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1320 MT_MIB_SDR37_RXTIME_MASK); 1321 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx), 1322 MT_MIB_OBSSTIME_MASK); 1323 1324 nf = mt7921_phy_get_nf(phy, idx); 1325 if (!phy->noise) 1326 phy->noise = nf << 4; 1327 else if (nf) 1328 phy->noise += nf - (phy->noise >> 4); 1329 1330 state = mphy->chan_state; 1331 state->cc_busy += busy_time; 1332 state->cc_tx += tx_time; 1333 state->cc_rx += rx_time + obss_time; 1334 state->cc_bss_rx += rx_time; 1335 state->noise = -(phy->noise >> 4); 1336 } 1337 1338 void mt7921_update_channel(struct mt76_phy *mphy) 1339 { 1340 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76); 1341 1342 if (mt76_connac_pm_wake(mphy, &dev->pm)) 1343 return; 1344 1345 mt7921_phy_update_channel(mphy, 0); 1346 /* reset obss airtime */ 1347 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1348 1349 mt76_connac_power_save_sched(mphy, &dev->pm); 1350 } 1351 EXPORT_SYMBOL_GPL(mt7921_update_channel); 1352 1353 static void 1354 mt7921_vif_connect_iter(void *priv, u8 *mac, 1355 struct ieee80211_vif *vif) 1356 { 1357 struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv; 1358 struct mt7921_dev *dev = mvif->phy->dev; 1359 1360 if (vif->type == NL80211_IFTYPE_STATION) 1361 ieee80211_disconnect(vif, true); 1362 1363 mt76_connac_mcu_uni_add_dev(&dev->mphy, vif, &mvif->sta.wcid, true); 1364 mt7921_mcu_set_tx(dev, vif); 1365 } 1366 1367 /* system error recovery */ 1368 void mt7921_mac_reset_work(struct work_struct *work) 1369 { 1370 struct mt7921_dev *dev = container_of(work, struct mt7921_dev, 1371 reset_work); 1372 struct ieee80211_hw *hw = mt76_hw(dev); 1373 struct mt76_connac_pm *pm = &dev->pm; 1374 int i; 1375 1376 dev_err(dev->mt76.dev, "chip reset\n"); 1377 dev->hw_full_reset = true; 1378 ieee80211_stop_queues(hw); 1379 1380 cancel_delayed_work_sync(&dev->mphy.mac_work); 1381 cancel_delayed_work_sync(&pm->ps_work); 1382 cancel_work_sync(&pm->wake_work); 1383 1384 mutex_lock(&dev->mt76.mutex); 1385 for (i = 0; i < 10; i++) 1386 if (!mt7921_dev_reset(dev)) 1387 break; 1388 mutex_unlock(&dev->mt76.mutex); 1389 1390 if (i == 10) 1391 dev_err(dev->mt76.dev, "chip reset failed\n"); 1392 1393 if (test_and_clear_bit(MT76_HW_SCANNING, &dev->mphy.state)) { 1394 struct cfg80211_scan_info info = { 1395 .aborted = true, 1396 }; 1397 1398 ieee80211_scan_completed(dev->mphy.hw, &info); 1399 } 1400 1401 dev->hw_full_reset = false; 1402 pm->suspended = false; 1403 ieee80211_wake_queues(hw); 1404 ieee80211_iterate_active_interfaces(hw, 1405 IEEE80211_IFACE_ITER_RESUME_ALL, 1406 mt7921_vif_connect_iter, NULL); 1407 mt76_connac_power_save_sched(&dev->mt76.phy, pm); 1408 } 1409 1410 void mt7921_reset(struct mt76_dev *mdev) 1411 { 1412 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 1413 1414 if (!dev->hw_init_done) 1415 return; 1416 1417 if (dev->hw_full_reset) 1418 return; 1419 1420 queue_work(dev->mt76.wq, &dev->reset_work); 1421 } 1422 1423 void mt7921_mac_update_mib_stats(struct mt7921_phy *phy) 1424 { 1425 struct mt7921_dev *dev = phy->dev; 1426 struct mib_stats *mib = &phy->mib; 1427 int i, aggr0 = 0, aggr1; 1428 u32 val; 1429 1430 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0), 1431 MT_MIB_SDR3_FCS_ERR_MASK); 1432 mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0), 1433 MT_MIB_ACK_FAIL_COUNT_MASK); 1434 mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0), 1435 MT_MIB_BA_FAIL_COUNT_MASK); 1436 mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0), 1437 MT_MIB_RTS_COUNT_MASK); 1438 mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0), 1439 MT_MIB_RTS_FAIL_COUNT_MASK); 1440 1441 mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0)); 1442 mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0)); 1443 mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0)); 1444 1445 val = mt76_rr(dev, MT_MIB_SDR32(0)); 1446 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR9_EBF_CNT_MASK, val); 1447 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR9_IBF_CNT_MASK, val); 1448 1449 val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0)); 1450 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, val); 1451 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, val); 1452 1453 val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0)); 1454 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, val); 1455 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, val); 1456 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, val); 1457 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, val); 1458 1459 mib->rx_mpdu_cnt += mt76_rr(dev, MT_MIB_SDR5(0)); 1460 mib->rx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR22(0)); 1461 mib->rx_ampdu_bytes_cnt += mt76_rr(dev, MT_MIB_SDR23(0)); 1462 mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0)); 1463 1464 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1465 val = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1466 mib->tx_amsdu[i] += val; 1467 mib->tx_amsdu_cnt += val; 1468 } 1469 1470 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 1471 u32 val2; 1472 1473 val = mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 1474 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); 1475 1476 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 1477 dev->mt76.aggr_stats[aggr0++] += val >> 16; 1478 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff; 1479 dev->mt76.aggr_stats[aggr1++] += val2 >> 16; 1480 } 1481 } 1482 1483 void mt7921_mac_work(struct work_struct *work) 1484 { 1485 struct mt7921_phy *phy; 1486 struct mt76_phy *mphy; 1487 1488 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1489 mac_work.work); 1490 phy = mphy->priv; 1491 1492 mt7921_mutex_acquire(phy->dev); 1493 1494 mt76_update_survey(mphy); 1495 if (++mphy->mac_work_count == 2) { 1496 mphy->mac_work_count = 0; 1497 1498 mt7921_mac_update_mib_stats(phy); 1499 } 1500 1501 mt7921_mutex_release(phy->dev); 1502 1503 mt76_tx_status_check(mphy->dev, false); 1504 ieee80211_queue_delayed_work(phy->mt76->hw, &mphy->mac_work, 1505 MT7921_WATCHDOG_TIME); 1506 } 1507 1508 void mt7921_pm_wake_work(struct work_struct *work) 1509 { 1510 struct mt7921_dev *dev; 1511 struct mt76_phy *mphy; 1512 1513 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1514 pm.wake_work); 1515 mphy = dev->phy.mt76; 1516 1517 if (!mt7921_mcu_drv_pmctrl(dev)) { 1518 struct mt76_dev *mdev = &dev->mt76; 1519 int i; 1520 1521 if (mt76_is_sdio(mdev)) { 1522 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1523 mt76_worker_schedule(&mdev->sdio.txrx_worker); 1524 } else { 1525 mt76_for_each_q_rx(mdev, i) 1526 napi_schedule(&mdev->napi[i]); 1527 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1528 mt7921_mcu_tx_cleanup(dev); 1529 } 1530 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) 1531 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1532 MT7921_WATCHDOG_TIME); 1533 } 1534 1535 ieee80211_wake_queues(mphy->hw); 1536 wake_up(&dev->pm.wait); 1537 } 1538 1539 void mt7921_pm_power_save_work(struct work_struct *work) 1540 { 1541 struct mt7921_dev *dev; 1542 unsigned long delta; 1543 struct mt76_phy *mphy; 1544 1545 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1546 pm.ps_work.work); 1547 mphy = dev->phy.mt76; 1548 1549 delta = dev->pm.idle_timeout; 1550 if (test_bit(MT76_HW_SCANNING, &mphy->state) || 1551 test_bit(MT76_HW_SCHED_SCANNING, &mphy->state)) 1552 goto out; 1553 1554 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 1555 delta = dev->pm.last_activity + delta - jiffies; 1556 goto out; 1557 } 1558 1559 if (!mt7921_mcu_fw_pmctrl(dev)) { 1560 cancel_delayed_work_sync(&mphy->mac_work); 1561 return; 1562 } 1563 out: 1564 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 1565 } 1566 1567 void mt7921_coredump_work(struct work_struct *work) 1568 { 1569 struct mt7921_dev *dev; 1570 char *dump, *data; 1571 1572 dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev, 1573 coredump.work.work); 1574 1575 if (time_is_after_jiffies(dev->coredump.last_activity + 1576 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 1577 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 1578 MT76_CONNAC_COREDUMP_TIMEOUT); 1579 return; 1580 } 1581 1582 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 1583 data = dump; 1584 1585 while (true) { 1586 struct sk_buff *skb; 1587 1588 spin_lock_bh(&dev->mt76.lock); 1589 skb = __skb_dequeue(&dev->coredump.msg_list); 1590 spin_unlock_bh(&dev->mt76.lock); 1591 1592 if (!skb) 1593 break; 1594 1595 skb_pull(skb, sizeof(struct mt7921_mcu_rxd)); 1596 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 1597 dev_kfree_skb(skb); 1598 continue; 1599 } 1600 1601 memcpy(data, skb->data, skb->len); 1602 data += skb->len; 1603 1604 dev_kfree_skb(skb); 1605 } 1606 1607 if (dump) 1608 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 1609 GFP_KERNEL); 1610 1611 mt7921_reset(&dev->mt76); 1612 } 1613