1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include "mt7915.h" 5 #include "mac.h" 6 #include "mcu.h" 7 #include "testmode.h" 8 9 enum { 10 TM_CHANGED_TXPOWER, 11 TM_CHANGED_FREQ_OFFSET, 12 13 /* must be last */ 14 NUM_TM_CHANGED 15 }; 16 17 static const u8 tm_change_map[] = { 18 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER, 19 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET, 20 }; 21 22 struct reg_band { 23 u32 band[2]; 24 }; 25 26 #define REG_BAND(_reg) \ 27 { .band[0] = MT_##_reg(0), .band[1] = MT_##_reg(1) } 28 #define REG_BAND_IDX(_reg, _idx) \ 29 { .band[0] = MT_##_reg(0, _idx), .band[1] = MT_##_reg(1, _idx) } 30 31 static const struct reg_band reg_backup_list[] = { 32 REG_BAND_IDX(AGG_PCR0, 0), 33 REG_BAND_IDX(AGG_PCR0, 1), 34 REG_BAND_IDX(AGG_AWSCR0, 0), 35 REG_BAND_IDX(AGG_AWSCR0, 1), 36 REG_BAND_IDX(AGG_AWSCR0, 2), 37 REG_BAND_IDX(AGG_AWSCR0, 3), 38 REG_BAND(AGG_MRCR), 39 REG_BAND(TMAC_TFCR0), 40 REG_BAND(TMAC_TCR0), 41 REG_BAND(AGG_ATCR1), 42 REG_BAND(AGG_ATCR3), 43 REG_BAND(TMAC_TRCR0), 44 REG_BAND(TMAC_ICR0), 45 REG_BAND_IDX(ARB_DRNGR0, 0), 46 REG_BAND_IDX(ARB_DRNGR0, 1), 47 REG_BAND(WF_RFCR), 48 REG_BAND(WF_RFCR1), 49 }; 50 51 static int 52 mt7915_tm_set_tx_power(struct mt7915_phy *phy) 53 { 54 struct mt7915_dev *dev = phy->dev; 55 struct mt76_phy *mphy = phy->mt76; 56 struct cfg80211_chan_def *chandef = &mphy->chandef; 57 int freq = chandef->center_freq1; 58 int ret; 59 struct { 60 u8 format_id; 61 u8 dbdc_idx; 62 s8 tx_power; 63 u8 ant_idx; /* Only 0 is valid */ 64 u8 center_chan; 65 u8 rsv[3]; 66 } __packed req = { 67 .format_id = 0xf, 68 .dbdc_idx = phy != &dev->phy, 69 .center_chan = ieee80211_frequency_to_channel(freq), 70 }; 71 u8 *tx_power = NULL; 72 73 if (phy->mt76->test.state != MT76_TM_STATE_OFF) 74 tx_power = phy->mt76->test.tx_power; 75 76 /* Tx power of the other antennas are the same as antenna 0 */ 77 if (tx_power && tx_power[0]) 78 req.tx_power = tx_power[0]; 79 80 ret = mt76_mcu_send_msg(&dev->mt76, 81 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 82 &req, sizeof(req), false); 83 84 return ret; 85 } 86 87 static int 88 mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val) 89 { 90 struct mt7915_dev *dev = phy->dev; 91 struct mt7915_tm_cmd req = { 92 .testmode_en = en, 93 .param_idx = MCU_ATE_SET_FREQ_OFFSET, 94 .param.freq.band = phy != &dev->phy, 95 .param.freq.freq_offset = cpu_to_le32(val), 96 }; 97 98 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 99 sizeof(req), false); 100 } 101 102 static int 103 mt7915_tm_mode_ctrl(struct mt7915_dev *dev, bool enable) 104 { 105 struct { 106 u8 format_id; 107 bool enable; 108 u8 rsv[2]; 109 } __packed req = { 110 .format_id = 0x6, 111 .enable = enable, 112 }; 113 114 return mt76_mcu_send_msg(&dev->mt76, 115 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 116 &req, sizeof(req), false); 117 } 118 119 static int 120 mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en) 121 { 122 struct mt7915_dev *dev = phy->dev; 123 struct mt7915_tm_cmd req = { 124 .testmode_en = 1, 125 .param_idx = MCU_ATE_SET_TRX, 126 .param.trx.type = type, 127 .param.trx.enable = en, 128 .param.trx.band = phy != &dev->phy, 129 }; 130 131 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 132 sizeof(req), false); 133 } 134 135 static int 136 mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid) 137 { 138 struct mt7915_dev *dev = phy->dev; 139 struct mt7915_tm_cmd req = { 140 .testmode_en = 1, 141 .param_idx = MCU_ATE_CLEAN_TXQUEUE, 142 .param.clean.wcid = wcid, 143 .param.clean.band = phy != &dev->phy, 144 }; 145 146 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 147 sizeof(req), false); 148 } 149 150 static int 151 mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs) 152 { 153 struct mt7915_dev *dev = phy->dev; 154 struct mt7915_tm_cmd req = { 155 .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF), 156 .param_idx = MCU_ATE_SET_SLOT_TIME, 157 .param.slot.slot_time = slot_time, 158 .param.slot.sifs = sifs, 159 .param.slot.rifs = 2, 160 .param.slot.eifs = cpu_to_le16(60), 161 .param.slot.band = phy != &dev->phy, 162 }; 163 164 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 165 sizeof(req), false); 166 } 167 168 static int 169 mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu) 170 { 171 struct mt7915_dev *dev = phy->dev; 172 u32 op_mode; 173 174 if (!enable) 175 op_mode = TAM_ARB_OP_MODE_NORMAL; 176 else if (mu) 177 op_mode = TAM_ARB_OP_MODE_TEST; 178 else 179 op_mode = TAM_ARB_OP_MODE_FORCE_SU; 180 181 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode); 182 } 183 184 static int 185 mt7915_tm_set_wmm_qid(struct mt7915_dev *dev, u8 qid, u8 aifs, u8 cw_min, 186 u16 cw_max, u16 txop) 187 { 188 struct mt7915_mcu_tx req = { .total = 1 }; 189 struct edca *e = &req.edca[0]; 190 191 e->queue = qid; 192 e->set = WMM_PARAM_SET; 193 194 e->aifs = aifs; 195 e->cw_min = cw_min; 196 e->cw_max = cpu_to_le16(cw_max); 197 e->txop = cpu_to_le16(txop); 198 199 return mt7915_mcu_update_edca(dev, &req); 200 } 201 202 static int 203 mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode) 204 { 205 #define TM_DEFAULT_SIFS 10 206 #define TM_MAX_SIFS 127 207 #define TM_MAX_AIFSN 0xf 208 #define TM_MIN_AIFSN 0x1 209 #define BBP_PROC_TIME 1500 210 struct mt7915_dev *dev = phy->dev; 211 u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6; 212 u8 slot_time = 9, sifs = TM_DEFAULT_SIFS; 213 u8 aifsn = TM_MIN_AIFSN; 214 u32 i2t_time, tr2t_time, txv_time; 215 bool ext_phy = phy != &dev->phy; 216 u16 cw = 0; 217 218 if (ipg < sig_ext + slot_time + sifs) 219 ipg = 0; 220 221 if (!ipg) 222 goto done; 223 224 ipg -= sig_ext; 225 226 if (ipg <= (TM_MAX_SIFS + slot_time)) { 227 sifs = ipg - slot_time; 228 } else { 229 u32 val = (ipg + slot_time) / slot_time; 230 231 while (val >>= 1) 232 cw++; 233 234 if (cw > 16) 235 cw = 16; 236 237 ipg -= ((1 << cw) - 1) * slot_time; 238 239 aifsn = ipg / slot_time; 240 if (aifsn > TM_MAX_AIFSN) 241 aifsn = TM_MAX_AIFSN; 242 243 ipg -= aifsn * slot_time; 244 245 if (ipg > TM_DEFAULT_SIFS) { 246 if (ipg < TM_MAX_SIFS) 247 sifs = ipg; 248 else 249 sifs = TM_MAX_SIFS; 250 } 251 } 252 done: 253 txv_time = mt76_get_field(dev, MT_TMAC_ATCR(ext_phy), 254 MT_TMAC_ATCR_TXV_TOUT); 255 txv_time *= 50; /* normal clock time */ 256 257 i2t_time = (slot_time * 1000 - txv_time - BBP_PROC_TIME) / 50; 258 tr2t_time = (sifs * 1000 - txv_time - BBP_PROC_TIME) / 50; 259 260 mt76_set(dev, MT_TMAC_TRCR0(ext_phy), 261 FIELD_PREP(MT_TMAC_TRCR0_TR2T_CHK, tr2t_time) | 262 FIELD_PREP(MT_TMAC_TRCR0_I2T_CHK, i2t_time)); 263 264 mt7915_tm_set_slot_time(phy, slot_time, sifs); 265 266 return mt7915_tm_set_wmm_qid(dev, 267 mt7915_lmac_mapping(dev, IEEE80211_AC_BE), 268 aifsn, cw, cw, 0); 269 } 270 271 static int 272 mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time) 273 { 274 struct mt76_phy *mphy = phy->mt76; 275 struct mt76_testmode_data *td = &mphy->test; 276 struct ieee80211_supported_band *sband; 277 struct rate_info rate = {}; 278 u16 flags = 0, tx_len; 279 u32 bitrate; 280 int ret; 281 282 if (!tx_time) 283 return 0; 284 285 rate.mcs = td->tx_rate_idx; 286 rate.nss = td->tx_rate_nss; 287 288 switch (td->tx_rate_mode) { 289 case MT76_TM_TX_MODE_CCK: 290 case MT76_TM_TX_MODE_OFDM: 291 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 292 sband = &mphy->sband_5g.sband; 293 else 294 sband = &mphy->sband_2g.sband; 295 296 rate.legacy = sband->bitrates[rate.mcs].bitrate; 297 break; 298 case MT76_TM_TX_MODE_HT: 299 rate.mcs += rate.nss * 8; 300 flags |= RATE_INFO_FLAGS_MCS; 301 302 if (td->tx_rate_sgi) 303 flags |= RATE_INFO_FLAGS_SHORT_GI; 304 break; 305 case MT76_TM_TX_MODE_VHT: 306 flags |= RATE_INFO_FLAGS_VHT_MCS; 307 308 if (td->tx_rate_sgi) 309 flags |= RATE_INFO_FLAGS_SHORT_GI; 310 break; 311 case MT76_TM_TX_MODE_HE_SU: 312 case MT76_TM_TX_MODE_HE_EXT_SU: 313 case MT76_TM_TX_MODE_HE_TB: 314 case MT76_TM_TX_MODE_HE_MU: 315 rate.he_gi = td->tx_rate_sgi; 316 flags |= RATE_INFO_FLAGS_HE_MCS; 317 break; 318 default: 319 break; 320 } 321 rate.flags = flags; 322 323 switch (mphy->chandef.width) { 324 case NL80211_CHAN_WIDTH_160: 325 case NL80211_CHAN_WIDTH_80P80: 326 rate.bw = RATE_INFO_BW_160; 327 break; 328 case NL80211_CHAN_WIDTH_80: 329 rate.bw = RATE_INFO_BW_80; 330 break; 331 case NL80211_CHAN_WIDTH_40: 332 rate.bw = RATE_INFO_BW_40; 333 break; 334 default: 335 rate.bw = RATE_INFO_BW_20; 336 break; 337 } 338 339 bitrate = cfg80211_calculate_bitrate(&rate); 340 tx_len = bitrate * tx_time / 10 / 8; 341 342 ret = mt76_testmode_alloc_skb(phy->mt76, tx_len); 343 if (ret) 344 return ret; 345 346 return 0; 347 } 348 349 static void 350 mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) 351 { 352 int n_regs = ARRAY_SIZE(reg_backup_list); 353 struct mt7915_dev *dev = phy->dev; 354 bool ext_phy = phy != &dev->phy; 355 u32 *b = phy->test.reg_backup; 356 int i; 357 358 if (phy->mt76->test.state == MT76_TM_STATE_OFF) { 359 for (i = 0; i < n_regs; i++) 360 mt76_wr(dev, reg_backup_list[i].band[ext_phy], b[i]); 361 return; 362 } 363 364 if (!b) { 365 b = devm_kzalloc(dev->mt76.dev, 4 * n_regs, GFP_KERNEL); 366 if (!b) 367 return; 368 369 phy->test.reg_backup = b; 370 for (i = 0; i < n_regs; i++) 371 b[i] = mt76_rr(dev, reg_backup_list[i].band[ext_phy]); 372 } 373 374 mt76_clear(dev, MT_AGG_PCR0(ext_phy, 0), MT_AGG_PCR0_MM_PROT | 375 MT_AGG_PCR0_GF_PROT | MT_AGG_PCR0_ERP_PROT | 376 MT_AGG_PCR0_VHT_PROT | MT_AGG_PCR0_BW20_PROT | 377 MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT); 378 mt76_set(dev, MT_AGG_PCR0(ext_phy, 0), MT_AGG_PCR0_PTA_WIN_DIS); 379 380 mt76_wr(dev, MT_AGG_PCR0(ext_phy, 1), MT_AGG_PCR1_RTS0_NUM_THRES | 381 MT_AGG_PCR1_RTS0_LEN_THRES); 382 383 mt76_clear(dev, MT_AGG_MRCR(ext_phy), MT_AGG_MRCR_BAR_CNT_LIMIT | 384 MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT | 385 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT); 386 387 mt76_rmw(dev, MT_AGG_MRCR(ext_phy), MT_AGG_MRCR_RTS_FAIL_LIMIT | 388 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 389 FIELD_PREP(MT_AGG_MRCR_RTS_FAIL_LIMIT, 1) | 390 FIELD_PREP(MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 1)); 391 392 mt76_wr(dev, MT_TMAC_TFCR0(ext_phy), 0); 393 mt76_clear(dev, MT_TMAC_TCR0(ext_phy), MT_TMAC_TCR0_TBTT_STOP_CTRL); 394 395 /* config rx filter for testmode rx */ 396 mt76_wr(dev, MT_WF_RFCR(ext_phy), 0xcf70a); 397 mt76_wr(dev, MT_WF_RFCR1(ext_phy), 0); 398 } 399 400 static void 401 mt7915_tm_init(struct mt7915_phy *phy, bool en) 402 { 403 struct mt7915_dev *dev = phy->dev; 404 405 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 406 return; 407 408 mt7915_mcu_set_sku_en(phy, !en); 409 410 mt7915_tm_mode_ctrl(dev, en); 411 mt7915_tm_reg_backup_restore(phy); 412 mt7915_tm_set_trx(phy, TM_MAC_TXRX, !en); 413 414 mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en); 415 mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en); 416 417 if (!en) 418 mt7915_tm_set_tam_arb(phy, en, 0); 419 } 420 421 static void 422 mt7915_tm_update_channel(struct mt7915_phy *phy) 423 { 424 mutex_unlock(&phy->dev->mt76.mutex); 425 mt7915_set_channel(phy); 426 mutex_lock(&phy->dev->mt76.mutex); 427 428 mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH)); 429 } 430 431 static void 432 mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en) 433 { 434 static const u8 spe_idx_map[] = {0, 0, 1, 0, 3, 2, 4, 0, 435 9, 8, 6, 10, 16, 12, 18, 0}; 436 struct mt76_testmode_data *td = &phy->mt76->test; 437 struct mt7915_dev *dev = phy->dev; 438 struct ieee80211_tx_info *info; 439 u8 duty_cycle = td->tx_duty_cycle; 440 u32 tx_time = td->tx_time; 441 u32 ipg = td->tx_ipg; 442 443 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false); 444 mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx); 445 446 if (en) { 447 mt7915_tm_update_channel(phy); 448 449 if (td->tx_spe_idx) { 450 phy->test.spe_idx = td->tx_spe_idx; 451 } else { 452 u8 tx_ant = td->tx_antenna_mask; 453 454 if (phy != &dev->phy) 455 tx_ant >>= 2; 456 phy->test.spe_idx = spe_idx_map[tx_ant]; 457 } 458 } 459 460 mt7915_tm_set_tam_arb(phy, en, 461 td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU); 462 463 /* if all three params are set, duty_cycle will be ignored */ 464 if (duty_cycle && tx_time && !ipg) { 465 ipg = tx_time * 100 / duty_cycle - tx_time; 466 } else if (duty_cycle && !tx_time && ipg) { 467 if (duty_cycle < 100) 468 tx_time = duty_cycle * ipg / (100 - duty_cycle); 469 } 470 471 mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode); 472 mt7915_tm_set_tx_len(phy, tx_time); 473 474 if (ipg) 475 td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2; 476 477 if (!en || !td->tx_skb) 478 return; 479 480 info = IEEE80211_SKB_CB(td->tx_skb); 481 info->control.vif = phy->monitor_vif; 482 483 mt7915_tm_set_trx(phy, TM_MAC_TX, en); 484 } 485 486 static void 487 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en) 488 { 489 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false); 490 491 if (en) { 492 struct mt7915_dev *dev = phy->dev; 493 494 mt7915_tm_update_channel(phy); 495 496 /* read-clear */ 497 mt76_rr(dev, MT_MIB_SDR3(phy != &dev->phy)); 498 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en); 499 } 500 } 501 502 static int 503 mt7915_tm_rf_switch_mode(struct mt7915_dev *dev, u32 oper) 504 { 505 struct mt7915_tm_rf_test req = { 506 .op.op_mode = cpu_to_le32(oper), 507 }; 508 509 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 510 sizeof(req), true); 511 } 512 513 static int 514 mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en) 515 { 516 #define TX_CONT_START 0x05 517 #define TX_CONT_STOP 0x06 518 struct mt7915_dev *dev = phy->dev; 519 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 520 int freq1 = ieee80211_frequency_to_channel(chandef->center_freq1); 521 struct mt76_testmode_data *td = &phy->mt76->test; 522 u32 func_idx = en ? TX_CONT_START : TX_CONT_STOP; 523 u8 rate_idx = td->tx_rate_idx, mode; 524 u16 rateval; 525 struct mt7915_tm_rf_test req = { 526 .action = 1, 527 .icap_len = 120, 528 .op.rf.func_idx = cpu_to_le32(func_idx), 529 }; 530 struct tm_tx_cont *tx_cont = &req.op.rf.param.tx_cont; 531 532 tx_cont->control_ch = chandef->chan->hw_value; 533 tx_cont->center_ch = freq1; 534 tx_cont->tx_ant = td->tx_antenna_mask; 535 tx_cont->band = phy != &dev->phy; 536 537 switch (chandef->width) { 538 case NL80211_CHAN_WIDTH_40: 539 tx_cont->bw = CMD_CBW_40MHZ; 540 break; 541 case NL80211_CHAN_WIDTH_80: 542 tx_cont->bw = CMD_CBW_80MHZ; 543 break; 544 case NL80211_CHAN_WIDTH_80P80: 545 tx_cont->bw = CMD_CBW_8080MHZ; 546 break; 547 case NL80211_CHAN_WIDTH_160: 548 tx_cont->bw = CMD_CBW_160MHZ; 549 break; 550 case NL80211_CHAN_WIDTH_5: 551 tx_cont->bw = CMD_CBW_5MHZ; 552 break; 553 case NL80211_CHAN_WIDTH_10: 554 tx_cont->bw = CMD_CBW_10MHZ; 555 break; 556 case NL80211_CHAN_WIDTH_20: 557 tx_cont->bw = CMD_CBW_20MHZ; 558 break; 559 case NL80211_CHAN_WIDTH_20_NOHT: 560 tx_cont->bw = CMD_CBW_20MHZ; 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 if (!en) { 567 req.op.rf.param.func_data = cpu_to_le32(phy != &dev->phy); 568 goto out; 569 } 570 571 if (td->tx_rate_mode <= MT76_TM_TX_MODE_OFDM) { 572 struct ieee80211_supported_band *sband; 573 u8 idx = rate_idx; 574 575 if (chandef->chan->band == NL80211_BAND_5GHZ) 576 sband = &phy->mt76->sband_5g.sband; 577 else 578 sband = &phy->mt76->sband_2g.sband; 579 580 if (td->tx_rate_mode == MT76_TM_TX_MODE_OFDM) 581 idx += 4; 582 rate_idx = sband->bitrates[idx].hw_value & 0xff; 583 } 584 585 switch (td->tx_rate_mode) { 586 case MT76_TM_TX_MODE_CCK: 587 mode = MT_PHY_TYPE_CCK; 588 break; 589 case MT76_TM_TX_MODE_OFDM: 590 mode = MT_PHY_TYPE_OFDM; 591 break; 592 case MT76_TM_TX_MODE_HT: 593 mode = MT_PHY_TYPE_HT; 594 break; 595 case MT76_TM_TX_MODE_VHT: 596 mode = MT_PHY_TYPE_VHT; 597 break; 598 case MT76_TM_TX_MODE_HE_SU: 599 mode = MT_PHY_TYPE_HE_SU; 600 break; 601 case MT76_TM_TX_MODE_HE_EXT_SU: 602 mode = MT_PHY_TYPE_HE_EXT_SU; 603 break; 604 case MT76_TM_TX_MODE_HE_TB: 605 mode = MT_PHY_TYPE_HE_TB; 606 break; 607 case MT76_TM_TX_MODE_HE_MU: 608 mode = MT_PHY_TYPE_HE_MU; 609 break; 610 default: 611 return -EINVAL; 612 } 613 614 rateval = mode << 6 | rate_idx; 615 tx_cont->rateval = cpu_to_le16(rateval); 616 617 out: 618 if (!en) { 619 int ret; 620 621 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 622 sizeof(req), true); 623 if (ret) 624 return ret; 625 626 return mt7915_tm_rf_switch_mode(dev, RF_OPER_NORMAL); 627 } 628 629 mt7915_tm_rf_switch_mode(dev, RF_OPER_RF_TEST); 630 mt7915_tm_update_channel(phy); 631 632 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 633 sizeof(req), true); 634 } 635 636 static void 637 mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed) 638 { 639 struct mt76_testmode_data *td = &phy->mt76->test; 640 bool en = phy->mt76->test.state != MT76_TM_STATE_OFF; 641 642 if (changed & BIT(TM_CHANGED_FREQ_OFFSET)) 643 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0); 644 if (changed & BIT(TM_CHANGED_TXPOWER)) 645 mt7915_tm_set_tx_power(phy); 646 } 647 648 static int 649 mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state) 650 { 651 struct mt76_testmode_data *td = &mphy->test; 652 struct mt7915_phy *phy = mphy->priv; 653 enum mt76_testmode_state prev_state = td->state; 654 655 mphy->test.state = state; 656 657 if (prev_state == MT76_TM_STATE_TX_FRAMES || 658 state == MT76_TM_STATE_TX_FRAMES) 659 mt7915_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES); 660 else if (prev_state == MT76_TM_STATE_RX_FRAMES || 661 state == MT76_TM_STATE_RX_FRAMES) 662 mt7915_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES); 663 else if (prev_state == MT76_TM_STATE_TX_CONT || 664 state == MT76_TM_STATE_TX_CONT) 665 mt7915_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT); 666 else if (prev_state == MT76_TM_STATE_OFF || 667 state == MT76_TM_STATE_OFF) 668 mt7915_tm_init(phy, !(state == MT76_TM_STATE_OFF)); 669 670 if ((state == MT76_TM_STATE_IDLE && 671 prev_state == MT76_TM_STATE_OFF) || 672 (state == MT76_TM_STATE_OFF && 673 prev_state == MT76_TM_STATE_IDLE)) { 674 u32 changed = 0; 675 int i; 676 677 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { 678 u16 cur = tm_change_map[i]; 679 680 if (td->param_set[cur / 32] & BIT(cur % 32)) 681 changed |= BIT(i); 682 } 683 684 mt7915_tm_update_params(phy, changed); 685 } 686 687 return 0; 688 } 689 690 static int 691 mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb, 692 enum mt76_testmode_state new_state) 693 { 694 struct mt76_testmode_data *td = &mphy->test; 695 struct mt7915_phy *phy = mphy->priv; 696 u32 changed = 0; 697 int i; 698 699 BUILD_BUG_ON(NUM_TM_CHANGED >= 32); 700 701 if (new_state == MT76_TM_STATE_OFF || 702 td->state == MT76_TM_STATE_OFF) 703 return 0; 704 705 if (td->tx_antenna_mask & ~mphy->chainmask) 706 return -EINVAL; 707 708 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { 709 if (tb[tm_change_map[i]]) 710 changed |= BIT(i); 711 } 712 713 mt7915_tm_update_params(phy, changed); 714 715 return 0; 716 } 717 718 static int 719 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg) 720 { 721 struct mt7915_phy *phy = mphy->priv; 722 struct mt7915_dev *dev = phy->dev; 723 bool ext_phy = phy != &dev->phy; 724 enum mt76_rxq_id q; 725 void *rx, *rssi; 726 u16 fcs_err; 727 int i; 728 729 rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX); 730 if (!rx) 731 return -ENOMEM; 732 733 if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset)) 734 return -ENOMEM; 735 736 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI); 737 if (!rssi) 738 return -ENOMEM; 739 740 for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++) 741 if (nla_put_u8(msg, i, phy->test.last_rcpi[i])) 742 return -ENOMEM; 743 744 nla_nest_end(msg, rssi); 745 746 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI); 747 if (!rssi) 748 return -ENOMEM; 749 750 for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++) 751 if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i])) 752 return -ENOMEM; 753 754 nla_nest_end(msg, rssi); 755 756 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI); 757 if (!rssi) 758 return -ENOMEM; 759 760 for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++) 761 if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i])) 762 return -ENOMEM; 763 764 nla_nest_end(msg, rssi); 765 766 if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr)) 767 return -ENOMEM; 768 769 nla_nest_end(msg, rx); 770 771 fcs_err = mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 772 MT_MIB_SDR3_FCS_ERR_MASK); 773 q = ext_phy ? MT_RXQ_EXT : MT_RXQ_MAIN; 774 mphy->test.rx_stats.packets[q] += fcs_err; 775 mphy->test.rx_stats.fcs_error[q] += fcs_err; 776 777 return 0; 778 } 779 780 const struct mt76_testmode_ops mt7915_testmode_ops = { 781 .set_state = mt7915_tm_set_state, 782 .set_params = mt7915_tm_set_params, 783 .dump_stats = mt7915_tm_dump_stats, 784 }; 785