1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_REGS_H 5 #define __MT7915_REGS_H 6 7 /* MCU WFDMA1 */ 8 #define MT_MCU_WFDMA1_BASE 0x3000 9 #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 10 11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108) 12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 13 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 14 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 15 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 16 17 #define MT_PLE_BASE 0x8000 18 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 19 20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0) 21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4) 22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8) 23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc) 24 25 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \ 26 ((n) << 2)) 27 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 28 29 #define MT_MDP_BASE 0xf000 30 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 31 32 #define MT_MDP_DCR0 MT_MDP(0x000) 33 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 34 35 #define MT_MDP_DCR1 MT_MDP(0x004) 36 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 37 38 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8)) 39 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 40 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 41 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 42 43 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8)) 44 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 45 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 46 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 47 #define MT_MDP_TO_HIF 0 48 #define MT_MDP_TO_WM 1 49 50 /* TMAC: band 0(0x21000), band 1(0xa1000) */ 51 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000) 52 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 53 54 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 55 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 56 57 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090) 58 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094) 59 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 60 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 61 62 #define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, 0x098) 63 #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0) 64 65 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c) 66 #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0) 67 #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16) 68 69 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4) 70 #define MT_IFS_EIFS GENMASK(8, 0) 71 #define MT_IFS_RIFS GENMASK(14, 10) 72 #define MT_IFS_SIFS GENMASK(22, 16) 73 #define MT_IFS_SLOT GENMASK(30, 24) 74 75 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4) 76 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 77 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 78 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 79 80 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0) 81 82 #define MT_WF_DMA_BASE(_band) ((_band) ? 0xa1e00 : 0x21e00) 83 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 84 85 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 86 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 87 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 88 89 /* ETBF: band 0(0x24000), band 1(0xa4000) */ 90 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0xa4000 : 0x24000) 91 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 92 93 #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040) 94 #define MT_ETBF_TX_FB_CPL GENMASK(31, 16) 95 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0) 96 97 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0) 98 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 99 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 100 101 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8) 102 #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 103 #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 104 #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 105 #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 106 107 /* LPON: band 0(0x24200), band 1(0xa4200) */ 108 #define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200) 109 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 110 111 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080) 112 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084) 113 114 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4) 115 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 116 #define MT_LPON_TCR_SW_WRITE BIT(0) 117 118 /* MIB: band 0(0x24800), band 1(0xa4800) */ 119 #define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800) 120 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 121 122 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014) 123 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 124 125 #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c) 126 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0) 127 128 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048) 129 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0) 130 131 #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090) 132 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 133 134 #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098) 135 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0) 136 #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c) 137 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0) 138 139 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0) 140 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4) 141 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc) 142 143 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4)) 144 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 145 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 146 147 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4)) 148 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 149 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 150 151 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4)) 152 #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0) 153 154 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2)) 155 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2)) 156 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2)) 157 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 158 159 #define MT_WTBLON_TOP_BASE 0x34000 160 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 161 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0) 162 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 163 164 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030) 165 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 166 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 167 #define MT_WTBL_UPDATE_BUSY BIT(31) 168 169 #define MT_WTBL_BASE 0x38000 170 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 171 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 172 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 173 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 174 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 175 176 /* AGG: band 0(0x20800), band 1(0xa0800) */ 177 #define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800) 178 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 179 180 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4) 181 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4) 182 #define MT_AGG_PCR0_MM_PROT BIT(0) 183 #define MT_AGG_PCR0_GF_PROT BIT(1) 184 #define MT_AGG_PCR0_BW20_PROT BIT(2) 185 #define MT_AGG_PCR0_BW40_PROT BIT(4) 186 #define MT_AGG_PCR0_BW80_PROT BIT(6) 187 #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 188 #define MT_AGG_PCR0_VHT_PROT BIT(13) 189 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 190 191 #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 192 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 193 194 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084) 195 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 196 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 197 198 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098) 199 #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 200 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 201 #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 202 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 203 204 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0) 205 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4) 206 207 /* ARB: band 0(0x20c00), band 1(0xa0c00) */ 208 #define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00) 209 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 210 211 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080) 212 #define MT_ARB_SCR_TX_DISABLE BIT(8) 213 #define MT_ARB_SCR_RX_DISABLE BIT(9) 214 215 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4) 216 217 /* RMAC: band 0(0x21400), band 1(0xa1400) */ 218 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400) 219 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 220 221 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 222 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 223 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 224 #define MT_WF_RFCR_DROP_VERSION BIT(3) 225 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 226 #define MT_WF_RFCR_DROP_MCAST BIT(5) 227 #define MT_WF_RFCR_DROP_BCAST BIT(6) 228 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 229 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 230 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 231 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 232 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 233 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 234 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 235 #define MT_WF_RFCR_DROP_CTS BIT(14) 236 #define MT_WF_RFCR_DROP_RTS BIT(15) 237 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 238 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 239 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 240 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 241 #define MT_WF_RFCR_DROP_NDPA BIT(20) 242 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 243 244 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 245 #define MT_WF_RFCR1_DROP_ACK BIT(4) 246 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 247 #define MT_WF_RFCR1_DROP_BA BIT(6) 248 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 249 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 250 251 #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4) 252 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 253 #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30) 254 255 #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8) 256 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0) 257 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 258 259 /* WFDMA0 */ 260 #define MT_WFDMA0_BASE 0xd4000 261 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 262 263 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 264 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 265 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 266 267 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 268 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 269 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 270 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 271 272 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 273 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 274 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 275 276 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 277 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 278 279 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500) 280 281 #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680) 282 #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684) 283 #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688) 284 285 /* WFDMA1 */ 286 #define MT_WFDMA1_BASE 0xd5000 287 #define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs)) 288 289 #define MT_WFDMA1_RST MT_WFDMA1(0x100) 290 #define MT_WFDMA1_RST_LOGIC_RST BIT(4) 291 #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5) 292 293 #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c) 294 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0) 295 #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1) 296 #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2) 297 298 #define MT_MCU_CMD MT_WFDMA1(0x1f0) 299 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 300 #define MT_MCU_CMD_STOP_DMA BIT(2) 301 #define MT_MCU_CMD_RESET_DONE BIT(3) 302 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 303 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 304 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 305 306 #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208) 307 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0) 308 #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2) 309 #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28) 310 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27) 311 312 #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c) 313 #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0) 314 315 #define MT_TX_RING_BASE MT_WFDMA1(0x300) 316 #define MT_RX_EVENT_RING_BASE MT_WFDMA1(0x500) 317 318 #define MT_WFDMA1_TX_RING0_EXT_CTRL MT_WFDMA1(0x600) 319 #define MT_WFDMA1_TX_RING1_EXT_CTRL MT_WFDMA1(0x604) 320 #define MT_WFDMA1_TX_RING2_EXT_CTRL MT_WFDMA1(0x608) 321 #define MT_WFDMA1_TX_RING3_EXT_CTRL MT_WFDMA1(0x60c) 322 #define MT_WFDMA1_TX_RING4_EXT_CTRL MT_WFDMA1(0x610) 323 #define MT_WFDMA1_TX_RING5_EXT_CTRL MT_WFDMA1(0x614) 324 #define MT_WFDMA1_TX_RING6_EXT_CTRL MT_WFDMA1(0x618) 325 #define MT_WFDMA1_TX_RING7_EXT_CTRL MT_WFDMA1(0x61c) 326 327 #define MT_WFDMA1_TX_RING16_EXT_CTRL MT_WFDMA1(0x640) 328 #define MT_WFDMA1_TX_RING17_EXT_CTRL MT_WFDMA1(0x644) 329 #define MT_WFDMA1_TX_RING18_EXT_CTRL MT_WFDMA1(0x648) 330 #define MT_WFDMA1_TX_RING19_EXT_CTRL MT_WFDMA1(0x64c) 331 #define MT_WFDMA1_TX_RING20_EXT_CTRL MT_WFDMA1(0x650) 332 #define MT_WFDMA1_TX_RING21_EXT_CTRL MT_WFDMA1(0x654) 333 #define MT_WFDMA1_TX_RING22_EXT_CTRL MT_WFDMA1(0x658) 334 #define MT_WFDMA1_TX_RING23_EXT_CTRL MT_WFDMA1(0x65c) 335 336 #define MT_WFDMA1_RX_RING0_EXT_CTRL MT_WFDMA1(0x680) 337 #define MT_WFDMA1_RX_RING1_EXT_CTRL MT_WFDMA1(0x684) 338 #define MT_WFDMA1_RX_RING2_EXT_CTRL MT_WFDMA1(0x688) 339 #define MT_WFDMA1_RX_RING3_EXT_CTRL MT_WFDMA1(0x68c) 340 341 /* WFDMA CSR */ 342 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 343 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 344 345 #define MT_INT_SOURCE_CSR MT_WFDMA_EXT_CSR(0x10) 346 #define MT_INT_MASK_CSR MT_WFDMA_EXT_CSR(0x14) 347 #define MT_INT_RX_DONE_DATA0 BIT(16) 348 #define MT_INT_RX_DONE_DATA1 BIT(17) 349 #define MT_INT_RX_DONE_WM BIT(0) 350 #define MT_INT_RX_DONE_WA BIT(1) 351 #define MT_INT_RX_DONE_WA_EXT BIT(2) 352 #define MT_INT_RX_DONE_ALL (GENMASK(2, 0) | GENMASK(17, 16)) 353 #define MT_INT_TX_DONE_MCU_WA BIT(15) 354 #define MT_INT_TX_DONE_FWDL BIT(26) 355 #define MT_INT_TX_DONE_MCU_WM BIT(27) 356 #define MT_INT_TX_DONE_BAND0 BIT(30) 357 #define MT_INT_TX_DONE_BAND1 BIT(31) 358 359 #define MT_INT_BAND1_MASK (MT_INT_RX_DONE_WA_EXT | \ 360 MT_INT_TX_DONE_BAND1) 361 362 #define MT_INT_MCU_CMD BIT(29) 363 364 #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WA | \ 365 MT_INT_TX_DONE_MCU_WM | \ 366 MT_INT_TX_DONE_FWDL) 367 368 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 369 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 370 371 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 372 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 373 374 #define MT_INT1_SOURCE_CSR MT_WFDMA_EXT_CSR(0x88) 375 #define MT_INT1_MASK_CSR MT_WFDMA_EXT_CSR(0x8c) 376 377 #define MT_PCIE_RECOG_ID MT_WFDMA_EXT_CSR(0x90) 378 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 379 #define MT_PCIE_RECOG_ID_SEM BIT(31) 380 381 /* WFDMA0 PCIE1 */ 382 #define MT_WFDMA0_PCIE1_BASE 0xd8000 383 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 384 385 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 386 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 387 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 388 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 389 390 /* WFDMA1 PCIE1 */ 391 #define MT_WFDMA1_PCIE1_BASE 0xd9000 392 #define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 393 394 #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c) 395 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 396 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 397 #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 398 399 #define MT_INFRA_CFG_BASE 0xf1000 400 #define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs)) 401 402 #define MT_HIF_REMAP_L1 MT_INFRA(0x1ac) 403 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 404 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 405 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 406 #define MT_HIF_REMAP_BASE_L1 0xe0000 407 408 #define MT_HIF_REMAP_L2 MT_INFRA(0x1b0) 409 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 410 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 411 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 412 #define MT_HIF_REMAP_BASE_L2 0x00000 413 414 #define MT_SWDEF_BASE 0x41f200 415 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 416 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 417 #define MT_SWDEF_NORMAL_MODE 0 418 #define MT_SWDEF_ICAP_MODE 1 419 #define MT_SWDEF_SPECTRUM_MODE 2 420 421 #define MT_TOP_BASE 0x18060000 422 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 423 424 #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10) 425 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 426 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 427 428 #define MT_TOP_MISC MT_TOP(0xf0) 429 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 430 431 #define MT_HW_BOUND 0x70010020 432 #define MT_HW_CHIPID 0x70010200 433 #define MT_HW_REV 0x70010204 434 435 #define MT_PCIE1_MAC_BASE 0x74020000 436 #define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs)) 437 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188) 438 439 #define MT_PCIE_MAC_BASE 0x74030000 440 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 441 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 442 443 #define MT_WF_IRPI_BASE 0x83006000 444 #define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + ((ofs) << 16)) 445 446 /* PHY: band 0(0x83080000), band 1(0x83090000) */ 447 #define MT_WF_PHY_BASE 0x83080000 448 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 449 450 #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16)) 451 #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0) 452 #define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 453 454 #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16)) 455 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 456 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) 457 458 #endif 459