1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_REGS_H 5 #define __MT7915_REGS_H 6 7 struct __map { 8 u32 phys; 9 u32 maps; 10 u32 size; 11 }; 12 13 /* used to differentiate between generations */ 14 struct mt7915_reg_desc { 15 const u32 *reg_rev; 16 const u32 *offs_rev; 17 const struct __map *map; 18 u32 map_size; 19 }; 20 21 enum reg_rev { 22 INT_SOURCE_CSR, 23 INT_MASK_CSR, 24 INT1_SOURCE_CSR, 25 INT1_MASK_CSR, 26 INT_MCU_CMD_SOURCE, 27 INT_MCU_CMD_EVENT, 28 __MT_REG_MAX, 29 }; 30 31 enum offs_rev { 32 TMAC_CDTR, 33 TMAC_ODTR, 34 TMAC_ATCR, 35 TMAC_TRCR0, 36 TMAC_ICR0, 37 TMAC_ICR1, 38 TMAC_CTCR0, 39 TMAC_TFCR0, 40 MDP_BNRCFR0, 41 MDP_BNRCFR1, 42 ARB_DRNGR0, 43 ARB_SCR, 44 RMAC_MIB_AIRTIME14, 45 AGG_AWSCR0, 46 AGG_PCR0, 47 AGG_ACR0, 48 AGG_MRCR, 49 AGG_ATCR1, 50 AGG_ATCR3, 51 LPON_UTTR0, 52 LPON_UTTR1, 53 LPON_FRCR, 54 MIB_SDR3, 55 MIB_SDR4, 56 MIB_SDR5, 57 MIB_SDR7, 58 MIB_SDR8, 59 MIB_SDR9, 60 MIB_SDR10, 61 MIB_SDR11, 62 MIB_SDR12, 63 MIB_SDR13, 64 MIB_SDR14, 65 MIB_SDR15, 66 MIB_SDR16, 67 MIB_SDR17, 68 MIB_SDR18, 69 MIB_SDR19, 70 MIB_SDR20, 71 MIB_SDR21, 72 MIB_SDR22, 73 MIB_SDR23, 74 MIB_SDR24, 75 MIB_SDR25, 76 MIB_SDR27, 77 MIB_SDR28, 78 MIB_SDR29, 79 MIB_SDRVEC, 80 MIB_SDR31, 81 MIB_SDR32, 82 MIB_SDRMUBF, 83 MIB_DR8, 84 MIB_DR9, 85 MIB_DR11, 86 MIB_MB_SDR0, 87 MIB_MB_SDR1, 88 TX_AGG_CNT, 89 TX_AGG_CNT2, 90 MIB_ARNG, 91 WTBLON_TOP_WDUCR, 92 WTBL_UPDATE, 93 PLE_FL_Q_EMPTY, 94 PLE_FL_Q_CTRL, 95 PLE_AC_QEMPTY, 96 PLE_FREEPG_CNT, 97 PLE_FREEPG_HEAD_TAIL, 98 PLE_PG_HIF_GROUP, 99 PLE_HIF_PG_INFO, 100 AC_OFFSET, 101 __MT_OFFS_MAX, 102 }; 103 104 #define __REG(id) (dev->reg.reg_rev[(id)]) 105 #define __OFFS(id) (dev->reg.offs_rev[(id)]) 106 107 /* MCU WFDMA0 */ 108 #define MT_MCU_WFDMA0_BASE 0x2000 109 #define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs)) 110 111 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120) 112 113 /* MCU WFDMA1 */ 114 #define MT_MCU_WFDMA1_BASE 0x3000 115 #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 116 117 #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT) 118 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 119 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 120 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 121 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 122 123 /* PLE */ 124 #define MT_PLE_BASE 0x820c0000 125 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 126 127 #define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY)) 128 #define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL)) 129 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8) 130 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc) 131 132 #define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT)) 133 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL)) 134 #define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP)) 135 #define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO)) 136 137 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \ 138 __OFFS(AC_OFFSET) * \ 139 (ac) + ((n) << 2)) 140 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 141 142 #define MT_PSE_BASE 0x820c8000 143 #define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) 144 145 /* WF MDP TOP */ 146 #define MT_MDP_BASE 0x820cd000 147 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 148 149 #define MT_MDP_DCR0 MT_MDP(0x000) 150 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 151 152 #define MT_MDP_DCR1 MT_MDP(0x004) 153 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 154 155 #define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \ 156 ((_band) << 8)) 157 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 158 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 159 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 160 161 #define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \ 162 ((_band) << 8)) 163 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 164 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 165 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 166 #define MT_MDP_TO_HIF 0 167 #define MT_MDP_TO_WM 1 168 169 /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ 170 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 171 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 172 173 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 174 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 175 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 176 177 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR)) 178 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR)) 179 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 180 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 181 182 #define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR)) 183 #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0) 184 185 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0)) 186 #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0) 187 #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16) 188 189 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0)) 190 #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 191 #define MT_IFS_RIFS GENMASK(14, 10) 192 #define MT_IFS_SIFS GENMASK(22, 16) 193 #define MT_IFS_SLOT GENMASK(30, 24) 194 195 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1)) 196 #define MT_IFS_EIFS_CCK GENMASK(8, 0) 197 198 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0)) 199 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 200 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 201 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 202 203 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0)) 204 205 /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */ 206 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 207 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 208 209 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 210 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 211 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 212 213 /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */ 214 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 215 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 216 217 #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040) 218 #define MT_ETBF_TX_FB_CPL GENMASK(31, 16) 219 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0) 220 221 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x068) 222 #define MT_ETBF_RX_FB_BW GENMASK(7, 6) 223 #define MT_ETBF_RX_FB_NC GENMASK(5, 3) 224 #define MT_ETBF_RX_FB_NR GENMASK(2, 0) 225 226 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0) 227 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 228 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 229 230 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8) 231 #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 232 #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 233 #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 234 #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 235 236 /* LPON: band 0(0x820eb000), band 1(0x820fb000) */ 237 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 238 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 239 240 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0)) 241 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1)) 242 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR)) 243 244 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 245 (((n) * 4) << 1)) 246 #define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 247 (((n) * 4) << 4)) 248 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 249 #define MT_LPON_TCR_SW_WRITE BIT(0) 250 #define MT_LPON_TCR_SW_ADJUST BIT(1) 251 #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 252 253 /* MIB: band 0(0x820ed000), band 1(0x820fd000) */ 254 /* These counters are (mostly?) clear-on-read. So, some should not 255 * be read at all in case firmware is already reading them. These 256 * are commented with 'DNR' below. The DNR stats will be read by querying 257 * the firmware API for the appropriate message. For counters the driver 258 * does read, the driver should accumulate the counters. 259 */ 260 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 261 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 262 263 #define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010) 264 #define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0) 265 266 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3)) 267 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 268 #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16) 269 270 #define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4)) 271 #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0) 272 273 /* rx mpdu counter, full 32 bits */ 274 #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5)) 275 276 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 277 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 278 279 #define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7)) 280 #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0) 281 282 #define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8)) 283 #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0) 284 285 /* aka CCA_NAV_TX_TIME */ 286 #define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9)) 287 #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0) 288 289 #define MT_MIB_SDR10_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10)) 290 #define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0) 291 #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0) 292 293 #define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11)) 294 #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0) 295 296 /* tx ampdu cnt, full 32 bits */ 297 #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12)) 298 299 #define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13)) 300 #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0) 301 302 /* counts all mpdus in ampdu, regardless of success */ 303 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14)) 304 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0) 305 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0) 306 307 /* counts all successfully tx'd mpdus in ampdu */ 308 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15)) 309 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0) 310 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0) 311 312 /* in units of 'us' */ 313 #define MT_MIB_SDR16_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16)) 314 #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 315 316 #define MT_MIB_SDR17_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17)) 317 #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 318 319 #define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18)) 320 #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0) 321 322 /* units are us */ 323 #define MT_MIB_SDR19_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19)) 324 #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0) 325 326 #define MT_MIB_SDR20_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20)) 327 #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0) 328 329 #define MT_MIB_SDR21_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21)) 330 #define MT_MIB_SDR20_GREEN_MDRDY_TIME_MASK GENMASK(23, 0) 331 332 /* rx ampdu count, 32-bit */ 333 #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22)) 334 335 /* rx ampdu bytes count, 32-bit */ 336 #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23)) 337 338 /* rx ampdu valid subframe count */ 339 #define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24)) 340 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0) 341 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0) 342 343 /* rx ampdu valid subframe bytes count, 32bits */ 344 #define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25)) 345 346 /* remaining windows protected stats */ 347 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27)) 348 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0) 349 350 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28)) 351 #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0) 352 353 #define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29)) 354 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0) 355 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0) 356 357 #define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC)) 358 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0) 359 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16) 360 361 /* rx blockack count, 32 bits */ 362 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31)) 363 364 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32)) 365 #define MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK GENMASK(15, 0) 366 367 #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088) 368 #define MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK GENMASK(15, 0) 369 #define MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK_MT7916 GENMASK(31, 16) 370 371 #define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF)) 372 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 373 374 /* 36, 37 both DNR */ 375 376 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8)) 377 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9)) 378 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11)) 379 380 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n)) 381 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 382 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 383 384 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n)) 385 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 386 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 387 388 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n)) 389 #define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n)) 390 391 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \ 392 ((n) << 2)) 393 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \ 394 ((n) << 2)) 395 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \ 396 ((n) << 2)) 397 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 398 399 /* WTBLON TOP */ 400 #define MT_WTBLON_TOP_BASE 0x820d4000 401 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 402 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR)) 403 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 404 405 #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 406 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 407 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 408 #define MT_WTBL_UPDATE_BUSY BIT(31) 409 410 /* WTBL */ 411 #define MT_WTBL_BASE 0x820d8000 412 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 413 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 414 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 415 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 416 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 417 418 /* AGG: band 0(0x820e2000), band 1(0x820f2000) */ 419 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 420 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 421 422 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \ 423 (_n) * 4)) 424 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \ 425 (_n) * 4)) 426 #define MT_AGG_PCR0_MM_PROT BIT(0) 427 #define MT_AGG_PCR0_GF_PROT BIT(1) 428 #define MT_AGG_PCR0_BW20_PROT BIT(2) 429 #define MT_AGG_PCR0_BW40_PROT BIT(4) 430 #define MT_AGG_PCR0_BW80_PROT BIT(6) 431 #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 432 #define MT_AGG_PCR0_VHT_PROT BIT(13) 433 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 434 435 #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 436 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 437 438 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0)) 439 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 440 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 441 442 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR)) 443 #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 444 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 445 #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 446 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 447 448 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1)) 449 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3)) 450 451 /* ARB: band 0(0x820e3000), band 1(0x820f3000) */ 452 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 453 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 454 455 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR)) 456 #define MT_ARB_SCR_TX_DISABLE BIT(8) 457 #define MT_ARB_SCR_RX_DISABLE BIT(9) 458 459 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \ 460 (_n) * 4)) 461 462 /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */ 463 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 464 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 465 466 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 467 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 468 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 469 #define MT_WF_RFCR_DROP_VERSION BIT(3) 470 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 471 #define MT_WF_RFCR_DROP_MCAST BIT(5) 472 #define MT_WF_RFCR_DROP_BCAST BIT(6) 473 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 474 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 475 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 476 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 477 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 478 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 479 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 480 #define MT_WF_RFCR_DROP_CTS BIT(14) 481 #define MT_WF_RFCR_DROP_RTS BIT(15) 482 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 483 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 484 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 485 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 486 #define MT_WF_RFCR_DROP_NDPA BIT(20) 487 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 488 489 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 490 #define MT_WF_RFCR1_DROP_ACK BIT(4) 491 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 492 #define MT_WF_RFCR1_DROP_BA BIT(6) 493 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 494 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 495 496 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 497 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 498 499 /* WFDMA0 */ 500 #define MT_WFDMA0_BASE 0xd4000 501 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 502 503 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 504 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 505 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 506 507 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 508 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 509 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 510 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 511 512 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 513 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 514 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 515 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 516 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 517 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 518 519 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 520 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 521 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 522 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 523 524 /* WFDMA1 */ 525 #define MT_WFDMA1_BASE 0xd5000 526 #define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs)) 527 528 #define MT_WFDMA1_RST MT_WFDMA1(0x100) 529 #define MT_WFDMA1_RST_LOGIC_RST BIT(4) 530 #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5) 531 532 #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c) 533 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0) 534 #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1) 535 #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2) 536 537 #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208) 538 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0) 539 #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2) 540 #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28) 541 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27) 542 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 543 544 #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c) 545 #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0) 546 547 /* WFDMA CSR */ 548 #define MT_WFDMA_EXT_CSR_BASE 0xd7000 549 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 550 551 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 552 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 553 554 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) 555 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 556 557 #define MT_PCIE_RECOG_ID 0xd7090 558 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 559 #define MT_PCIE_RECOG_ID_SEM BIT(31) 560 561 /* WFDMA0 PCIE1 */ 562 #define MT_WFDMA0_PCIE1_BASE 0xd8000 563 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 564 565 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 566 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 567 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 568 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 569 570 /* WFDMA1 PCIE1 */ 571 #define MT_WFDMA1_PCIE1_BASE 0xd9000 572 #define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs)) 573 574 #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c) 575 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 576 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 577 #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 578 579 /* WFDMA COMMON */ 580 #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 581 #define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX) 582 583 #define MT_Q_ID(q) (dev->q_id[(q)]) 584 #define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \ 585 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 586 587 #define MT_MCUQ_ID(q) MT_Q_ID(q) 588 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 589 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 590 591 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 592 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 593 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 594 595 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 596 MT_MCUQ_ID(q)* 0x4) 597 #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 598 MT_RXQ_ID(q)* 0x4) 599 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 600 MT_TXQ_ID(q)* 0x4) 601 602 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) 603 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR) 604 605 #define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR) 606 #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR) 607 608 #define MT_INT_RX_DONE_BAND0 BIT(16) 609 #define MT_INT_RX_DONE_BAND1 BIT(17) 610 #define MT_INT_RX_DONE_WM BIT(0) 611 #define MT_INT_RX_DONE_WA BIT(1) 612 #define MT_INT_RX_DONE_WA_MAIN BIT(1) 613 #define MT_INT_RX_DONE_WA_EXT BIT(2) 614 #define MT_INT_MCU_CMD BIT(29) 615 #define MT_INT_RX_DONE_BAND0_MT7916 BIT(22) 616 #define MT_INT_RX_DONE_BAND1_MT7916 BIT(23) 617 #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2) 618 #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3) 619 620 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 621 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 622 623 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 624 MT_INT_RX(MT_RXQ_MCU_WA)) 625 626 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 627 MT_INT_RX(MT_RXQ_MAIN_WA)) 628 629 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_EXT) | \ 630 MT_INT_RX(MT_RXQ_EXT_WA) | \ 631 MT_INT_RX(MT_RXQ_MAIN_WA)) 632 633 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 634 MT_INT_BAND0_RX_DONE | \ 635 MT_INT_BAND1_RX_DONE) 636 637 #define MT_INT_TX_DONE_FWDL BIT(26) 638 #define MT_INT_TX_DONE_MCU_WM BIT(27) 639 #define MT_INT_TX_DONE_MCU_WA BIT(15) 640 #define MT_INT_TX_DONE_BAND0 BIT(30) 641 #define MT_INT_TX_DONE_BAND1 BIT(31) 642 #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25) 643 644 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 645 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 646 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 647 648 #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE) 649 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 650 #define MT_MCU_CMD_STOP_DMA BIT(2) 651 #define MT_MCU_CMD_RESET_DONE BIT(3) 652 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 653 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 654 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 655 656 /* TOP RGU */ 657 #define MT_TOP_RGU_BASE 0x18000000 658 #define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0)) 659 #define MT_TOP_PWR_KEY (0x5746 << 16) 660 #define MT_TOP_PWR_SW_RST BIT(0) 661 #define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2) 662 #define MT_TOP_PWR_HW_CTRL BIT(4) 663 #define MT_TOP_PWR_PWR_ON BIT(7) 664 665 /* l1/l2 remap */ 666 #define MT_HIF_REMAP_L1 0xf11ac 667 #define MT_HIF_REMAP_L1_MT7916 0xfe260 668 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 669 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 670 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 671 #define MT_HIF_REMAP_BASE_L1 0xe0000 672 673 #define MT_HIF_REMAP_L2 0xf11b0 674 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 675 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 676 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 677 #define MT_HIF_REMAP_L2_MT7916 0x1b8 678 #define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16) 679 #define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0) 680 #define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16) 681 #define MT_HIF_REMAP_BASE_L2_MT7916 0x40000 682 683 #define MT_INFRA_BASE 0x18000000 684 #define MT_WFSYS0_PHY_START 0x18400000 685 #define MT_WFSYS1_PHY_START 0x18800000 686 #define MT_WFSYS1_PHY_END 0x18bfffff 687 #define MT_CBTOP1_PHY_START 0x70000000 688 #define MT_CBTOP1_PHY_END 0x7fffffff 689 #define MT_CBTOP2_PHY_START 0xf0000000 690 #define MT_CBTOP2_PHY_END 0xffffffff 691 692 /* FW MODE SYNC */ 693 #define MT_SWDEF_MODE 0x41f23c 694 #define MT_SWDEF_MODE_MT7916 0x41143c 695 #define MT_SWDEF_NORMAL_MODE 0 696 #define MT_SWDEF_ICAP_MODE 1 697 #define MT_SWDEF_SPECTRUM_MODE 2 698 699 #define MT_DIC_CMD_REG_BASE 0x41f000 700 #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) 701 #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) 702 703 #define MT_CPU_UTIL_BASE 0x41f030 704 #define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs)) 705 #define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00) 706 #define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04) 707 #define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08) 708 #define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c) 709 #define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c) 710 711 /* LED */ 712 #define MT_LED_TOP_BASE 0x18013000 713 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 714 715 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 716 #define MT_LED_CTRL_KICK BIT(7) 717 #define MT_LED_CTRL_BLINK_MODE BIT(2) 718 #define MT_LED_CTRL_POLARITY BIT(1) 719 720 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 721 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 722 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 723 724 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 725 726 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 727 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ 728 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) 729 730 /* MT TOP */ 731 #define MT_TOP_BASE 0x18060000 732 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 733 734 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 735 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 736 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 737 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 738 739 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 740 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 741 742 #define MT_TOP_MISC MT_TOP(0xf0) 743 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 744 745 #define MT_HW_BOUND 0x70010020 746 #define MT_HW_REV 0x70010204 747 #define MT_WF_SUBSYS_RST 0x70002600 748 749 /* PCIE MAC */ 750 #define MT_PCIE_MAC_BASE 0x74030000 751 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 752 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 753 754 #define MT_PCIE1_MAC_INT_ENABLE 0x74020188 755 #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188 756 757 /* PP TOP */ 758 #define MT_WF_PP_TOP_BASE 0x820cc000 759 #define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs)) 760 761 #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8) 762 #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6) 763 764 #define MT_WF_IRPI_BASE 0x83006000 765 #define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + ((ofs) << 16)) 766 767 /* PHY: band 0(0x83080000), band 1(0x83090000) */ 768 #define MT_WF_PHY_BASE 0x83080000 769 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 770 771 #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16)) 772 #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0) 773 #define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 774 775 #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16)) 776 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 777 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) 778 779 #define MT_MCU_WM_CIRQ_BASE 0x89010000 780 #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) 781 #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) 782 #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0) 783 784 #endif 785