1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/pci.h>
8 
9 #include "mt7915.h"
10 #include "mac.h"
11 #include "../trace.h"
12 #include "../dma.h"
13 
14 static bool wed_enable;
15 module_param(wed_enable, bool, 0644);
16 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support");
17 
18 static const u32 mt7915_reg[] = {
19 	[INT_SOURCE_CSR]		= 0xd7010,
20 	[INT_MASK_CSR]			= 0xd7014,
21 	[INT1_SOURCE_CSR]		= 0xd7088,
22 	[INT1_MASK_CSR]			= 0xd708c,
23 	[INT_MCU_CMD_SOURCE]		= 0xd51f0,
24 	[INT_MCU_CMD_EVENT]		= 0x3108,
25 	[WFDMA0_ADDR]			= 0xd4000,
26 	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
27 	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
28 	[CBTOP1_PHY_END]		= 0x77ffffff,
29 	[INFRA_MCU_ADDR_END]		= 0x7c3fffff,
30 	[FW_ASSERT_STAT_ADDR]		= 0x219848,
31 	[FW_EXCEPT_TYPE_ADDR]		= 0x21987c,
32 	[FW_EXCEPT_COUNT_ADDR]		= 0x219848,
33 	[FW_CIRQ_COUNT_ADDR]		= 0x216f94,
34 	[FW_CIRQ_IDX_ADDR]		= 0x216ef8,
35 	[FW_CIRQ_LISR_ADDR]		= 0x2170ac,
36 	[FW_TASK_ID_ADDR]		= 0x216f90,
37 	[FW_TASK_IDX_ADDR]		= 0x216f9c,
38 	[FW_TASK_QID1_ADDR]		= 0x219680,
39 	[FW_TASK_QID2_ADDR]		= 0x219760,
40 	[FW_TASK_START_ADDR]		= 0x219558,
41 	[FW_TASK_END_ADDR]		= 0x219554,
42 	[FW_TASK_SIZE_ADDR]		= 0x219560,
43 	[FW_LAST_MSG_ID_ADDR]		= 0x216f70,
44 	[FW_EINT_INFO_ADDR]		= 0x219818,
45 	[FW_SCHED_INFO_ADDR]		= 0x219828,
46 	[SWDEF_BASE_ADDR]		= 0x41f200,
47 	[TXQ_WED_RING_BASE]		= 0xd7300,
48 	[RXQ_WED_RING_BASE]		= 0xd7410,
49 	[RXQ_WED_DATA_RING_BASE]	= 0xd4500,
50 };
51 
52 static const u32 mt7916_reg[] = {
53 	[INT_SOURCE_CSR]		= 0xd4200,
54 	[INT_MASK_CSR]			= 0xd4204,
55 	[INT1_SOURCE_CSR]		= 0xd8200,
56 	[INT1_MASK_CSR]			= 0xd8204,
57 	[INT_MCU_CMD_SOURCE]		= 0xd41f0,
58 	[INT_MCU_CMD_EVENT]		= 0x2108,
59 	[WFDMA0_ADDR]			= 0xd4000,
60 	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
61 	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
62 	[CBTOP1_PHY_END]		= 0x7fffffff,
63 	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
64 	[FW_ASSERT_STAT_ADDR]		= 0x02204c14,
65 	[FW_EXCEPT_TYPE_ADDR]		= 0x022051a4,
66 	[FW_EXCEPT_COUNT_ADDR]		= 0x022050bc,
67 	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
68 	[FW_CIRQ_IDX_ADDR]		= 0x02204f84,
69 	[FW_CIRQ_LISR_ADDR]		= 0x022050d0,
70 	[FW_TASK_ID_ADDR]		= 0x0220406c,
71 	[FW_TASK_IDX_ADDR]		= 0x0220500c,
72 	[FW_TASK_QID1_ADDR]		= 0x022028c8,
73 	[FW_TASK_QID2_ADDR]		= 0x02202a38,
74 	[FW_TASK_START_ADDR]		= 0x0220286c,
75 	[FW_TASK_END_ADDR]		= 0x02202870,
76 	[FW_TASK_SIZE_ADDR]		= 0x02202878,
77 	[FW_LAST_MSG_ID_ADDR]		= 0x02204fe8,
78 	[FW_EINT_INFO_ADDR]		= 0x0220525c,
79 	[FW_SCHED_INFO_ADDR]		= 0x0220516c,
80 	[SWDEF_BASE_ADDR]		= 0x411400,
81 	[TXQ_WED_RING_BASE]		= 0xd7300,
82 	[RXQ_WED_RING_BASE]		= 0xd7410,
83 	[RXQ_WED_DATA_RING_BASE]	= 0xd4540,
84 };
85 
86 static const u32 mt7986_reg[] = {
87 	[INT_SOURCE_CSR]		= 0x24200,
88 	[INT_MASK_CSR]			= 0x24204,
89 	[INT1_SOURCE_CSR]		= 0x28200,
90 	[INT1_MASK_CSR]			= 0x28204,
91 	[INT_MCU_CMD_SOURCE]		= 0x241f0,
92 	[INT_MCU_CMD_EVENT]		= 0x54000108,
93 	[WFDMA0_ADDR]			= 0x24000,
94 	[WFDMA0_PCIE1_ADDR]		= 0x28000,
95 	[WFDMA_EXT_CSR_ADDR]		= 0x27000,
96 	[CBTOP1_PHY_END]		= 0x7fffffff,
97 	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
98 	[FW_ASSERT_STAT_ADDR]		= 0x02204b54,
99 	[FW_EXCEPT_TYPE_ADDR]		= 0x022050dc,
100 	[FW_EXCEPT_COUNT_ADDR]		= 0x02204ffc,
101 	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
102 	[FW_CIRQ_IDX_ADDR]		= 0x02204ec4,
103 	[FW_CIRQ_LISR_ADDR]		= 0x02205010,
104 	[FW_TASK_ID_ADDR]		= 0x02204fac,
105 	[FW_TASK_IDX_ADDR]		= 0x02204f4c,
106 	[FW_TASK_QID1_ADDR]		= 0x02202814,
107 	[FW_TASK_QID2_ADDR]		= 0x02202984,
108 	[FW_TASK_START_ADDR]		= 0x022027b8,
109 	[FW_TASK_END_ADDR]		= 0x022027bc,
110 	[FW_TASK_SIZE_ADDR]		= 0x022027c4,
111 	[FW_LAST_MSG_ID_ADDR]		= 0x02204f28,
112 	[FW_EINT_INFO_ADDR]		= 0x02205194,
113 	[FW_SCHED_INFO_ADDR]		= 0x022051a4,
114 	[SWDEF_BASE_ADDR]		= 0x411400,
115 	[TXQ_WED_RING_BASE]		= 0x24420,
116 	[RXQ_WED_RING_BASE]		= 0x24520,
117 	[RXQ_WED_DATA_RING_BASE]	= 0x24540,
118 };
119 
120 static const u32 mt7915_offs[] = {
121 	[TMAC_CDTR]		= 0x090,
122 	[TMAC_ODTR]		= 0x094,
123 	[TMAC_ATCR]		= 0x098,
124 	[TMAC_TRCR0]		= 0x09c,
125 	[TMAC_ICR0]		= 0x0a4,
126 	[TMAC_ICR1]		= 0x0b4,
127 	[TMAC_CTCR0]		= 0x0f4,
128 	[TMAC_TFCR0]		= 0x1e0,
129 	[MDP_BNRCFR0]		= 0x070,
130 	[MDP_BNRCFR1]		= 0x074,
131 	[ARB_DRNGR0]		= 0x194,
132 	[ARB_SCR]		= 0x080,
133 	[RMAC_MIB_AIRTIME14]	= 0x3b8,
134 	[AGG_AWSCR0]		= 0x05c,
135 	[AGG_PCR0]		= 0x06c,
136 	[AGG_ACR0]		= 0x084,
137 	[AGG_ACR4]		= 0x08c,
138 	[AGG_MRCR]		= 0x098,
139 	[AGG_ATCR1]		= 0x0f0,
140 	[AGG_ATCR3]		= 0x0f4,
141 	[LPON_UTTR0]		= 0x080,
142 	[LPON_UTTR1]		= 0x084,
143 	[LPON_FRCR]		= 0x314,
144 	[MIB_SDR3]		= 0x014,
145 	[MIB_SDR4]		= 0x018,
146 	[MIB_SDR5]		= 0x01c,
147 	[MIB_SDR7]		= 0x024,
148 	[MIB_SDR8]		= 0x028,
149 	[MIB_SDR9]		= 0x02c,
150 	[MIB_SDR10]		= 0x030,
151 	[MIB_SDR11]		= 0x034,
152 	[MIB_SDR12]		= 0x038,
153 	[MIB_SDR13]		= 0x03c,
154 	[MIB_SDR14]		= 0x040,
155 	[MIB_SDR15]		= 0x044,
156 	[MIB_SDR16]		= 0x048,
157 	[MIB_SDR17]		= 0x04c,
158 	[MIB_SDR18]		= 0x050,
159 	[MIB_SDR19]		= 0x054,
160 	[MIB_SDR20]		= 0x058,
161 	[MIB_SDR21]		= 0x05c,
162 	[MIB_SDR22]		= 0x060,
163 	[MIB_SDR23]		= 0x064,
164 	[MIB_SDR24]		= 0x068,
165 	[MIB_SDR25]		= 0x06c,
166 	[MIB_SDR27]		= 0x074,
167 	[MIB_SDR28]		= 0x078,
168 	[MIB_SDR29]		= 0x07c,
169 	[MIB_SDRVEC]		= 0x080,
170 	[MIB_SDR31]		= 0x084,
171 	[MIB_SDR32]		= 0x088,
172 	[MIB_SDRMUBF]		= 0x090,
173 	[MIB_DR8]		= 0x0c0,
174 	[MIB_DR9]		= 0x0c4,
175 	[MIB_DR11]		= 0x0cc,
176 	[MIB_MB_SDR0]		= 0x100,
177 	[MIB_MB_SDR1]		= 0x104,
178 	[TX_AGG_CNT]		= 0x0a8,
179 	[TX_AGG_CNT2]		= 0x164,
180 	[MIB_ARNG]		= 0x4b8,
181 	[WTBLON_TOP_WDUCR]	= 0x0,
182 	[WTBL_UPDATE]		= 0x030,
183 	[PLE_FL_Q_EMPTY]	= 0x0b0,
184 	[PLE_FL_Q_CTRL]		= 0x1b0,
185 	[PLE_AC_QEMPTY]		= 0x500,
186 	[PLE_FREEPG_CNT]	= 0x100,
187 	[PLE_FREEPG_HEAD_TAIL]	= 0x104,
188 	[PLE_PG_HIF_GROUP]	= 0x110,
189 	[PLE_HIF_PG_INFO]	= 0x114,
190 	[AC_OFFSET]		= 0x040,
191 	[ETBF_PAR_RPT0]		= 0x068,
192 };
193 
194 static const u32 mt7916_offs[] = {
195 	[TMAC_CDTR]		= 0x0c8,
196 	[TMAC_ODTR]		= 0x0cc,
197 	[TMAC_ATCR]		= 0x00c,
198 	[TMAC_TRCR0]		= 0x010,
199 	[TMAC_ICR0]		= 0x014,
200 	[TMAC_ICR1]		= 0x018,
201 	[TMAC_CTCR0]		= 0x114,
202 	[TMAC_TFCR0]		= 0x0e4,
203 	[MDP_BNRCFR0]		= 0x090,
204 	[MDP_BNRCFR1]		= 0x094,
205 	[ARB_DRNGR0]		= 0x1e0,
206 	[ARB_SCR]		= 0x000,
207 	[RMAC_MIB_AIRTIME14]	= 0x0398,
208 	[AGG_AWSCR0]		= 0x030,
209 	[AGG_PCR0]		= 0x040,
210 	[AGG_ACR0]		= 0x054,
211 	[AGG_ACR4]		= 0x05c,
212 	[AGG_MRCR]		= 0x068,
213 	[AGG_ATCR1]		= 0x1a8,
214 	[AGG_ATCR3]		= 0x080,
215 	[LPON_UTTR0]		= 0x360,
216 	[LPON_UTTR1]		= 0x364,
217 	[LPON_FRCR]		= 0x37c,
218 	[MIB_SDR3]		= 0x698,
219 	[MIB_SDR4]		= 0x788,
220 	[MIB_SDR5]		= 0x780,
221 	[MIB_SDR7]		= 0x5a8,
222 	[MIB_SDR8]		= 0x78c,
223 	[MIB_SDR9]		= 0x024,
224 	[MIB_SDR10]		= 0x76c,
225 	[MIB_SDR11]		= 0x790,
226 	[MIB_SDR12]		= 0x558,
227 	[MIB_SDR13]		= 0x560,
228 	[MIB_SDR14]		= 0x564,
229 	[MIB_SDR15]		= 0x568,
230 	[MIB_SDR16]		= 0x7fc,
231 	[MIB_SDR17]		= 0x800,
232 	[MIB_SDR18]		= 0x030,
233 	[MIB_SDR19]		= 0x5ac,
234 	[MIB_SDR20]		= 0x5b0,
235 	[MIB_SDR21]		= 0x5b4,
236 	[MIB_SDR22]		= 0x770,
237 	[MIB_SDR23]		= 0x774,
238 	[MIB_SDR24]		= 0x778,
239 	[MIB_SDR25]		= 0x77c,
240 	[MIB_SDR27]		= 0x080,
241 	[MIB_SDR28]		= 0x084,
242 	[MIB_SDR29]		= 0x650,
243 	[MIB_SDRVEC]		= 0x5a8,
244 	[MIB_SDR31]		= 0x55c,
245 	[MIB_SDR32]		= 0x7a8,
246 	[MIB_SDRMUBF]		= 0x7ac,
247 	[MIB_DR8]		= 0x56c,
248 	[MIB_DR9]		= 0x570,
249 	[MIB_DR11]		= 0x574,
250 	[MIB_MB_SDR0]		= 0x688,
251 	[MIB_MB_SDR1]		= 0x690,
252 	[TX_AGG_CNT]		= 0x7dc,
253 	[TX_AGG_CNT2]		= 0x7ec,
254 	[MIB_ARNG]		= 0x0b0,
255 	[WTBLON_TOP_WDUCR]	= 0x200,
256 	[WTBL_UPDATE]		= 0x230,
257 	[PLE_FL_Q_EMPTY]	= 0x360,
258 	[PLE_FL_Q_CTRL]		= 0x3e0,
259 	[PLE_AC_QEMPTY]		= 0x600,
260 	[PLE_FREEPG_CNT]	= 0x380,
261 	[PLE_FREEPG_HEAD_TAIL]	= 0x384,
262 	[PLE_PG_HIF_GROUP]	= 0x00c,
263 	[PLE_HIF_PG_INFO]	= 0x388,
264 	[AC_OFFSET]		= 0x080,
265 	[ETBF_PAR_RPT0]		= 0x100,
266 };
267 
268 static const struct mt76_connac_reg_map mt7915_reg_map[] = {
269 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
270 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
271 	{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
272 	{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
273 	{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
274 	{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
275 	{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
276 	{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
277 	{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
278 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
279 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
280 	{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
281 	{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
282 	{ 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
283 	{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
284 	{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
285 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
286 	{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
287 	{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
288 	{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
289 	{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
290 	{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
291 	{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
292 	{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
293 	{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
294 	{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
295 	{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
296 	{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
297 	{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
298 	{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
299 	{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
300 	{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
301 	{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
302 	{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
303 	{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
304 	{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
305 	{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
306 	{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
307 	{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
308 	{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
309 	{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
310 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
311 };
312 
313 static const struct mt76_connac_reg_map mt7916_reg_map[] = {
314 	{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
315 	{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
316 	{ 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
317 	{ 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
318 	{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
319 	{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
320 	{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
321 	{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
322 	{ 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
323 	{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
324 	{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
325 	{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
326 	{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
327 	{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
328 	{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
329 	{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
330 	{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
331 	{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
332 	{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
333 	{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
334 	{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
335 	{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
336 	{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
337 	{ 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
338 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
339 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
340 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
341 	{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
342 	{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
343 	{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
344 	{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
345 	{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
346 	{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
347 	{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
348 	{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
349 	{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
350 	{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
351 	{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
352 	{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
353 	{ 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
354 	{ 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
355 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
356 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
357 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
358 };
359 
360 static const struct mt76_connac_reg_map mt7986_reg_map[] = {
361 	{ 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
362 	{ 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
363 	{ 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
364 	{ 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
365 	{ 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
366 	{ 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
367 	{ 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
368 	{ 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
369 	{ 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
370 	{ 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
371 	{ 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
372 	{ 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
373 	{ 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
374 	{ 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
375 	{ 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
376 	{ 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
377 	{ 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
378 	{ 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
379 	{ 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
380 	{ 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
381 	{ 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
382 	{ 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
383 	{ 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
384 	{ 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
385 	{ 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
386 	{ 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
387 	{ 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
388 	{ 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
389 	{ 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
390 	{ 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
391 	{ 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
392 	{ 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
393 	{ 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
394 	{ 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
395 	{ 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
396 	{ 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
397 	{ 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
398 	{ 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
399 	{ 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
400 	{ 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
401 	{ 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
402 	{ 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
403 	{ 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
404 	{ 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
405 	{ 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
406 	{ 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
407 	{ 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
408 	{ 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
409 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
410 };
411 
412 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
413 {
414 	u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
415 	u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
416 	u32 l1_remap;
417 
418 	if (is_mt7986(&dev->mt76))
419 		return MT_CONN_INFRA_OFFSET(addr);
420 
421 	l1_remap = is_mt7915(&dev->mt76) ?
422 		   MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
423 
424 	dev->bus_ops->rmw(&dev->mt76, l1_remap,
425 			  MT_HIF_REMAP_L1_MASK,
426 			  FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
427 	/* use read to push write */
428 	dev->bus_ops->rr(&dev->mt76, l1_remap);
429 
430 	return MT_HIF_REMAP_BASE_L1 + offset;
431 }
432 
433 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
434 {
435 	u32 offset, base;
436 
437 	if (is_mt7915(&dev->mt76)) {
438 		offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
439 		base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
440 
441 		dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
442 				  MT_HIF_REMAP_L2_MASK,
443 				  FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
444 
445 		/* use read to push write */
446 		dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
447 	} else {
448 		u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0;
449 
450 		offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
451 		base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
452 
453 		dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
454 				  MT_HIF_REMAP_L2_MASK_MT7916,
455 				  FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
456 
457 		/* use read to push write */
458 		dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
459 
460 		offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
461 	}
462 
463 	return offset;
464 }
465 
466 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
467 {
468 	int i;
469 
470 	if (addr < 0x100000)
471 		return addr;
472 
473 	if (!dev->reg.map) {
474 		dev_err(dev->mt76.dev, "err: reg_map is null\n");
475 		return addr;
476 	}
477 
478 	for (i = 0; i < dev->reg.map_size; i++) {
479 		u32 ofs;
480 
481 		if (addr < dev->reg.map[i].phys)
482 			continue;
483 
484 		ofs = addr - dev->reg.map[i].phys;
485 		if (ofs > dev->reg.map[i].size)
486 			continue;
487 
488 		return dev->reg.map[i].maps + ofs;
489 	}
490 
491 	if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
492 	    (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
493 	    (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
494 		return mt7915_reg_map_l1(dev, addr);
495 
496 	if (dev_is_pci(dev->mt76.dev) &&
497 	    ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
498 	     (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END)))
499 		return mt7915_reg_map_l1(dev, addr);
500 
501 	/* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
502 	if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
503 		addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
504 		return mt7915_reg_map_l1(dev, addr);
505 	}
506 
507 	return mt7915_reg_map_l2(dev, addr);
508 }
509 
510 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,
511 			  size_t len)
512 {
513 	u32 addr = __mt7915_reg_addr(dev, offset);
514 
515 	memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
516 }
517 
518 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
519 {
520 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
521 	u32 addr = __mt7915_reg_addr(dev, offset);
522 
523 	return dev->bus_ops->rr(mdev, addr);
524 }
525 
526 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
527 {
528 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
529 	u32 addr = __mt7915_reg_addr(dev, offset);
530 
531 	dev->bus_ops->wr(mdev, addr, val);
532 }
533 
534 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
535 {
536 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
537 	u32 addr = __mt7915_reg_addr(dev, offset);
538 
539 	return dev->bus_ops->rmw(mdev, addr, mask, val);
540 }
541 
542 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
543 static int mt7915_mmio_wed_offload_enable(struct mtk_wed_device *wed)
544 {
545 	struct mt7915_dev *dev;
546 	struct mt7915_phy *phy;
547 	int ret;
548 
549 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
550 
551 	spin_lock_bh(&dev->mt76.token_lock);
552 	dev->mt76.token_size = wed->wlan.token_start;
553 	spin_unlock_bh(&dev->mt76.token_lock);
554 
555 	ret = wait_event_timeout(dev->mt76.tx_wait,
556 				 !dev->mt76.wed_token_count, HZ);
557 	if (!ret)
558 		return -EAGAIN;
559 
560 	phy = &dev->phy;
561 	mt76_set(dev, MT_AGG_ACR4(phy->mt76->band_idx), MT_AGG_ACR_PPDU_TXS2H);
562 
563 	phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL;
564 	if (phy)
565 		mt76_set(dev, MT_AGG_ACR4(phy->mt76->band_idx),
566 			 MT_AGG_ACR_PPDU_TXS2H);
567 
568 	return 0;
569 }
570 
571 static void mt7915_mmio_wed_offload_disable(struct mtk_wed_device *wed)
572 {
573 	struct mt7915_dev *dev;
574 	struct mt7915_phy *phy;
575 
576 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
577 
578 	spin_lock_bh(&dev->mt76.token_lock);
579 	dev->mt76.token_size = MT7915_TOKEN_SIZE;
580 	spin_unlock_bh(&dev->mt76.token_lock);
581 
582 	/* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
583 	 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
584 	 */
585 	phy = &dev->phy;
586 	mt76_clear(dev, MT_AGG_ACR4(phy->mt76->band_idx), MT_AGG_ACR_PPDU_TXS2H);
587 
588 	phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL;
589 	if (phy)
590 		mt76_clear(dev, MT_AGG_ACR4(phy->mt76->band_idx),
591 			   MT_AGG_ACR_PPDU_TXS2H);
592 }
593 
594 static void mt7915_mmio_wed_release_rx_buf(struct mtk_wed_device *wed)
595 {
596 	struct mt7915_dev *dev;
597 	struct page *page;
598 	int i;
599 
600 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
601 	for (i = 0; i < dev->mt76.rx_token_size; i++) {
602 		struct mt76_txwi_cache *t;
603 
604 		t = mt76_rx_token_release(&dev->mt76, i);
605 		if (!t || !t->ptr)
606 			continue;
607 
608 		dma_unmap_single(dev->mt76.dma_dev, t->dma_addr,
609 				 wed->wlan.rx_size, DMA_FROM_DEVICE);
610 		skb_free_frag(t->ptr);
611 		t->ptr = NULL;
612 
613 		mt76_put_rxwi(&dev->mt76, t);
614 	}
615 
616 	if (!wed->rx_buf_ring.rx_page.va)
617 		return;
618 
619 	page = virt_to_page(wed->rx_buf_ring.rx_page.va);
620 	__page_frag_cache_drain(page, wed->rx_buf_ring.rx_page.pagecnt_bias);
621 	memset(&wed->rx_buf_ring.rx_page, 0, sizeof(wed->rx_buf_ring.rx_page));
622 }
623 
624 static u32 mt7915_mmio_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
625 {
626 	struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
627 	struct mt7915_dev *dev;
628 	u32 length;
629 	int i;
630 
631 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
632 	length = SKB_DATA_ALIGN(NET_SKB_PAD + wed->wlan.rx_size +
633 				sizeof(struct skb_shared_info));
634 
635 	for (i = 0; i < size; i++) {
636 		struct mt76_txwi_cache *t = mt76_get_rxwi(&dev->mt76);
637 		dma_addr_t phy_addr;
638 		int token;
639 		void *ptr;
640 
641 		ptr = page_frag_alloc(&wed->rx_buf_ring.rx_page, length,
642 				      GFP_KERNEL);
643 		if (!ptr)
644 			goto unmap;
645 
646 		phy_addr = dma_map_single(dev->mt76.dma_dev, ptr,
647 					  wed->wlan.rx_size,
648 					  DMA_TO_DEVICE);
649 		if (unlikely(dma_mapping_error(dev->mt76.dev, phy_addr))) {
650 			skb_free_frag(ptr);
651 			goto unmap;
652 		}
653 
654 		desc->buf0 = cpu_to_le32(phy_addr);
655 		token = mt76_rx_token_consume(&dev->mt76, ptr, t, phy_addr);
656 		desc->token |= cpu_to_le32(FIELD_PREP(MT_DMA_CTL_TOKEN,
657 						      token));
658 		desc++;
659 	}
660 
661 	return 0;
662 
663 unmap:
664 	mt7915_mmio_wed_release_rx_buf(wed);
665 	return -ENOMEM;
666 }
667 
668 static void mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device *wed,
669 					    struct mtk_wed_wo_rx_stats *stats)
670 {
671 	int idx = le16_to_cpu(stats->wlan_idx);
672 	struct mt7915_dev *dev;
673 	struct mt76_wcid *wcid;
674 
675 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
676 
677 	if (idx >= mt7915_wtbl_size(dev))
678 		return;
679 
680 	rcu_read_lock();
681 
682 	wcid = rcu_dereference(dev->mt76.wcid[idx]);
683 	if (wcid) {
684 		wcid->stats.rx_bytes += le32_to_cpu(stats->rx_byte_cnt);
685 		wcid->stats.rx_packets += le32_to_cpu(stats->rx_pkt_cnt);
686 		wcid->stats.rx_errors += le32_to_cpu(stats->rx_err_cnt);
687 		wcid->stats.rx_drops += le32_to_cpu(stats->rx_drop_cnt);
688 	}
689 
690 	rcu_read_unlock();
691 }
692 #endif
693 
694 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
695 			 bool pci, int *irq)
696 {
697 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
698 	struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
699 	int ret;
700 
701 	if (!wed_enable)
702 		return 0;
703 
704 	if (pci) {
705 		struct pci_dev *pci_dev = pdev_ptr;
706 
707 		wed->wlan.pci_dev = pci_dev;
708 		wed->wlan.bus_type = MTK_WED_BUS_PCIE;
709 		wed->wlan.base = devm_ioremap(dev->mt76.dev,
710 					      pci_resource_start(pci_dev, 0),
711 					      pci_resource_len(pci_dev, 0));
712 		wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
713 		wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) +
714 				      MT_INT_WED_SOURCE_CSR;
715 		wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) +
716 				       MT_INT_WED_MASK_CSR;
717 		wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) +
718 				       MT_WFDMA_EXT_CSR_BASE;
719 		wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) +
720 				     MT_TXQ_WED_RING_BASE;
721 		wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +
722 					 MT_RXQ_WED_RING_BASE;
723 		wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
724 					 MT_WPDMA_GLO_CFG;
725 		wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
726 				     MT_RXQ_WED_DATA_RING_BASE;
727 	} else {
728 		struct platform_device *plat_dev = pdev_ptr;
729 		struct resource *res;
730 
731 		res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
732 		if (!res)
733 			return -ENOMEM;
734 
735 		wed->wlan.platform_dev = plat_dev;
736 		wed->wlan.bus_type = MTK_WED_BUS_AXI;
737 		wed->wlan.base = devm_ioremap(dev->mt76.dev, res->start,
738 					      resource_size(res));
739 		wed->wlan.phy_base = res->start;
740 		wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR;
741 		wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR;
742 		wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
743 		wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
744 		wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
745 		wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
746 	}
747 	wed->wlan.nbuf = 4096;
748 	wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;
749 	wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31;
750 	wed->wlan.txfree_tbit = is_mt7986(&dev->mt76) ? 2 : 1;
751 	wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
752 	wed->wlan.wcid_512 = !is_mt7915(&dev->mt76);
753 
754 	wed->wlan.rx_nbuf = 65536;
755 	wed->wlan.rx_npkt = MT7915_WED_RX_TOKEN_SIZE;
756 	wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE);
757 	if (is_mt7915(&dev->mt76)) {
758 		wed->wlan.rx_tbit[0] = 16;
759 		wed->wlan.rx_tbit[1] = 17;
760 	} else if (is_mt7986(&dev->mt76)) {
761 		wed->wlan.rx_tbit[0] = 22;
762 		wed->wlan.rx_tbit[1] = 23;
763 	} else {
764 		wed->wlan.rx_tbit[0] = 18;
765 		wed->wlan.rx_tbit[1] = 19;
766 	}
767 
768 	wed->wlan.init_buf = mt7915_wed_init_buf;
769 	wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable;
770 	wed->wlan.offload_disable = mt7915_mmio_wed_offload_disable;
771 	wed->wlan.init_rx_buf = mt7915_mmio_wed_init_rx_buf;
772 	wed->wlan.release_rx_buf = mt7915_mmio_wed_release_rx_buf;
773 	wed->wlan.update_wo_rx_stats = mt7915_mmio_wed_update_rx_stats;
774 
775 	dev->mt76.rx_token_size = wed->wlan.rx_npkt;
776 
777 	if (mtk_wed_device_attach(wed))
778 		return 0;
779 
780 	*irq = wed->irq;
781 	dev->mt76.dma_dev = wed->dev;
782 
783 	ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
784 	if (ret)
785 		return ret;
786 
787 	return 1;
788 #else
789 	return 0;
790 #endif
791 }
792 
793 static int mt7915_mmio_init(struct mt76_dev *mdev,
794 			    void __iomem *mem_base,
795 			    u32 device_id)
796 {
797 	struct mt76_bus_ops *bus_ops;
798 	struct mt7915_dev *dev;
799 
800 	dev = container_of(mdev, struct mt7915_dev, mt76);
801 	mt76_mmio_init(&dev->mt76, mem_base);
802 
803 	switch (device_id) {
804 	case 0x7915:
805 		dev->reg.reg_rev = mt7915_reg;
806 		dev->reg.offs_rev = mt7915_offs;
807 		dev->reg.map = mt7915_reg_map;
808 		dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
809 		break;
810 	case 0x7906:
811 		dev->reg.reg_rev = mt7916_reg;
812 		dev->reg.offs_rev = mt7916_offs;
813 		dev->reg.map = mt7916_reg_map;
814 		dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
815 		break;
816 	case 0x7986:
817 		dev->reg.reg_rev = mt7986_reg;
818 		dev->reg.offs_rev = mt7916_offs;
819 		dev->reg.map = mt7986_reg_map;
820 		dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
821 		break;
822 	default:
823 		return -EINVAL;
824 	}
825 
826 	dev->bus_ops = dev->mt76.bus;
827 	bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
828 			       GFP_KERNEL);
829 	if (!bus_ops)
830 		return -ENOMEM;
831 
832 	bus_ops->rr = mt7915_rr;
833 	bus_ops->wr = mt7915_wr;
834 	bus_ops->rmw = mt7915_rmw;
835 	dev->mt76.bus = bus_ops;
836 
837 	mdev->rev = (device_id << 16) |
838 		    (mt76_rr(dev, MT_HW_REV) & 0xff);
839 	dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
840 
841 	return 0;
842 }
843 
844 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
845 				  bool write_reg,
846 				  u32 clear, u32 set)
847 {
848 	struct mt76_dev *mdev = &dev->mt76;
849 	unsigned long flags;
850 
851 	spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
852 
853 	mdev->mmio.irqmask &= ~clear;
854 	mdev->mmio.irqmask |= set;
855 
856 	if (write_reg) {
857 		if (mtk_wed_device_active(&mdev->mmio.wed))
858 			mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
859 						    mdev->mmio.irqmask);
860 		else
861 			mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
862 		mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
863 	}
864 
865 	spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
866 }
867 
868 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
869 				    enum mt76_rxq_id q)
870 {
871 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
872 
873 	mt7915_irq_enable(dev, MT_INT_RX(q));
874 }
875 
876 /* TODO: support 2/4/6/8 MSI-X vectors */
877 static void mt7915_irq_tasklet(struct tasklet_struct *t)
878 {
879 	struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
880 	struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
881 	u32 intr, intr1, mask;
882 
883 	if (mtk_wed_device_active(wed)) {
884 		mtk_wed_device_irq_set_mask(wed, 0);
885 		if (dev->hif2)
886 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);
887 		intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
888 	} else {
889 		mt76_wr(dev, MT_INT_MASK_CSR, 0);
890 		if (dev->hif2)
891 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);
892 
893 		intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
894 		intr &= dev->mt76.mmio.irqmask;
895 		mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
896 	}
897 
898 	if (dev->hif2) {
899 		intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
900 		intr1 &= dev->mt76.mmio.irqmask;
901 		mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
902 
903 		intr |= intr1;
904 	}
905 
906 	trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
907 
908 	mask = intr & MT_INT_RX_DONE_ALL;
909 	if (intr & MT_INT_TX_DONE_MCU)
910 		mask |= MT_INT_TX_DONE_MCU;
911 
912 	mt7915_irq_disable(dev, mask);
913 
914 	if (intr & MT_INT_TX_DONE_MCU)
915 		napi_schedule(&dev->mt76.tx_napi);
916 
917 	if (intr & MT_INT_RX(MT_RXQ_MAIN))
918 		napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
919 
920 	if (intr & MT_INT_RX(MT_RXQ_BAND1))
921 		napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]);
922 
923 	if (intr & MT_INT_RX(MT_RXQ_MCU))
924 		napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
925 
926 	if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
927 		napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
928 
929 	if (!is_mt7915(&dev->mt76) &&
930 	    (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
931 		napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
932 
933 	if (intr & MT_INT_RX(MT_RXQ_BAND1_WA))
934 		napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
935 
936 	if (intr & MT_INT_MCU_CMD) {
937 		u32 val = mt76_rr(dev, MT_MCU_CMD);
938 
939 		mt76_wr(dev, MT_MCU_CMD, val);
940 		if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
941 			dev->recovery.state = val;
942 			mt7915_reset(dev);
943 		}
944 	}
945 }
946 
947 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
948 {
949 	struct mt7915_dev *dev = dev_instance;
950 	struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
951 
952 	if (mtk_wed_device_active(wed)) {
953 		mtk_wed_device_irq_set_mask(wed, 0);
954 	} else {
955 		mt76_wr(dev, MT_INT_MASK_CSR, 0);
956 		if (dev->hif2)
957 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);
958 	}
959 
960 	if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
961 		return IRQ_NONE;
962 
963 	tasklet_schedule(&dev->irq_tasklet);
964 
965 	return IRQ_HANDLED;
966 }
967 
968 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
969 				     void __iomem *mem_base, u32 device_id)
970 {
971 	static const struct mt76_driver_ops drv_ops = {
972 		/* txwi_size = txd size + txp size */
973 		.txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
974 		.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
975 			     MT_DRV_AMSDU_OFFLOAD,
976 		.survey_flags = SURVEY_INFO_TIME_TX |
977 				SURVEY_INFO_TIME_RX |
978 				SURVEY_INFO_TIME_BSS_RX,
979 		.token_size = MT7915_TOKEN_SIZE,
980 		.tx_prepare_skb = mt7915_tx_prepare_skb,
981 		.tx_complete_skb = mt76_connac_tx_complete_skb,
982 		.rx_skb = mt7915_queue_rx_skb,
983 		.rx_check = mt7915_rx_check,
984 		.rx_poll_complete = mt7915_rx_poll_complete,
985 		.sta_ps = mt7915_sta_ps,
986 		.sta_add = mt7915_mac_sta_add,
987 		.sta_remove = mt7915_mac_sta_remove,
988 		.update_survey = mt7915_update_channel,
989 	};
990 	struct mt7915_dev *dev;
991 	struct mt76_dev *mdev;
992 	int ret;
993 
994 	mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops);
995 	if (!mdev)
996 		return ERR_PTR(-ENOMEM);
997 
998 	dev = container_of(mdev, struct mt7915_dev, mt76);
999 
1000 	ret = mt7915_mmio_init(mdev, mem_base, device_id);
1001 	if (ret)
1002 		goto error;
1003 
1004 	tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet);
1005 
1006 	return dev;
1007 
1008 error:
1009 	mt76_free_device(&dev->mt76);
1010 
1011 	return ERR_PTR(ret);
1012 }
1013 
1014 static int __init mt7915_init(void)
1015 {
1016 	int ret;
1017 
1018 	ret = pci_register_driver(&mt7915_hif_driver);
1019 	if (ret)
1020 		return ret;
1021 
1022 	ret = pci_register_driver(&mt7915_pci_driver);
1023 	if (ret)
1024 		goto error_pci;
1025 
1026 	if (IS_ENABLED(CONFIG_MT7986_WMAC)) {
1027 		ret = platform_driver_register(&mt7986_wmac_driver);
1028 		if (ret)
1029 			goto error_wmac;
1030 	}
1031 
1032 	return 0;
1033 
1034 error_wmac:
1035 	pci_unregister_driver(&mt7915_pci_driver);
1036 error_pci:
1037 	pci_unregister_driver(&mt7915_hif_driver);
1038 
1039 	return ret;
1040 }
1041 
1042 static void __exit mt7915_exit(void)
1043 {
1044 	if (IS_ENABLED(CONFIG_MT7986_WMAC))
1045 		platform_driver_unregister(&mt7986_wmac_driver);
1046 
1047 	pci_unregister_driver(&mt7915_pci_driver);
1048 	pci_unregister_driver(&mt7915_hif_driver);
1049 }
1050 
1051 module_init(mt7915_init);
1052 module_exit(mt7915_exit);
1053 MODULE_LICENSE("Dual BSD/GPL");
1054