1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/platform_device.h> 7 #include <linux/pci.h> 8 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "../trace.h" 12 13 static const u32 mt7915_reg[] = { 14 [INT_SOURCE_CSR] = 0xd7010, 15 [INT_MASK_CSR] = 0xd7014, 16 [INT1_SOURCE_CSR] = 0xd7088, 17 [INT1_MASK_CSR] = 0xd708c, 18 [INT_MCU_CMD_SOURCE] = 0xd51f0, 19 [INT_MCU_CMD_EVENT] = 0x3108, 20 [WFDMA0_ADDR] = 0xd4000, 21 [WFDMA0_PCIE1_ADDR] = 0xd8000, 22 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 23 [CBTOP1_PHY_END] = 0x77ffffff, 24 [INFRA_MCU_ADDR_END] = 0x7c3fffff, 25 }; 26 27 static const u32 mt7916_reg[] = { 28 [INT_SOURCE_CSR] = 0xd4200, 29 [INT_MASK_CSR] = 0xd4204, 30 [INT1_SOURCE_CSR] = 0xd8200, 31 [INT1_MASK_CSR] = 0xd8204, 32 [INT_MCU_CMD_SOURCE] = 0xd41f0, 33 [INT_MCU_CMD_EVENT] = 0x2108, 34 [WFDMA0_ADDR] = 0xd4000, 35 [WFDMA0_PCIE1_ADDR] = 0xd8000, 36 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 37 [CBTOP1_PHY_END] = 0x7fffffff, 38 [INFRA_MCU_ADDR_END] = 0x7c085fff, 39 }; 40 41 static const u32 mt7986_reg[] = { 42 [INT_SOURCE_CSR] = 0x24200, 43 [INT_MASK_CSR] = 0x24204, 44 [INT1_SOURCE_CSR] = 0x28200, 45 [INT1_MASK_CSR] = 0x28204, 46 [INT_MCU_CMD_SOURCE] = 0x241f0, 47 [INT_MCU_CMD_EVENT] = 0x54000108, 48 [WFDMA0_ADDR] = 0x24000, 49 [WFDMA0_PCIE1_ADDR] = 0x28000, 50 [WFDMA_EXT_CSR_ADDR] = 0x27000, 51 [CBTOP1_PHY_END] = 0x7fffffff, 52 [INFRA_MCU_ADDR_END] = 0x7c085fff, 53 }; 54 55 static const u32 mt7915_offs[] = { 56 [TMAC_CDTR] = 0x090, 57 [TMAC_ODTR] = 0x094, 58 [TMAC_ATCR] = 0x098, 59 [TMAC_TRCR0] = 0x09c, 60 [TMAC_ICR0] = 0x0a4, 61 [TMAC_ICR1] = 0x0b4, 62 [TMAC_CTCR0] = 0x0f4, 63 [TMAC_TFCR0] = 0x1e0, 64 [MDP_BNRCFR0] = 0x070, 65 [MDP_BNRCFR1] = 0x074, 66 [ARB_DRNGR0] = 0x194, 67 [ARB_SCR] = 0x080, 68 [RMAC_MIB_AIRTIME14] = 0x3b8, 69 [AGG_AWSCR0] = 0x05c, 70 [AGG_PCR0] = 0x06c, 71 [AGG_ACR0] = 0x084, 72 [AGG_MRCR] = 0x098, 73 [AGG_ATCR1] = 0x0f0, 74 [AGG_ATCR3] = 0x0f4, 75 [LPON_UTTR0] = 0x080, 76 [LPON_UTTR1] = 0x084, 77 [LPON_FRCR] = 0x314, 78 [MIB_SDR3] = 0x014, 79 [MIB_SDR4] = 0x018, 80 [MIB_SDR5] = 0x01c, 81 [MIB_SDR7] = 0x024, 82 [MIB_SDR8] = 0x028, 83 [MIB_SDR9] = 0x02c, 84 [MIB_SDR10] = 0x030, 85 [MIB_SDR11] = 0x034, 86 [MIB_SDR12] = 0x038, 87 [MIB_SDR13] = 0x03c, 88 [MIB_SDR14] = 0x040, 89 [MIB_SDR15] = 0x044, 90 [MIB_SDR16] = 0x048, 91 [MIB_SDR17] = 0x04c, 92 [MIB_SDR18] = 0x050, 93 [MIB_SDR19] = 0x054, 94 [MIB_SDR20] = 0x058, 95 [MIB_SDR21] = 0x05c, 96 [MIB_SDR22] = 0x060, 97 [MIB_SDR23] = 0x064, 98 [MIB_SDR24] = 0x068, 99 [MIB_SDR25] = 0x06c, 100 [MIB_SDR27] = 0x074, 101 [MIB_SDR28] = 0x078, 102 [MIB_SDR29] = 0x07c, 103 [MIB_SDRVEC] = 0x080, 104 [MIB_SDR31] = 0x084, 105 [MIB_SDR32] = 0x088, 106 [MIB_SDRMUBF] = 0x090, 107 [MIB_DR8] = 0x0c0, 108 [MIB_DR9] = 0x0c4, 109 [MIB_DR11] = 0x0cc, 110 [MIB_MB_SDR0] = 0x100, 111 [MIB_MB_SDR1] = 0x104, 112 [TX_AGG_CNT] = 0x0a8, 113 [TX_AGG_CNT2] = 0x164, 114 [MIB_ARNG] = 0x4b8, 115 [WTBLON_TOP_WDUCR] = 0x0, 116 [WTBL_UPDATE] = 0x030, 117 [PLE_FL_Q_EMPTY] = 0x0b0, 118 [PLE_FL_Q_CTRL] = 0x1b0, 119 [PLE_AC_QEMPTY] = 0x500, 120 [PLE_FREEPG_CNT] = 0x100, 121 [PLE_FREEPG_HEAD_TAIL] = 0x104, 122 [PLE_PG_HIF_GROUP] = 0x110, 123 [PLE_HIF_PG_INFO] = 0x114, 124 [AC_OFFSET] = 0x040, 125 [ETBF_PAR_RPT0] = 0x068, 126 }; 127 128 static const u32 mt7916_offs[] = { 129 [TMAC_CDTR] = 0x0c8, 130 [TMAC_ODTR] = 0x0cc, 131 [TMAC_ATCR] = 0x00c, 132 [TMAC_TRCR0] = 0x010, 133 [TMAC_ICR0] = 0x014, 134 [TMAC_ICR1] = 0x018, 135 [TMAC_CTCR0] = 0x114, 136 [TMAC_TFCR0] = 0x0e4, 137 [MDP_BNRCFR0] = 0x090, 138 [MDP_BNRCFR1] = 0x094, 139 [ARB_DRNGR0] = 0x1e0, 140 [ARB_SCR] = 0x000, 141 [RMAC_MIB_AIRTIME14] = 0x0398, 142 [AGG_AWSCR0] = 0x030, 143 [AGG_PCR0] = 0x040, 144 [AGG_ACR0] = 0x054, 145 [AGG_MRCR] = 0x068, 146 [AGG_ATCR1] = 0x1a8, 147 [AGG_ATCR3] = 0x080, 148 [LPON_UTTR0] = 0x360, 149 [LPON_UTTR1] = 0x364, 150 [LPON_FRCR] = 0x37c, 151 [MIB_SDR3] = 0x698, 152 [MIB_SDR4] = 0x788, 153 [MIB_SDR5] = 0x780, 154 [MIB_SDR7] = 0x5a8, 155 [MIB_SDR8] = 0x78c, 156 [MIB_SDR9] = 0x024, 157 [MIB_SDR10] = 0x76c, 158 [MIB_SDR11] = 0x790, 159 [MIB_SDR12] = 0x558, 160 [MIB_SDR13] = 0x560, 161 [MIB_SDR14] = 0x564, 162 [MIB_SDR15] = 0x568, 163 [MIB_SDR16] = 0x7fc, 164 [MIB_SDR17] = 0x800, 165 [MIB_SDR18] = 0x030, 166 [MIB_SDR19] = 0x5ac, 167 [MIB_SDR20] = 0x5b0, 168 [MIB_SDR21] = 0x5b4, 169 [MIB_SDR22] = 0x770, 170 [MIB_SDR23] = 0x774, 171 [MIB_SDR24] = 0x778, 172 [MIB_SDR25] = 0x77c, 173 [MIB_SDR27] = 0x080, 174 [MIB_SDR28] = 0x084, 175 [MIB_SDR29] = 0x650, 176 [MIB_SDRVEC] = 0x5a8, 177 [MIB_SDR31] = 0x55c, 178 [MIB_SDR32] = 0x7a8, 179 [MIB_SDRMUBF] = 0x7ac, 180 [MIB_DR8] = 0x56c, 181 [MIB_DR9] = 0x570, 182 [MIB_DR11] = 0x574, 183 [MIB_MB_SDR0] = 0x688, 184 [MIB_MB_SDR1] = 0x690, 185 [TX_AGG_CNT] = 0x7dc, 186 [TX_AGG_CNT2] = 0x7ec, 187 [MIB_ARNG] = 0x0b0, 188 [WTBLON_TOP_WDUCR] = 0x200, 189 [WTBL_UPDATE] = 0x230, 190 [PLE_FL_Q_EMPTY] = 0x360, 191 [PLE_FL_Q_CTRL] = 0x3e0, 192 [PLE_AC_QEMPTY] = 0x600, 193 [PLE_FREEPG_CNT] = 0x380, 194 [PLE_FREEPG_HEAD_TAIL] = 0x384, 195 [PLE_PG_HIF_GROUP] = 0x00c, 196 [PLE_HIF_PG_INFO] = 0x388, 197 [AC_OFFSET] = 0x080, 198 [ETBF_PAR_RPT0] = 0x100, 199 }; 200 201 static const struct __map mt7915_reg_map[] = { 202 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 203 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */ 204 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 205 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 206 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 207 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 208 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 209 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 210 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 211 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 212 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 213 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 214 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 215 { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 216 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 217 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 218 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 219 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 220 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 221 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 222 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 223 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 224 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 225 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 226 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 227 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 228 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 229 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 230 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 231 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 232 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 233 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 234 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 235 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 236 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 237 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 238 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 239 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 240 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 241 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 242 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 243 { 0x0, 0x0, 0x0 }, /* imply end of search */ 244 }; 245 246 static const struct __map mt7916_reg_map[] = { 247 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 248 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 249 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA_2 (Reserved) */ 250 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */ 251 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 252 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 253 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 254 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 255 { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 256 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 257 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 258 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 259 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 260 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 261 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 262 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 263 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 264 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 265 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 266 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 267 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 268 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 269 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 270 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 271 { 0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */ 272 { 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */ 273 { 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure cr) */ 274 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 275 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 276 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 277 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 278 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 279 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 280 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 281 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 282 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 283 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 284 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 285 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 286 { 0x820c4000, 0xa8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 287 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */ 288 { 0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */ 289 { 0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */ 290 { 0x0, 0x0, 0x0 }, /* imply end of search */ 291 }; 292 293 static const struct __map mt7986_reg_map[] = { 294 { 0x54000000, 0x402000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 295 { 0x55000000, 0x403000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 296 { 0x56000000, 0x404000, 0x1000 }, /* WFDMA_2 (Reserved) */ 297 { 0x57000000, 0x405000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */ 298 { 0x58000000, 0x406000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 299 { 0x59000000, 0x407000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 300 { 0x820c0000, 0x408000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 301 { 0x820c8000, 0x40c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 302 { 0x820cc000, 0x40e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 303 { 0x820e0000, 0x420000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 304 { 0x820e1000, 0x420400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 305 { 0x820e2000, 0x420800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 306 { 0x820e3000, 0x420c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 307 { 0x820e4000, 0x421000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 308 { 0x820e5000, 0x421400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 309 { 0x820ce000, 0x421c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 310 { 0x820e7000, 0x421e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 311 { 0x820cf000, 0x422000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 312 { 0x820e9000, 0x423400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 313 { 0x820ea000, 0x424000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 314 { 0x820eb000, 0x424200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 315 { 0x820ec000, 0x424600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 316 { 0x820ed000, 0x424800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 317 { 0x820ca000, 0x426000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 318 { 0x820d0000, 0x430000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */ 319 { 0x00400000, 0x480000, 0x10000}, /* WF_MCU_SYSRAM */ 320 { 0x00410000, 0x490000, 0x10000}, /* WF_MCU_SYSRAM */ 321 { 0x820f0000, 0x4a0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 322 { 0x820f1000, 0x4a0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 323 { 0x820f2000, 0x4a0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 324 { 0x820f3000, 0x4a0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 325 { 0x820f4000, 0x4a1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 326 { 0x820f5000, 0x4a1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 327 { 0x820f7000, 0x4a1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 328 { 0x820f9000, 0x4a3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 329 { 0x820fa000, 0x4a4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 330 { 0x820fb000, 0x4a4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 331 { 0x820fc000, 0x4a4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 332 { 0x820fd000, 0x4a4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 333 { 0x820c4000, 0x4a8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 334 { 0x820b0000, 0x4ae000, 0x1000 }, /* [APB2] WFSYS_ON */ 335 { 0x80020000, 0x4b0000, 0x10000}, /* WF_TOP_MISC_OFF */ 336 { 0x81020000, 0x4c0000, 0x10000}, /* WF_TOP_MISC_ON */ 337 { 0x89000000, 0x4d0000, 0x1000 }, /* WF_MCU_CFG_ON */ 338 { 0x89010000, 0x4d1000, 0x1000 }, /* WF_MCU_CIRQ */ 339 { 0x89020000, 0x4d2000, 0x1000 }, /* WF_MCU_GPT */ 340 { 0x89030000, 0x4d3000, 0x1000 }, /* WF_MCU_WDT */ 341 { 0x80010000, 0x4d4000, 0x1000 }, /* WF_AXIDMA */ 342 { 0x0, 0x0, 0x0 }, /* imply end of search */ 343 }; 344 345 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr) 346 { 347 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 348 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 349 u32 l1_remap; 350 351 if (is_mt7986(&dev->mt76)) 352 return MT_CONN_INFRA_OFFSET(addr); 353 354 l1_remap = is_mt7915(&dev->mt76) ? 355 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916; 356 357 dev->bus_ops->rmw(&dev->mt76, l1_remap, 358 MT_HIF_REMAP_L1_MASK, 359 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 360 /* use read to push write */ 361 dev->bus_ops->rr(&dev->mt76, l1_remap); 362 363 return MT_HIF_REMAP_BASE_L1 + offset; 364 } 365 366 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr) 367 { 368 u32 offset, base; 369 370 if (is_mt7915(&dev->mt76)) { 371 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 372 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 373 374 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 375 MT_HIF_REMAP_L2_MASK, 376 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 377 378 /* use read to push write */ 379 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 380 } else { 381 u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0; 382 383 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr); 384 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr); 385 386 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs, 387 MT_HIF_REMAP_L2_MASK_MT7916, 388 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base)); 389 390 /* use read to push write */ 391 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs); 392 393 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs); 394 } 395 396 return offset; 397 } 398 399 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 400 { 401 int i; 402 403 if (addr < 0x100000) 404 return addr; 405 406 if (!dev->reg.map) { 407 dev_err(dev->mt76.dev, "err: reg_map is null\n"); 408 return addr; 409 } 410 411 for (i = 0; i < dev->reg.map_size; i++) { 412 u32 ofs; 413 414 if (addr < dev->reg.map[i].phys) 415 continue; 416 417 ofs = addr - dev->reg.map[i].phys; 418 if (ofs > dev->reg.map[i].size) 419 continue; 420 421 return dev->reg.map[i].maps + ofs; 422 } 423 424 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 425 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 426 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 427 return mt7915_reg_map_l1(dev, addr); 428 429 if (dev_is_pci(dev->mt76.dev) && 430 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 431 (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) 432 return mt7915_reg_map_l1(dev, addr); 433 434 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 435 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 436 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 437 return mt7915_reg_map_l1(dev, addr); 438 } 439 440 return mt7915_reg_map_l2(dev, addr); 441 } 442 443 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 444 { 445 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 446 u32 addr = __mt7915_reg_addr(dev, offset); 447 448 return dev->bus_ops->rr(mdev, addr); 449 } 450 451 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 452 { 453 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 454 u32 addr = __mt7915_reg_addr(dev, offset); 455 456 dev->bus_ops->wr(mdev, addr, val); 457 } 458 459 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 460 { 461 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 462 u32 addr = __mt7915_reg_addr(dev, offset); 463 464 return dev->bus_ops->rmw(mdev, addr, mask, val); 465 } 466 467 static int mt7915_mmio_init(struct mt76_dev *mdev, 468 void __iomem *mem_base, 469 u32 device_id) 470 { 471 struct mt76_bus_ops *bus_ops; 472 struct mt7915_dev *dev; 473 474 dev = container_of(mdev, struct mt7915_dev, mt76); 475 mt76_mmio_init(&dev->mt76, mem_base); 476 477 switch (device_id) { 478 case 0x7915: 479 dev->reg.reg_rev = mt7915_reg; 480 dev->reg.offs_rev = mt7915_offs; 481 dev->reg.map = mt7915_reg_map; 482 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map); 483 break; 484 case 0x7906: 485 dev->reg.reg_rev = mt7916_reg; 486 dev->reg.offs_rev = mt7916_offs; 487 dev->reg.map = mt7916_reg_map; 488 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map); 489 break; 490 case 0x7986: 491 dev->reg.reg_rev = mt7986_reg; 492 dev->reg.offs_rev = mt7916_offs; 493 dev->reg.map = mt7986_reg_map; 494 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map); 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 dev->bus_ops = dev->mt76.bus; 501 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 502 GFP_KERNEL); 503 if (!bus_ops) 504 return -ENOMEM; 505 506 bus_ops->rr = mt7915_rr; 507 bus_ops->wr = mt7915_wr; 508 bus_ops->rmw = mt7915_rmw; 509 dev->mt76.bus = bus_ops; 510 511 mdev->rev = (device_id << 16) | 512 (mt76_rr(dev, MT_HW_REV) & 0xff); 513 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 514 515 return 0; 516 } 517 518 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, 519 bool write_reg, 520 u32 clear, u32 set) 521 { 522 struct mt76_dev *mdev = &dev->mt76; 523 unsigned long flags; 524 525 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 526 527 mdev->mmio.irqmask &= ~clear; 528 mdev->mmio.irqmask |= set; 529 530 if (write_reg) { 531 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 532 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 533 } 534 535 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 536 } 537 538 static void mt7915_rx_poll_complete(struct mt76_dev *mdev, 539 enum mt76_rxq_id q) 540 { 541 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 542 543 mt7915_irq_enable(dev, MT_INT_RX(q)); 544 } 545 546 /* TODO: support 2/4/6/8 MSI-X vectors */ 547 static void mt7915_irq_tasklet(struct tasklet_struct *t) 548 { 549 struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet); 550 u32 intr, intr1, mask; 551 552 mt76_wr(dev, MT_INT_MASK_CSR, 0); 553 if (dev->hif2) 554 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 555 556 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 557 intr &= dev->mt76.mmio.irqmask; 558 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 559 560 if (dev->hif2) { 561 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 562 intr1 &= dev->mt76.mmio.irqmask; 563 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 564 565 intr |= intr1; 566 } 567 568 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 569 570 mask = intr & MT_INT_RX_DONE_ALL; 571 if (intr & MT_INT_TX_DONE_MCU) 572 mask |= MT_INT_TX_DONE_MCU; 573 574 mt7915_irq_disable(dev, mask); 575 576 if (intr & MT_INT_TX_DONE_MCU) 577 napi_schedule(&dev->mt76.tx_napi); 578 579 if (intr & MT_INT_RX(MT_RXQ_MAIN)) 580 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 581 582 if (intr & MT_INT_RX(MT_RXQ_EXT)) 583 napi_schedule(&dev->mt76.napi[MT_RXQ_EXT]); 584 585 if (intr & MT_INT_RX(MT_RXQ_MCU)) 586 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 587 588 if (intr & MT_INT_RX(MT_RXQ_MCU_WA)) 589 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 590 591 if (!is_mt7915(&dev->mt76) && 592 (intr & MT_INT_RX(MT_RXQ_MAIN_WA))) 593 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]); 594 595 if (intr & MT_INT_RX(MT_RXQ_EXT_WA)) 596 napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]); 597 598 if (intr & MT_INT_MCU_CMD) { 599 u32 val = mt76_rr(dev, MT_MCU_CMD); 600 601 mt76_wr(dev, MT_MCU_CMD, val); 602 if (val & MT_MCU_CMD_ERROR_MASK) { 603 dev->reset_state = val; 604 ieee80211_queue_work(mt76_hw(dev), &dev->reset_work); 605 wake_up(&dev->reset_wait); 606 } 607 } 608 } 609 610 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) 611 { 612 struct mt7915_dev *dev = dev_instance; 613 614 mt76_wr(dev, MT_INT_MASK_CSR, 0); 615 if (dev->hif2) 616 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 617 618 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 619 return IRQ_NONE; 620 621 tasklet_schedule(&dev->irq_tasklet); 622 623 return IRQ_HANDLED; 624 } 625 626 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 627 void __iomem *mem_base, u32 device_id) 628 { 629 static const struct mt76_driver_ops drv_ops = { 630 /* txwi_size = txd size + txp size */ 631 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7915_txp), 632 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ, 633 .survey_flags = SURVEY_INFO_TIME_TX | 634 SURVEY_INFO_TIME_RX | 635 SURVEY_INFO_TIME_BSS_RX, 636 .token_size = MT7915_TOKEN_SIZE, 637 .tx_prepare_skb = mt7915_tx_prepare_skb, 638 .tx_complete_skb = mt7915_tx_complete_skb, 639 .rx_skb = mt7915_queue_rx_skb, 640 .rx_check = mt7915_rx_check, 641 .rx_poll_complete = mt7915_rx_poll_complete, 642 .sta_ps = mt7915_sta_ps, 643 .sta_add = mt7915_mac_sta_add, 644 .sta_remove = mt7915_mac_sta_remove, 645 .update_survey = mt7915_update_channel, 646 }; 647 struct ieee80211_ops *ops; 648 struct mt7915_dev *dev; 649 struct mt76_dev *mdev; 650 int ret; 651 652 ops = devm_kmemdup(pdev, &mt7915_ops, sizeof(mt7915_ops), GFP_KERNEL); 653 if (!ops) 654 return ERR_PTR(-ENOMEM); 655 656 mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops); 657 if (!mdev) 658 return ERR_PTR(-ENOMEM); 659 660 dev = container_of(mdev, struct mt7915_dev, mt76); 661 662 ret = mt7915_mmio_init(mdev, mem_base, device_id); 663 if (ret) 664 goto error; 665 666 tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet); 667 668 mt76_wr(dev, MT_INT_MASK_CSR, 0); 669 670 return dev; 671 672 error: 673 mt76_free_device(&dev->mt76); 674 675 return ERR_PTR(ret); 676 } 677 678 static int __init mt7915_init(void) 679 { 680 int ret; 681 682 ret = pci_register_driver(&mt7915_hif_driver); 683 if (ret) 684 return ret; 685 686 ret = pci_register_driver(&mt7915_pci_driver); 687 if (ret) 688 goto error_pci; 689 690 if (IS_ENABLED(CONFIG_MT7986_WMAC)) { 691 ret = platform_driver_register(&mt7986_wmac_driver); 692 if (ret) 693 goto error_wmac; 694 } 695 696 return 0; 697 698 error_wmac: 699 pci_unregister_driver(&mt7915_pci_driver); 700 error_pci: 701 pci_unregister_driver(&mt7915_hif_driver); 702 703 return ret; 704 } 705 706 static void __exit mt7915_exit(void) 707 { 708 if (IS_ENABLED(CONFIG_MT7986_WMAC)) 709 platform_driver_unregister(&mt7986_wmac_driver); 710 711 pci_unregister_driver(&mt7915_pci_driver); 712 pci_unregister_driver(&mt7915_hif_driver); 713 } 714 715 module_init(mt7915_init); 716 module_exit(mt7915_exit); 717 MODULE_LICENSE("Dual BSD/GPL"); 718