1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/rtnetlink.h>
8 #include <linux/pci.h>
9 
10 #include "mt7915.h"
11 #include "mac.h"
12 #include "mcu.h"
13 #include "../trace.h"
14 #include "../dma.h"
15 
16 static bool wed_enable;
17 module_param(wed_enable, bool, 0644);
18 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support");
19 
20 static const u32 mt7915_reg[] = {
21 	[INT_SOURCE_CSR]		= 0xd7010,
22 	[INT_MASK_CSR]			= 0xd7014,
23 	[INT1_SOURCE_CSR]		= 0xd7088,
24 	[INT1_MASK_CSR]			= 0xd708c,
25 	[INT_MCU_CMD_SOURCE]		= 0xd51f0,
26 	[INT_MCU_CMD_EVENT]		= 0x3108,
27 	[WFDMA0_ADDR]			= 0xd4000,
28 	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
29 	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
30 	[CBTOP1_PHY_END]		= 0x77ffffff,
31 	[INFRA_MCU_ADDR_END]		= 0x7c3fffff,
32 	[FW_ASSERT_STAT_ADDR]		= 0x219848,
33 	[FW_EXCEPT_TYPE_ADDR]		= 0x21987c,
34 	[FW_EXCEPT_COUNT_ADDR]		= 0x219848,
35 	[FW_CIRQ_COUNT_ADDR]		= 0x216f94,
36 	[FW_CIRQ_IDX_ADDR]		= 0x216ef8,
37 	[FW_CIRQ_LISR_ADDR]		= 0x2170ac,
38 	[FW_TASK_ID_ADDR]		= 0x216f90,
39 	[FW_TASK_IDX_ADDR]		= 0x216f9c,
40 	[FW_TASK_QID1_ADDR]		= 0x219680,
41 	[FW_TASK_QID2_ADDR]		= 0x219760,
42 	[FW_TASK_START_ADDR]		= 0x219558,
43 	[FW_TASK_END_ADDR]		= 0x219554,
44 	[FW_TASK_SIZE_ADDR]		= 0x219560,
45 	[FW_LAST_MSG_ID_ADDR]		= 0x216f70,
46 	[FW_EINT_INFO_ADDR]		= 0x219818,
47 	[FW_SCHED_INFO_ADDR]		= 0x219828,
48 	[SWDEF_BASE_ADDR]		= 0x41f200,
49 	[TXQ_WED_RING_BASE]		= 0xd7300,
50 	[RXQ_WED_RING_BASE]		= 0xd7410,
51 	[RXQ_WED_DATA_RING_BASE]	= 0xd4500,
52 };
53 
54 static const u32 mt7916_reg[] = {
55 	[INT_SOURCE_CSR]		= 0xd4200,
56 	[INT_MASK_CSR]			= 0xd4204,
57 	[INT1_SOURCE_CSR]		= 0xd8200,
58 	[INT1_MASK_CSR]			= 0xd8204,
59 	[INT_MCU_CMD_SOURCE]		= 0xd41f0,
60 	[INT_MCU_CMD_EVENT]		= 0x2108,
61 	[WFDMA0_ADDR]			= 0xd4000,
62 	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
63 	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
64 	[CBTOP1_PHY_END]		= 0x7fffffff,
65 	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
66 	[FW_ASSERT_STAT_ADDR]		= 0x02204c14,
67 	[FW_EXCEPT_TYPE_ADDR]		= 0x022051a4,
68 	[FW_EXCEPT_COUNT_ADDR]		= 0x022050bc,
69 	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
70 	[FW_CIRQ_IDX_ADDR]		= 0x02204f84,
71 	[FW_CIRQ_LISR_ADDR]		= 0x022050d0,
72 	[FW_TASK_ID_ADDR]		= 0x0220406c,
73 	[FW_TASK_IDX_ADDR]		= 0x0220500c,
74 	[FW_TASK_QID1_ADDR]		= 0x022028c8,
75 	[FW_TASK_QID2_ADDR]		= 0x02202a38,
76 	[FW_TASK_START_ADDR]		= 0x0220286c,
77 	[FW_TASK_END_ADDR]		= 0x02202870,
78 	[FW_TASK_SIZE_ADDR]		= 0x02202878,
79 	[FW_LAST_MSG_ID_ADDR]		= 0x02204fe8,
80 	[FW_EINT_INFO_ADDR]		= 0x0220525c,
81 	[FW_SCHED_INFO_ADDR]		= 0x0220516c,
82 	[SWDEF_BASE_ADDR]		= 0x411400,
83 	[TXQ_WED_RING_BASE]		= 0xd7300,
84 	[RXQ_WED_RING_BASE]		= 0xd7410,
85 	[RXQ_WED_DATA_RING_BASE]	= 0xd4540,
86 };
87 
88 static const u32 mt7986_reg[] = {
89 	[INT_SOURCE_CSR]		= 0x24200,
90 	[INT_MASK_CSR]			= 0x24204,
91 	[INT1_SOURCE_CSR]		= 0x28200,
92 	[INT1_MASK_CSR]			= 0x28204,
93 	[INT_MCU_CMD_SOURCE]		= 0x241f0,
94 	[INT_MCU_CMD_EVENT]		= 0x54000108,
95 	[WFDMA0_ADDR]			= 0x24000,
96 	[WFDMA0_PCIE1_ADDR]		= 0x28000,
97 	[WFDMA_EXT_CSR_ADDR]		= 0x27000,
98 	[CBTOP1_PHY_END]		= 0x7fffffff,
99 	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
100 	[FW_ASSERT_STAT_ADDR]		= 0x02204b54,
101 	[FW_EXCEPT_TYPE_ADDR]		= 0x022050dc,
102 	[FW_EXCEPT_COUNT_ADDR]		= 0x02204ffc,
103 	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
104 	[FW_CIRQ_IDX_ADDR]		= 0x02204ec4,
105 	[FW_CIRQ_LISR_ADDR]		= 0x02205010,
106 	[FW_TASK_ID_ADDR]		= 0x02204fac,
107 	[FW_TASK_IDX_ADDR]		= 0x02204f4c,
108 	[FW_TASK_QID1_ADDR]		= 0x02202814,
109 	[FW_TASK_QID2_ADDR]		= 0x02202984,
110 	[FW_TASK_START_ADDR]		= 0x022027b8,
111 	[FW_TASK_END_ADDR]		= 0x022027bc,
112 	[FW_TASK_SIZE_ADDR]		= 0x022027c4,
113 	[FW_LAST_MSG_ID_ADDR]		= 0x02204f28,
114 	[FW_EINT_INFO_ADDR]		= 0x02205194,
115 	[FW_SCHED_INFO_ADDR]		= 0x022051a4,
116 	[SWDEF_BASE_ADDR]		= 0x411400,
117 	[TXQ_WED_RING_BASE]		= 0x24420,
118 	[RXQ_WED_RING_BASE]		= 0x24520,
119 	[RXQ_WED_DATA_RING_BASE]	= 0x24540,
120 };
121 
122 static const u32 mt7915_offs[] = {
123 	[TMAC_CDTR]		= 0x090,
124 	[TMAC_ODTR]		= 0x094,
125 	[TMAC_ATCR]		= 0x098,
126 	[TMAC_TRCR0]		= 0x09c,
127 	[TMAC_ICR0]		= 0x0a4,
128 	[TMAC_ICR1]		= 0x0b4,
129 	[TMAC_CTCR0]		= 0x0f4,
130 	[TMAC_TFCR0]		= 0x1e0,
131 	[MDP_BNRCFR0]		= 0x070,
132 	[MDP_BNRCFR1]		= 0x074,
133 	[ARB_DRNGR0]		= 0x194,
134 	[ARB_SCR]		= 0x080,
135 	[RMAC_MIB_AIRTIME14]	= 0x3b8,
136 	[AGG_AWSCR0]		= 0x05c,
137 	[AGG_PCR0]		= 0x06c,
138 	[AGG_ACR0]		= 0x084,
139 	[AGG_ACR4]		= 0x08c,
140 	[AGG_MRCR]		= 0x098,
141 	[AGG_ATCR1]		= 0x0f0,
142 	[AGG_ATCR3]		= 0x0f4,
143 	[LPON_UTTR0]		= 0x080,
144 	[LPON_UTTR1]		= 0x084,
145 	[LPON_FRCR]		= 0x314,
146 	[MIB_SDR3]		= 0x014,
147 	[MIB_SDR4]		= 0x018,
148 	[MIB_SDR5]		= 0x01c,
149 	[MIB_SDR7]		= 0x024,
150 	[MIB_SDR8]		= 0x028,
151 	[MIB_SDR9]		= 0x02c,
152 	[MIB_SDR10]		= 0x030,
153 	[MIB_SDR11]		= 0x034,
154 	[MIB_SDR12]		= 0x038,
155 	[MIB_SDR13]		= 0x03c,
156 	[MIB_SDR14]		= 0x040,
157 	[MIB_SDR15]		= 0x044,
158 	[MIB_SDR16]		= 0x048,
159 	[MIB_SDR17]		= 0x04c,
160 	[MIB_SDR18]		= 0x050,
161 	[MIB_SDR19]		= 0x054,
162 	[MIB_SDR20]		= 0x058,
163 	[MIB_SDR21]		= 0x05c,
164 	[MIB_SDR22]		= 0x060,
165 	[MIB_SDR23]		= 0x064,
166 	[MIB_SDR24]		= 0x068,
167 	[MIB_SDR25]		= 0x06c,
168 	[MIB_SDR27]		= 0x074,
169 	[MIB_SDR28]		= 0x078,
170 	[MIB_SDR29]		= 0x07c,
171 	[MIB_SDRVEC]		= 0x080,
172 	[MIB_SDR31]		= 0x084,
173 	[MIB_SDR32]		= 0x088,
174 	[MIB_SDRMUBF]		= 0x090,
175 	[MIB_DR8]		= 0x0c0,
176 	[MIB_DR9]		= 0x0c4,
177 	[MIB_DR11]		= 0x0cc,
178 	[MIB_MB_SDR0]		= 0x100,
179 	[MIB_MB_SDR1]		= 0x104,
180 	[TX_AGG_CNT]		= 0x0a8,
181 	[TX_AGG_CNT2]		= 0x164,
182 	[MIB_ARNG]		= 0x4b8,
183 	[WTBLON_TOP_WDUCR]	= 0x0,
184 	[WTBL_UPDATE]		= 0x030,
185 	[PLE_FL_Q_EMPTY]	= 0x0b0,
186 	[PLE_FL_Q_CTRL]		= 0x1b0,
187 	[PLE_AC_QEMPTY]		= 0x500,
188 	[PLE_FREEPG_CNT]	= 0x100,
189 	[PLE_FREEPG_HEAD_TAIL]	= 0x104,
190 	[PLE_PG_HIF_GROUP]	= 0x110,
191 	[PLE_HIF_PG_INFO]	= 0x114,
192 	[AC_OFFSET]		= 0x040,
193 	[ETBF_PAR_RPT0]		= 0x068,
194 };
195 
196 static const u32 mt7916_offs[] = {
197 	[TMAC_CDTR]		= 0x0c8,
198 	[TMAC_ODTR]		= 0x0cc,
199 	[TMAC_ATCR]		= 0x00c,
200 	[TMAC_TRCR0]		= 0x010,
201 	[TMAC_ICR0]		= 0x014,
202 	[TMAC_ICR1]		= 0x018,
203 	[TMAC_CTCR0]		= 0x114,
204 	[TMAC_TFCR0]		= 0x0e4,
205 	[MDP_BNRCFR0]		= 0x090,
206 	[MDP_BNRCFR1]		= 0x094,
207 	[ARB_DRNGR0]		= 0x1e0,
208 	[ARB_SCR]		= 0x000,
209 	[RMAC_MIB_AIRTIME14]	= 0x0398,
210 	[AGG_AWSCR0]		= 0x030,
211 	[AGG_PCR0]		= 0x040,
212 	[AGG_ACR0]		= 0x054,
213 	[AGG_ACR4]		= 0x05c,
214 	[AGG_MRCR]		= 0x068,
215 	[AGG_ATCR1]		= 0x1a8,
216 	[AGG_ATCR3]		= 0x080,
217 	[LPON_UTTR0]		= 0x360,
218 	[LPON_UTTR1]		= 0x364,
219 	[LPON_FRCR]		= 0x37c,
220 	[MIB_SDR3]		= 0x698,
221 	[MIB_SDR4]		= 0x788,
222 	[MIB_SDR5]		= 0x780,
223 	[MIB_SDR7]		= 0x5a8,
224 	[MIB_SDR8]		= 0x78c,
225 	[MIB_SDR9]		= 0x024,
226 	[MIB_SDR10]		= 0x76c,
227 	[MIB_SDR11]		= 0x790,
228 	[MIB_SDR12]		= 0x558,
229 	[MIB_SDR13]		= 0x560,
230 	[MIB_SDR14]		= 0x564,
231 	[MIB_SDR15]		= 0x568,
232 	[MIB_SDR16]		= 0x7fc,
233 	[MIB_SDR17]		= 0x800,
234 	[MIB_SDR18]		= 0x030,
235 	[MIB_SDR19]		= 0x5ac,
236 	[MIB_SDR20]		= 0x5b0,
237 	[MIB_SDR21]		= 0x5b4,
238 	[MIB_SDR22]		= 0x770,
239 	[MIB_SDR23]		= 0x774,
240 	[MIB_SDR24]		= 0x778,
241 	[MIB_SDR25]		= 0x77c,
242 	[MIB_SDR27]		= 0x080,
243 	[MIB_SDR28]		= 0x084,
244 	[MIB_SDR29]		= 0x650,
245 	[MIB_SDRVEC]		= 0x5a8,
246 	[MIB_SDR31]		= 0x55c,
247 	[MIB_SDR32]		= 0x7a8,
248 	[MIB_SDRMUBF]		= 0x7ac,
249 	[MIB_DR8]		= 0x56c,
250 	[MIB_DR9]		= 0x570,
251 	[MIB_DR11]		= 0x574,
252 	[MIB_MB_SDR0]		= 0x688,
253 	[MIB_MB_SDR1]		= 0x690,
254 	[TX_AGG_CNT]		= 0x7dc,
255 	[TX_AGG_CNT2]		= 0x7ec,
256 	[MIB_ARNG]		= 0x0b0,
257 	[WTBLON_TOP_WDUCR]	= 0x200,
258 	[WTBL_UPDATE]		= 0x230,
259 	[PLE_FL_Q_EMPTY]	= 0x360,
260 	[PLE_FL_Q_CTRL]		= 0x3e0,
261 	[PLE_AC_QEMPTY]		= 0x600,
262 	[PLE_FREEPG_CNT]	= 0x380,
263 	[PLE_FREEPG_HEAD_TAIL]	= 0x384,
264 	[PLE_PG_HIF_GROUP]	= 0x00c,
265 	[PLE_HIF_PG_INFO]	= 0x388,
266 	[AC_OFFSET]		= 0x080,
267 	[ETBF_PAR_RPT0]		= 0x100,
268 };
269 
270 static const struct mt76_connac_reg_map mt7915_reg_map[] = {
271 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
272 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
273 	{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
274 	{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
275 	{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
276 	{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
277 	{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
278 	{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
279 	{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
280 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
281 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
282 	{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
283 	{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
284 	{ 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
285 	{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
286 	{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
287 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
288 	{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
289 	{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
290 	{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
291 	{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
292 	{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
293 	{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
294 	{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
295 	{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
296 	{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
297 	{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
298 	{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
299 	{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
300 	{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
301 	{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
302 	{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
303 	{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
304 	{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
305 	{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
306 	{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
307 	{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
308 	{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
309 	{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
310 	{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
311 	{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
312 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
313 };
314 
315 static const struct mt76_connac_reg_map mt7916_reg_map[] = {
316 	{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
317 	{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
318 	{ 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
319 	{ 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
320 	{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
321 	{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
322 	{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
323 	{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
324 	{ 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
325 	{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
326 	{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
327 	{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
328 	{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
329 	{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
330 	{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
331 	{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
332 	{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
333 	{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
334 	{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
335 	{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
336 	{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
337 	{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
338 	{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
339 	{ 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
340 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
341 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
342 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
343 	{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
344 	{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
345 	{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
346 	{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
347 	{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
348 	{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
349 	{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
350 	{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
351 	{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
352 	{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
353 	{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
354 	{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
355 	{ 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
356 	{ 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
357 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
358 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
359 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
360 };
361 
362 static const struct mt76_connac_reg_map mt7986_reg_map[] = {
363 	{ 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
364 	{ 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
365 	{ 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
366 	{ 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
367 	{ 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
368 	{ 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
369 	{ 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
370 	{ 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
371 	{ 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
372 	{ 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
373 	{ 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
374 	{ 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
375 	{ 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
376 	{ 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
377 	{ 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
378 	{ 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
379 	{ 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
380 	{ 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
381 	{ 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
382 	{ 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
383 	{ 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
384 	{ 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
385 	{ 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
386 	{ 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
387 	{ 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
388 	{ 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
389 	{ 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
390 	{ 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
391 	{ 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
392 	{ 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
393 	{ 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
394 	{ 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
395 	{ 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
396 	{ 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
397 	{ 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
398 	{ 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
399 	{ 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
400 	{ 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
401 	{ 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
402 	{ 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
403 	{ 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
404 	{ 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
405 	{ 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
406 	{ 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
407 	{ 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
408 	{ 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
409 	{ 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
410 	{ 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
411 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
412 };
413 
414 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
415 {
416 	u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
417 	u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
418 	u32 l1_remap;
419 
420 	if (is_mt798x(&dev->mt76))
421 		return MT_CONN_INFRA_OFFSET(addr);
422 
423 	l1_remap = is_mt7915(&dev->mt76) ?
424 		   MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
425 
426 	dev->bus_ops->rmw(&dev->mt76, l1_remap,
427 			  MT_HIF_REMAP_L1_MASK,
428 			  FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
429 	/* use read to push write */
430 	dev->bus_ops->rr(&dev->mt76, l1_remap);
431 
432 	return MT_HIF_REMAP_BASE_L1 + offset;
433 }
434 
435 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
436 {
437 	u32 offset, base;
438 
439 	if (is_mt7915(&dev->mt76)) {
440 		offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
441 		base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
442 
443 		dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
444 				  MT_HIF_REMAP_L2_MASK,
445 				  FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
446 
447 		/* use read to push write */
448 		dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
449 	} else {
450 		u32 ofs = is_mt798x(&dev->mt76) ? 0x400000 : 0;
451 
452 		offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
453 		base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
454 
455 		dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
456 				  MT_HIF_REMAP_L2_MASK_MT7916,
457 				  FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
458 
459 		/* use read to push write */
460 		dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
461 
462 		offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
463 	}
464 
465 	return offset;
466 }
467 
468 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
469 {
470 	int i;
471 
472 	if (addr < 0x100000)
473 		return addr;
474 
475 	if (!dev->reg.map) {
476 		dev_err(dev->mt76.dev, "err: reg_map is null\n");
477 		return addr;
478 	}
479 
480 	for (i = 0; i < dev->reg.map_size; i++) {
481 		u32 ofs;
482 
483 		if (addr < dev->reg.map[i].phys)
484 			continue;
485 
486 		ofs = addr - dev->reg.map[i].phys;
487 		if (ofs > dev->reg.map[i].size)
488 			continue;
489 
490 		return dev->reg.map[i].maps + ofs;
491 	}
492 
493 	if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
494 	    (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
495 	    (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
496 		return mt7915_reg_map_l1(dev, addr);
497 
498 	if (dev_is_pci(dev->mt76.dev) &&
499 	    ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
500 	    addr >= MT_CBTOP2_PHY_START))
501 		return mt7915_reg_map_l1(dev, addr);
502 
503 	/* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
504 	if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
505 		addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
506 		return mt7915_reg_map_l1(dev, addr);
507 	}
508 
509 	return mt7915_reg_map_l2(dev, addr);
510 }
511 
512 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,
513 			  size_t len)
514 {
515 	u32 addr = __mt7915_reg_addr(dev, offset);
516 
517 	memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
518 }
519 
520 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
521 {
522 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
523 	u32 addr = __mt7915_reg_addr(dev, offset);
524 
525 	return dev->bus_ops->rr(mdev, addr);
526 }
527 
528 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
529 {
530 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
531 	u32 addr = __mt7915_reg_addr(dev, offset);
532 
533 	dev->bus_ops->wr(mdev, addr, val);
534 }
535 
536 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
537 {
538 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
539 	u32 addr = __mt7915_reg_addr(dev, offset);
540 
541 	return dev->bus_ops->rmw(mdev, addr, mask, val);
542 }
543 
544 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
545 static int mt7915_mmio_wed_offload_enable(struct mtk_wed_device *wed)
546 {
547 	struct mt7915_dev *dev;
548 
549 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
550 
551 	spin_lock_bh(&dev->mt76.token_lock);
552 	dev->mt76.token_size = wed->wlan.token_start;
553 	spin_unlock_bh(&dev->mt76.token_lock);
554 
555 	return !wait_event_timeout(dev->mt76.tx_wait,
556 				   !dev->mt76.wed_token_count, HZ);
557 }
558 
559 static void mt7915_mmio_wed_offload_disable(struct mtk_wed_device *wed)
560 {
561 	struct mt7915_dev *dev;
562 
563 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
564 
565 	spin_lock_bh(&dev->mt76.token_lock);
566 	dev->mt76.token_size = MT7915_TOKEN_SIZE;
567 	spin_unlock_bh(&dev->mt76.token_lock);
568 }
569 
570 static void mt7915_mmio_wed_release_rx_buf(struct mtk_wed_device *wed)
571 {
572 	struct mt7915_dev *dev;
573 	int i;
574 
575 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
576 	for (i = 0; i < dev->mt76.rx_token_size; i++) {
577 		struct mt76_txwi_cache *t;
578 
579 		t = mt76_rx_token_release(&dev->mt76, i);
580 		if (!t || !t->ptr)
581 			continue;
582 
583 		mt76_put_page_pool_buf(t->ptr, false);
584 		t->ptr = NULL;
585 
586 		mt76_put_rxwi(&dev->mt76, t);
587 	}
588 
589 	mt76_free_pending_rxwi(&dev->mt76);
590 }
591 
592 static u32 mt7915_mmio_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
593 {
594 	struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
595 	struct mt76_txwi_cache *t = NULL;
596 	struct mt7915_dev *dev;
597 	struct mt76_queue *q;
598 	int i, len;
599 
600 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
601 	q = &dev->mt76.q_rx[MT_RXQ_MAIN];
602 	len = SKB_WITH_OVERHEAD(q->buf_size);
603 
604 	for (i = 0; i < size; i++) {
605 		enum dma_data_direction dir;
606 		dma_addr_t addr;
607 		u32 offset;
608 		int token;
609 		void *buf;
610 
611 		t = mt76_get_rxwi(&dev->mt76);
612 		if (!t)
613 			goto unmap;
614 
615 		buf = mt76_get_page_pool_buf(q, &offset, q->buf_size);
616 		if (!buf)
617 			goto unmap;
618 
619 		addr = page_pool_get_dma_addr(virt_to_head_page(buf)) + offset;
620 		dir = page_pool_get_dma_dir(q->page_pool);
621 		dma_sync_single_for_device(dev->mt76.dma_dev, addr, len, dir);
622 
623 		desc->buf0 = cpu_to_le32(addr);
624 		token = mt76_rx_token_consume(&dev->mt76, buf, t, addr);
625 		if (token < 0) {
626 			mt76_put_page_pool_buf(buf, false);
627 			goto unmap;
628 		}
629 
630 		desc->token |= cpu_to_le32(FIELD_PREP(MT_DMA_CTL_TOKEN,
631 						      token));
632 		desc++;
633 	}
634 
635 	return 0;
636 
637 unmap:
638 	if (t)
639 		mt76_put_rxwi(&dev->mt76, t);
640 	mt7915_mmio_wed_release_rx_buf(wed);
641 	return -ENOMEM;
642 }
643 
644 static void mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device *wed,
645 					    struct mtk_wed_wo_rx_stats *stats)
646 {
647 	int idx = le16_to_cpu(stats->wlan_idx);
648 	struct mt7915_dev *dev;
649 	struct mt76_wcid *wcid;
650 
651 	dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
652 
653 	if (idx >= mt7915_wtbl_size(dev))
654 		return;
655 
656 	rcu_read_lock();
657 
658 	wcid = rcu_dereference(dev->mt76.wcid[idx]);
659 	if (wcid) {
660 		wcid->stats.rx_bytes += le32_to_cpu(stats->rx_byte_cnt);
661 		wcid->stats.rx_packets += le32_to_cpu(stats->rx_pkt_cnt);
662 		wcid->stats.rx_errors += le32_to_cpu(stats->rx_err_cnt);
663 		wcid->stats.rx_drops += le32_to_cpu(stats->rx_drop_cnt);
664 	}
665 
666 	rcu_read_unlock();
667 }
668 
669 static int mt7915_mmio_wed_reset(struct mtk_wed_device *wed)
670 {
671 	struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed);
672 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
673 	struct mt76_phy *mphy = &dev->mphy;
674 	int ret;
675 
676 	ASSERT_RTNL();
677 
678 	if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state))
679 		return -EBUSY;
680 
681 	ret = mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1,
682 				 mphy->band_idx);
683 	if (ret)
684 		goto out;
685 
686 	rtnl_unlock();
687 	if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) {
688 		dev_err(mdev->dev, "wed reset timeout\n");
689 		ret = -ETIMEDOUT;
690 	}
691 	rtnl_lock();
692 out:
693 	clear_bit(MT76_STATE_WED_RESET, &mphy->state);
694 
695 	return ret;
696 }
697 
698 static void mt7915_mmio_wed_reset_complete(struct mtk_wed_device *wed)
699 {
700 	struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);
701 
702 	complete(&dev->mmio.wed_reset_complete);
703 }
704 #endif
705 
706 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
707 			 bool pci, int *irq)
708 {
709 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
710 	struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
711 	int ret;
712 
713 	if (!wed_enable)
714 		return 0;
715 
716 	if (pci) {
717 		struct pci_dev *pci_dev = pdev_ptr;
718 
719 		wed->wlan.pci_dev = pci_dev;
720 		wed->wlan.bus_type = MTK_WED_BUS_PCIE;
721 		wed->wlan.base = devm_ioremap(dev->mt76.dev,
722 					      pci_resource_start(pci_dev, 0),
723 					      pci_resource_len(pci_dev, 0));
724 		wed->wlan.phy_base = pci_resource_start(pci_dev, 0);
725 		wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) +
726 				      MT_INT_WED_SOURCE_CSR;
727 		wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) +
728 				       MT_INT_WED_MASK_CSR;
729 		wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) +
730 				       MT_WFDMA_EXT_CSR_BASE;
731 		wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) +
732 				     MT_TXQ_WED_RING_BASE;
733 		wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) +
734 					 MT_RXQ_WED_RING_BASE;
735 		wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) +
736 					 MT_WPDMA_GLO_CFG;
737 		wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) +
738 				     MT_RXQ_WED_DATA_RING_BASE;
739 	} else {
740 		struct platform_device *plat_dev = pdev_ptr;
741 		struct resource *res;
742 
743 		res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
744 		if (!res)
745 			return 0;
746 
747 		wed->wlan.platform_dev = plat_dev;
748 		wed->wlan.bus_type = MTK_WED_BUS_AXI;
749 		wed->wlan.base = devm_ioremap(dev->mt76.dev, res->start,
750 					      resource_size(res));
751 		wed->wlan.phy_base = res->start;
752 		wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR;
753 		wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR;
754 		wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE;
755 		wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE;
756 		wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG;
757 		wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE;
758 	}
759 	wed->wlan.nbuf = MT7915_HW_TOKEN_SIZE;
760 	wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30;
761 	wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31;
762 	wed->wlan.txfree_tbit = is_mt798x(&dev->mt76) ? 2 : 1;
763 	wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
764 	wed->wlan.wcid_512 = !is_mt7915(&dev->mt76);
765 
766 	wed->wlan.rx_nbuf = 65536;
767 	wed->wlan.rx_npkt = MT7915_WED_RX_TOKEN_SIZE;
768 	wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE);
769 	if (is_mt7915(&dev->mt76)) {
770 		wed->wlan.rx_tbit[0] = 16;
771 		wed->wlan.rx_tbit[1] = 17;
772 	} else if (is_mt798x(&dev->mt76)) {
773 		wed->wlan.rx_tbit[0] = 22;
774 		wed->wlan.rx_tbit[1] = 23;
775 	} else {
776 		wed->wlan.rx_tbit[0] = 18;
777 		wed->wlan.rx_tbit[1] = 19;
778 	}
779 
780 	wed->wlan.init_buf = mt7915_wed_init_buf;
781 	wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable;
782 	wed->wlan.offload_disable = mt7915_mmio_wed_offload_disable;
783 	wed->wlan.init_rx_buf = mt7915_mmio_wed_init_rx_buf;
784 	wed->wlan.release_rx_buf = mt7915_mmio_wed_release_rx_buf;
785 	wed->wlan.update_wo_rx_stats = mt7915_mmio_wed_update_rx_stats;
786 	wed->wlan.reset = mt7915_mmio_wed_reset;
787 	wed->wlan.reset_complete = mt7915_mmio_wed_reset_complete;
788 
789 	dev->mt76.rx_token_size = wed->wlan.rx_npkt;
790 
791 	if (mtk_wed_device_attach(wed))
792 		return 0;
793 
794 	*irq = wed->irq;
795 	dev->mt76.dma_dev = wed->dev;
796 
797 	ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
798 	if (ret)
799 		return ret;
800 
801 	return 1;
802 #else
803 	return 0;
804 #endif
805 }
806 
807 static int mt7915_mmio_init(struct mt76_dev *mdev,
808 			    void __iomem *mem_base,
809 			    u32 device_id)
810 {
811 	struct mt76_bus_ops *bus_ops;
812 	struct mt7915_dev *dev;
813 
814 	dev = container_of(mdev, struct mt7915_dev, mt76);
815 	mt76_mmio_init(&dev->mt76, mem_base);
816 
817 	switch (device_id) {
818 	case 0x7915:
819 		dev->reg.reg_rev = mt7915_reg;
820 		dev->reg.offs_rev = mt7915_offs;
821 		dev->reg.map = mt7915_reg_map;
822 		dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
823 		break;
824 	case 0x7906:
825 		dev->reg.reg_rev = mt7916_reg;
826 		dev->reg.offs_rev = mt7916_offs;
827 		dev->reg.map = mt7916_reg_map;
828 		dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
829 		break;
830 	case 0x7981:
831 	case 0x7986:
832 		dev->reg.reg_rev = mt7986_reg;
833 		dev->reg.offs_rev = mt7916_offs;
834 		dev->reg.map = mt7986_reg_map;
835 		dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
836 		break;
837 	default:
838 		return -EINVAL;
839 	}
840 
841 	dev->bus_ops = dev->mt76.bus;
842 	bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
843 			       GFP_KERNEL);
844 	if (!bus_ops)
845 		return -ENOMEM;
846 
847 	bus_ops->rr = mt7915_rr;
848 	bus_ops->wr = mt7915_wr;
849 	bus_ops->rmw = mt7915_rmw;
850 	dev->mt76.bus = bus_ops;
851 
852 	mdev->rev = (device_id << 16) |
853 		    (mt76_rr(dev, MT_HW_REV) & 0xff);
854 	dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
855 
856 	return 0;
857 }
858 
859 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
860 				  bool write_reg,
861 				  u32 clear, u32 set)
862 {
863 	struct mt76_dev *mdev = &dev->mt76;
864 	unsigned long flags;
865 
866 	spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
867 
868 	mdev->mmio.irqmask &= ~clear;
869 	mdev->mmio.irqmask |= set;
870 
871 	if (write_reg) {
872 		if (mtk_wed_device_active(&mdev->mmio.wed))
873 			mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
874 						    mdev->mmio.irqmask);
875 		else
876 			mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
877 		mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
878 	}
879 
880 	spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
881 }
882 
883 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
884 				    enum mt76_rxq_id q)
885 {
886 	struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
887 
888 	mt7915_irq_enable(dev, MT_INT_RX(q));
889 }
890 
891 /* TODO: support 2/4/6/8 MSI-X vectors */
892 static void mt7915_irq_tasklet(struct tasklet_struct *t)
893 {
894 	struct mt7915_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
895 	struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
896 	u32 intr, intr1, mask;
897 
898 	if (mtk_wed_device_active(wed)) {
899 		mtk_wed_device_irq_set_mask(wed, 0);
900 		if (dev->hif2)
901 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);
902 		intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
903 	} else {
904 		mt76_wr(dev, MT_INT_MASK_CSR, 0);
905 		if (dev->hif2)
906 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);
907 
908 		intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
909 		intr &= dev->mt76.mmio.irqmask;
910 		mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
911 	}
912 
913 	if (dev->hif2) {
914 		intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
915 		intr1 &= dev->mt76.mmio.irqmask;
916 		mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
917 
918 		intr |= intr1;
919 	}
920 
921 	trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
922 
923 	mask = intr & MT_INT_RX_DONE_ALL;
924 	if (intr & MT_INT_TX_DONE_MCU)
925 		mask |= MT_INT_TX_DONE_MCU;
926 
927 	mt7915_irq_disable(dev, mask);
928 
929 	if (intr & MT_INT_TX_DONE_MCU)
930 		napi_schedule(&dev->mt76.tx_napi);
931 
932 	if (intr & MT_INT_RX(MT_RXQ_MAIN))
933 		napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
934 
935 	if (intr & MT_INT_RX(MT_RXQ_BAND1))
936 		napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]);
937 
938 	if (intr & MT_INT_RX(MT_RXQ_MCU))
939 		napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
940 
941 	if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
942 		napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
943 
944 	if (!is_mt7915(&dev->mt76) &&
945 	    (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
946 		napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
947 
948 	if (intr & MT_INT_RX(MT_RXQ_BAND1_WA))
949 		napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
950 
951 	if (intr & MT_INT_MCU_CMD) {
952 		u32 val = mt76_rr(dev, MT_MCU_CMD);
953 
954 		mt76_wr(dev, MT_MCU_CMD, val);
955 		if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
956 			dev->recovery.state = val;
957 			mt7915_reset(dev);
958 		}
959 	}
960 }
961 
962 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
963 {
964 	struct mt7915_dev *dev = dev_instance;
965 	struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
966 
967 	if (mtk_wed_device_active(wed))
968 		mtk_wed_device_irq_set_mask(wed, 0);
969 	else
970 		mt76_wr(dev, MT_INT_MASK_CSR, 0);
971 
972 	if (dev->hif2)
973 		mt76_wr(dev, MT_INT1_MASK_CSR, 0);
974 
975 	if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
976 		return IRQ_NONE;
977 
978 	tasklet_schedule(&dev->mt76.irq_tasklet);
979 
980 	return IRQ_HANDLED;
981 }
982 
983 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
984 				     void __iomem *mem_base, u32 device_id)
985 {
986 	static const struct mt76_driver_ops drv_ops = {
987 		/* txwi_size = txd size + txp size */
988 		.txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
989 		.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
990 			     MT_DRV_AMSDU_OFFLOAD,
991 		.survey_flags = SURVEY_INFO_TIME_TX |
992 				SURVEY_INFO_TIME_RX |
993 				SURVEY_INFO_TIME_BSS_RX,
994 		.token_size = MT7915_TOKEN_SIZE,
995 		.tx_prepare_skb = mt7915_tx_prepare_skb,
996 		.tx_complete_skb = mt76_connac_tx_complete_skb,
997 		.rx_skb = mt7915_queue_rx_skb,
998 		.rx_check = mt7915_rx_check,
999 		.rx_poll_complete = mt7915_rx_poll_complete,
1000 		.sta_add = mt7915_mac_sta_add,
1001 		.sta_remove = mt7915_mac_sta_remove,
1002 		.update_survey = mt7915_update_channel,
1003 	};
1004 	struct mt7915_dev *dev;
1005 	struct mt76_dev *mdev;
1006 	int ret;
1007 
1008 	mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops);
1009 	if (!mdev)
1010 		return ERR_PTR(-ENOMEM);
1011 
1012 	dev = container_of(mdev, struct mt7915_dev, mt76);
1013 
1014 	ret = mt7915_mmio_init(mdev, mem_base, device_id);
1015 	if (ret)
1016 		goto error;
1017 
1018 	tasklet_setup(&mdev->irq_tasklet, mt7915_irq_tasklet);
1019 
1020 	return dev;
1021 
1022 error:
1023 	mt76_free_device(&dev->mt76);
1024 
1025 	return ERR_PTR(ret);
1026 }
1027 
1028 static int __init mt7915_init(void)
1029 {
1030 	int ret;
1031 
1032 	ret = pci_register_driver(&mt7915_hif_driver);
1033 	if (ret)
1034 		return ret;
1035 
1036 	ret = pci_register_driver(&mt7915_pci_driver);
1037 	if (ret)
1038 		goto error_pci;
1039 
1040 	if (IS_ENABLED(CONFIG_MT798X_WMAC)) {
1041 		ret = platform_driver_register(&mt798x_wmac_driver);
1042 		if (ret)
1043 			goto error_wmac;
1044 	}
1045 
1046 	return 0;
1047 
1048 error_wmac:
1049 	pci_unregister_driver(&mt7915_pci_driver);
1050 error_pci:
1051 	pci_unregister_driver(&mt7915_hif_driver);
1052 
1053 	return ret;
1054 }
1055 
1056 static void __exit mt7915_exit(void)
1057 {
1058 	if (IS_ENABLED(CONFIG_MT798X_WMAC))
1059 		platform_driver_unregister(&mt798x_wmac_driver);
1060 
1061 	pci_unregister_driver(&mt7915_pci_driver);
1062 	pci_unregister_driver(&mt7915_hif_driver);
1063 }
1064 
1065 module_init(mt7915_init);
1066 module_exit(mt7915_exit);
1067 MODULE_LICENSE("Dual BSD/GPL");
1068