1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 struct mt7915_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /* event table */ 27 enum { 28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 29 MCU_EVENT_FW_START = 0x01, 30 MCU_EVENT_GENERIC = 0x01, 31 MCU_EVENT_ACCESS_REG = 0x02, 32 MCU_EVENT_MT_PATCH_SEM = 0x04, 33 MCU_EVENT_CH_PRIVILEGE = 0x18, 34 MCU_EVENT_EXT = 0xed, 35 MCU_EVENT_RESTART_DL = 0xef, 36 }; 37 38 /* ext event table */ 39 enum { 40 MCU_EXT_EVENT_PS_SYNC = 0x5, 41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 44 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 46 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 47 }; 48 49 enum { 50 MCU_ATE_SET_TRX = 0x1, 51 MCU_ATE_SET_FREQ_OFFSET = 0xa, 52 MCU_ATE_SET_SLOT_TIME = 0x13, 53 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 54 }; 55 56 struct mt7915_mcu_rxd { 57 __le32 rxd[6]; 58 59 __le16 len; 60 __le16 pkt_type_id; 61 62 u8 eid; 63 u8 seq; 64 __le16 __rsv; 65 66 u8 ext_eid; 67 u8 __rsv1[2]; 68 u8 s2d_index; 69 }; 70 71 struct mt7915_mcu_thermal_ctrl { 72 u8 ctrl_id; 73 u8 band_idx; 74 union { 75 struct { 76 u8 protect_type; /* 1: duty admit, 2: radio off */ 77 u8 trigger_type; /* 0: low, 1: high */ 78 } __packed type; 79 struct { 80 u8 duty_level; /* level 0~3 */ 81 u8 duty_cycle; 82 } __packed duty; 83 }; 84 } __packed; 85 86 struct mt7915_mcu_thermal_notify { 87 struct mt7915_mcu_rxd rxd; 88 89 struct mt7915_mcu_thermal_ctrl ctrl; 90 __le32 temperature; 91 u8 rsv[8]; 92 } __packed; 93 94 struct mt7915_mcu_csa_notify { 95 struct mt7915_mcu_rxd rxd; 96 97 u8 omac_idx; 98 u8 csa_count; 99 u8 band_idx; 100 u8 rsv; 101 } __packed; 102 103 struct mt7915_mcu_rdd_report { 104 struct mt7915_mcu_rxd rxd; 105 106 u8 band_idx; 107 u8 long_detected; 108 u8 constant_prf_detected; 109 u8 staggered_prf_detected; 110 u8 radar_type_idx; 111 u8 periodic_pulse_num; 112 u8 long_pulse_num; 113 u8 hw_pulse_num; 114 115 u8 out_lpn; 116 u8 out_spn; 117 u8 out_crpn; 118 u8 out_crpw; 119 u8 out_crbn; 120 u8 out_stgpn; 121 u8 out_stgpw; 122 123 u8 rsv; 124 125 __le32 out_pri_const; 126 __le32 out_pri_stg[3]; 127 128 struct { 129 __le32 start; 130 __le16 pulse_width; 131 __le16 pulse_power; 132 u8 mdrdy_flag; 133 u8 rsv[3]; 134 } long_pulse[32]; 135 136 struct { 137 __le32 start; 138 __le16 pulse_width; 139 __le16 pulse_power; 140 u8 mdrdy_flag; 141 u8 rsv[3]; 142 } periodic_pulse[32]; 143 144 struct { 145 __le32 start; 146 __le16 pulse_width; 147 __le16 pulse_power; 148 u8 sc_pass; 149 u8 sw_reset; 150 u8 mdrdy_flag; 151 u8 tx_active; 152 } hw_pulse[32]; 153 } __packed; 154 155 struct mt7915_mcu_eeprom { 156 u8 buffer_mode; 157 u8 format; 158 __le16 len; 159 } __packed; 160 161 struct mt7915_mcu_eeprom_info { 162 __le32 addr; 163 __le32 valid; 164 u8 data[16]; 165 } __packed; 166 167 struct mt7915_mcu_phy_rx_info { 168 u8 category; 169 u8 rate; 170 u8 mode; 171 u8 nsts; 172 u8 gi; 173 u8 coding; 174 u8 stbc; 175 u8 bw; 176 }; 177 178 struct mt7915_mcu_mib { 179 __le32 band; 180 __le32 offs; 181 __le64 data; 182 } __packed; 183 184 enum mt7915_chan_mib_offs { 185 MIB_BUSY_TIME = 14, 186 MIB_TX_TIME = 81, 187 MIB_RX_TIME, 188 MIB_OBSS_AIRTIME = 86 189 }; 190 191 struct edca { 192 u8 queue; 193 u8 set; 194 u8 aifs; 195 u8 cw_min; 196 __le16 cw_max; 197 __le16 txop; 198 }; 199 200 struct mt7915_mcu_tx { 201 u8 total; 202 u8 action; 203 u8 valid; 204 u8 mode; 205 206 struct edca edca[IEEE80211_NUM_ACS]; 207 } __packed; 208 209 #define WMM_AIFS_SET BIT(0) 210 #define WMM_CW_MIN_SET BIT(1) 211 #define WMM_CW_MAX_SET BIT(2) 212 #define WMM_TXOP_SET BIT(3) 213 #define WMM_PARAM_SET GENMASK(3, 0) 214 215 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 216 #define MCU_PKT_ID 0xa0 217 218 enum { 219 MCU_Q_QUERY, 220 MCU_Q_SET, 221 MCU_Q_RESERVED, 222 MCU_Q_NA 223 }; 224 225 enum { 226 MCU_S2D_H2N, 227 MCU_S2D_C2N, 228 MCU_S2D_H2C, 229 MCU_S2D_H2CN 230 }; 231 232 enum { 233 MCU_FW_LOG_WM, 234 MCU_FW_LOG_WA, 235 MCU_FW_LOG_TO_HOST, 236 }; 237 238 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 239 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 240 #define __MCU_CMD_FIELD_QUERY BIT(16) 241 #define __MCU_CMD_FIELD_WA BIT(17) 242 243 enum { 244 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 245 MCU_CMD_FW_START_REQ = 0x02, 246 MCU_CMD_INIT_ACCESS_REG = 0x3, 247 MCU_CMD_NIC_POWER_CTRL = 0x4, 248 MCU_CMD_PATCH_START_REQ = 0x05, 249 MCU_CMD_PATCH_FINISH_REQ = 0x07, 250 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 251 MCU_CMD_WA_PARAM = 0xC4, 252 MCU_CMD_EXT_CID = 0xED, 253 MCU_CMD_FW_SCATTER = 0xEE, 254 MCU_CMD_RESTART_DL_REQ = 0xEF, 255 }; 256 257 enum { 258 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 259 MCU_EXT_CMD_RF_TEST = 0x04, 260 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 261 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 262 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 263 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 264 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 265 MCU_EXT_CMD_THERMAL_PROT = 0x23, 266 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 267 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 268 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 269 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 270 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 271 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 272 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 273 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 274 MCU_EXT_CMD_ATE_CTRL = 0x3d, 275 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 276 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 277 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 278 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 279 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 280 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 281 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 282 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 283 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 284 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 285 MCU_EXT_CMD_SCS_CTRL = 0x82, 286 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 287 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 288 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 289 MCU_EXT_CMD_MURU_CTRL = 0x9f, 290 MCU_EXT_CMD_SET_SPR = 0xa8, 291 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 292 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 293 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 294 }; 295 296 enum { 297 MCU_TWT_AGRT_ADD, 298 MCU_TWT_AGRT_MODIFY, 299 MCU_TWT_AGRT_DELETE, 300 MCU_TWT_AGRT_TEARDOWN, 301 MCU_TWT_AGRT_GET_TSF, 302 }; 303 304 enum { 305 MCU_WA_PARAM_CMD_QUERY, 306 MCU_WA_PARAM_CMD_SET, 307 MCU_WA_PARAM_CMD_CAPABILITY, 308 MCU_WA_PARAM_CMD_DEBUG, 309 }; 310 311 enum { 312 MCU_WA_PARAM_PDMA_RX = 0x04, 313 MCU_WA_PARAM_CPU_UTIL = 0x0b, 314 MCU_WA_PARAM_RED = 0x0e, 315 }; 316 317 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, MCU_CMD_##_t) 318 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 319 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 320 MCU_EXT_CMD_##_t)) 321 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 322 323 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 324 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 325 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 326 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 327 MCU_WA_PARAM_CMD_##_t)) 328 329 enum { 330 PATCH_SEM_RELEASE, 331 PATCH_SEM_GET 332 }; 333 334 enum { 335 PATCH_NOT_DL_SEM_FAIL, 336 PATCH_IS_DL, 337 PATCH_NOT_DL_SEM_SUCCESS, 338 PATCH_REL_SEM_SUCCESS 339 }; 340 341 enum { 342 FW_STATE_INITIAL, 343 FW_STATE_FW_DOWNLOAD, 344 FW_STATE_NORMAL_OPERATION, 345 FW_STATE_NORMAL_TRX, 346 FW_STATE_WACPU_RDY = 7 347 }; 348 349 enum { 350 EE_MODE_EFUSE, 351 EE_MODE_BUFFER, 352 }; 353 354 enum { 355 EE_FORMAT_BIN, 356 EE_FORMAT_WHOLE, 357 EE_FORMAT_MULTIPLE, 358 }; 359 360 enum { 361 MCU_PHY_STATE_TX_RATE, 362 MCU_PHY_STATE_RX_RATE, 363 MCU_PHY_STATE_RSSI, 364 MCU_PHY_STATE_CONTENTION_RX_RATE, 365 MCU_PHY_STATE_OFDMLQ_CNINFO, 366 }; 367 368 #define STA_TYPE_STA BIT(0) 369 #define STA_TYPE_AP BIT(1) 370 #define STA_TYPE_ADHOC BIT(2) 371 #define STA_TYPE_WDS BIT(4) 372 #define STA_TYPE_BC BIT(5) 373 374 #define NETWORK_INFRA BIT(16) 375 #define NETWORK_P2P BIT(17) 376 #define NETWORK_IBSS BIT(18) 377 #define NETWORK_WDS BIT(21) 378 379 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 380 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 381 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 382 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 383 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 384 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 385 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 386 387 #define CONN_STATE_DISCONNECT 0 388 #define CONN_STATE_CONNECT 1 389 #define CONN_STATE_PORT_SECURE 2 390 391 enum { 392 DEV_INFO_ACTIVE, 393 DEV_INFO_MAX_NUM 394 }; 395 396 enum { 397 SCS_SEND_DATA, 398 SCS_SET_MANUAL_PD_TH, 399 SCS_CONFIG, 400 SCS_ENABLE, 401 SCS_SHOW_INFO, 402 SCS_GET_GLO_ADDR, 403 SCS_GET_GLO_ADDR_EVENT, 404 }; 405 406 enum { 407 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 408 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 409 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 410 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 411 CMD_CBW_10MHZ, 412 CMD_CBW_5MHZ, 413 CMD_CBW_8080MHZ, 414 415 CMD_HE_MCS_BW80 = 0, 416 CMD_HE_MCS_BW160, 417 CMD_HE_MCS_BW8080, 418 CMD_HE_MCS_BW_NUM 419 }; 420 421 struct tlv { 422 __le16 tag; 423 __le16 len; 424 } __packed; 425 426 struct bss_info_omac { 427 __le16 tag; 428 __le16 len; 429 u8 hw_bss_idx; 430 u8 omac_idx; 431 u8 band_idx; 432 u8 rsv0; 433 __le32 conn_type; 434 u32 rsv1; 435 } __packed; 436 437 struct bss_info_basic { 438 __le16 tag; 439 __le16 len; 440 __le32 network_type; 441 u8 active; 442 u8 rsv0; 443 __le16 bcn_interval; 444 u8 bssid[ETH_ALEN]; 445 u8 wmm_idx; 446 u8 dtim_period; 447 u8 bmc_wcid_lo; 448 u8 cipher; 449 u8 phy_mode; 450 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 451 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 452 u8 bmc_wcid_hi; /* high Byte and version */ 453 u8 rsv[2]; 454 } __packed; 455 456 struct bss_info_rf_ch { 457 __le16 tag; 458 __le16 len; 459 u8 pri_ch; 460 u8 center_ch0; 461 u8 center_ch1; 462 u8 bw; 463 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 464 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 465 u8 rsv[2]; 466 } __packed; 467 468 struct bss_info_ext_bss { 469 __le16 tag; 470 __le16 len; 471 __le32 mbss_tsf_offset; /* in unit of us */ 472 u8 rsv[8]; 473 } __packed; 474 475 struct bss_info_bmc_rate { 476 __le16 tag; 477 __le16 len; 478 __le16 bc_trans; 479 __le16 mc_trans; 480 u8 short_preamble; 481 u8 rsv[7]; 482 } __packed; 483 484 struct bss_info_ra { 485 __le16 tag; 486 __le16 len; 487 u8 op_mode; 488 u8 adhoc_en; 489 u8 short_preamble; 490 u8 tx_streams; 491 u8 rx_streams; 492 u8 algo; 493 u8 force_sgi; 494 u8 force_gf; 495 u8 ht_mode; 496 u8 has_20_sta; /* Check if any sta support GF. */ 497 u8 bss_width_trigger_events; 498 u8 vht_nss_cap; 499 u8 vht_bw_signal; /* not use */ 500 u8 vht_force_sgi; /* not use */ 501 u8 se_off; 502 u8 antenna_idx; 503 u8 train_up_rule; 504 u8 rsv[3]; 505 unsigned short train_up_high_thres; 506 short train_up_rule_rssi; 507 unsigned short low_traffic_thres; 508 __le16 max_phyrate; 509 __le32 phy_cap; 510 __le32 interval; 511 __le32 fast_interval; 512 } __packed; 513 514 struct bss_info_hw_amsdu { 515 __le16 tag; 516 __le16 len; 517 __le32 cmp_bitmap_0; 518 __le32 cmp_bitmap_1; 519 __le16 trig_thres; 520 u8 enable; 521 u8 rsv; 522 } __packed; 523 524 struct bss_info_color { 525 __le16 tag; 526 __le16 len; 527 u8 disable; 528 u8 color; 529 u8 rsv[2]; 530 } __packed; 531 532 struct bss_info_he { 533 __le16 tag; 534 __le16 len; 535 u8 he_pe_duration; 536 u8 vht_op_info_present; 537 __le16 he_rts_thres; 538 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 539 u8 rsv[6]; 540 } __packed; 541 542 struct bss_info_bcn { 543 __le16 tag; 544 __le16 len; 545 u8 ver; 546 u8 enable; 547 __le16 sub_ntlv; 548 } __packed __aligned(4); 549 550 struct bss_info_bcn_cntdwn { 551 __le16 tag; 552 __le16 len; 553 u8 cnt; 554 u8 rsv[3]; 555 } __packed __aligned(4); 556 557 struct bss_info_bcn_mbss { 558 #define MAX_BEACON_NUM 32 559 __le16 tag; 560 __le16 len; 561 __le32 bitmap; 562 __le16 offset[MAX_BEACON_NUM]; 563 u8 rsv[8]; 564 } __packed __aligned(4); 565 566 struct bss_info_bcn_cont { 567 __le16 tag; 568 __le16 len; 569 __le16 tim_ofs; 570 __le16 csa_ofs; 571 __le16 bcc_ofs; 572 __le16 pkt_len; 573 } __packed __aligned(4); 574 575 enum { 576 BSS_INFO_BCN_CSA, 577 BSS_INFO_BCN_BCC, 578 BSS_INFO_BCN_MBSSID, 579 BSS_INFO_BCN_CONTENT, 580 BSS_INFO_BCN_MAX 581 }; 582 583 enum { 584 BSS_INFO_OMAC, 585 BSS_INFO_BASIC, 586 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 587 BSS_INFO_PM, /* sta only */ 588 BSS_INFO_UAPSD, /* sta only */ 589 BSS_INFO_ROAM_DETECT, /* obsoleted */ 590 BSS_INFO_LQ_RM, /* obsoleted */ 591 BSS_INFO_EXT_BSS, 592 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 593 BSS_INFO_SYNC_MODE, /* obsoleted */ 594 BSS_INFO_RA, 595 BSS_INFO_HW_AMSDU, 596 BSS_INFO_BSS_COLOR, 597 BSS_INFO_HE_BASIC, 598 BSS_INFO_PROTECT_INFO, 599 BSS_INFO_OFFLOAD, 600 BSS_INFO_11V_MBSSID, 601 BSS_INFO_MAX_NUM 602 }; 603 604 enum { 605 WTBL_RESET_AND_SET = 1, 606 WTBL_SET, 607 WTBL_QUERY, 608 WTBL_RESET_ALL 609 }; 610 611 struct wtbl_req_hdr { 612 u8 wlan_idx_lo; 613 u8 operation; 614 __le16 tlv_num; 615 u8 wlan_idx_hi; 616 u8 rsv[3]; 617 } __packed; 618 619 struct wtbl_generic { 620 __le16 tag; 621 __le16 len; 622 u8 peer_addr[ETH_ALEN]; 623 u8 muar_idx; 624 u8 skip_tx; 625 u8 cf_ack; 626 u8 qos; 627 u8 mesh; 628 u8 adm; 629 __le16 partial_aid; 630 u8 baf_en; 631 u8 aad_om; 632 } __packed; 633 634 struct wtbl_rx { 635 __le16 tag; 636 __le16 len; 637 u8 rcid; 638 u8 rca1; 639 u8 rca2; 640 u8 rv; 641 u8 rsv[4]; 642 } __packed; 643 644 struct wtbl_ht { 645 __le16 tag; 646 __le16 len; 647 u8 ht; 648 u8 ldpc; 649 u8 af; 650 u8 mm; 651 u8 rsv[4]; 652 } __packed; 653 654 struct wtbl_vht { 655 __le16 tag; 656 __le16 len; 657 u8 ldpc; 658 u8 dyn_bw; 659 u8 vht; 660 u8 txop_ps; 661 u8 rsv[4]; 662 } __packed; 663 664 struct wtbl_hdr_trans { 665 __le16 tag; 666 __le16 len; 667 u8 to_ds; 668 u8 from_ds; 669 u8 no_rx_trans; 670 u8 _rsv; 671 }; 672 673 enum { 674 MT_BA_TYPE_INVALID, 675 MT_BA_TYPE_ORIGINATOR, 676 MT_BA_TYPE_RECIPIENT 677 }; 678 679 enum { 680 RST_BA_MAC_TID_MATCH, 681 RST_BA_MAC_MATCH, 682 RST_BA_NO_MATCH 683 }; 684 685 struct wtbl_ba { 686 __le16 tag; 687 __le16 len; 688 /* common */ 689 u8 tid; 690 u8 ba_type; 691 u8 rsv0[2]; 692 /* originator only */ 693 __le16 sn; 694 u8 ba_en; 695 u8 ba_winsize_idx; 696 /* originator & recipient */ 697 __le16 ba_winsize; 698 /* recipient only */ 699 u8 peer_addr[ETH_ALEN]; 700 u8 rst_ba_tid; 701 u8 rst_ba_sel; 702 u8 rst_ba_sb; 703 u8 band_idx; 704 u8 rsv1[4]; 705 } __packed; 706 707 struct wtbl_smps { 708 __le16 tag; 709 __le16 len; 710 u8 smps; 711 u8 rsv[3]; 712 } __packed; 713 714 enum { 715 WTBL_GENERIC, 716 WTBL_RX, 717 WTBL_HT, 718 WTBL_VHT, 719 WTBL_PEER_PS, /* not used */ 720 WTBL_TX_PS, 721 WTBL_HDR_TRANS, 722 WTBL_SEC_KEY, 723 WTBL_BA, 724 WTBL_RDG, /* obsoleted */ 725 WTBL_PROTECT, /* not used */ 726 WTBL_CLEAR, /* not used */ 727 WTBL_BF, 728 WTBL_SMPS, 729 WTBL_RAW_DATA, /* debug only */ 730 WTBL_PN, 731 WTBL_SPE, 732 WTBL_MAX_NUM 733 }; 734 735 struct sta_ntlv_hdr { 736 u8 rsv[2]; 737 __le16 tlv_num; 738 } __packed; 739 740 struct sta_req_hdr { 741 u8 bss_idx; 742 u8 wlan_idx_lo; 743 __le16 tlv_num; 744 u8 is_tlv_append; 745 u8 muar_idx; 746 u8 wlan_idx_hi; 747 u8 rsv; 748 } __packed; 749 750 struct sta_rec_basic { 751 __le16 tag; 752 __le16 len; 753 __le32 conn_type; 754 u8 conn_state; 755 u8 qos; 756 __le16 aid; 757 u8 peer_addr[ETH_ALEN]; 758 __le16 extra_info; 759 } __packed; 760 761 struct sta_rec_ht { 762 __le16 tag; 763 __le16 len; 764 __le16 ht_cap; 765 u16 rsv; 766 } __packed; 767 768 struct sta_rec_vht { 769 __le16 tag; 770 __le16 len; 771 __le32 vht_cap; 772 __le16 vht_rx_mcs_map; 773 __le16 vht_tx_mcs_map; 774 u8 rts_bw_sig; 775 u8 rsv[3]; 776 } __packed; 777 778 struct sta_rec_uapsd { 779 __le16 tag; 780 __le16 len; 781 u8 dac_map; 782 u8 tac_map; 783 u8 max_sp; 784 u8 rsv0; 785 __le16 listen_interval; 786 u8 rsv1[2]; 787 } __packed; 788 789 struct sta_rec_muru { 790 __le16 tag; 791 __le16 len; 792 793 struct { 794 bool ofdma_dl_en; 795 bool ofdma_ul_en; 796 bool mimo_dl_en; 797 bool mimo_ul_en; 798 u8 rsv[4]; 799 } cfg; 800 801 struct { 802 u8 punc_pream_rx; 803 bool he_20m_in_40m_2g; 804 bool he_20m_in_160m; 805 bool he_80m_in_160m; 806 bool lt16_sigb; 807 bool rx_su_comp_sigb; 808 bool rx_su_non_comp_sigb; 809 u8 rsv; 810 } ofdma_dl; 811 812 struct { 813 u8 t_frame_dur; 814 u8 mu_cascading; 815 u8 uo_ra; 816 u8 he_2x996_tone; 817 u8 rx_t_frame_11ac; 818 u8 rsv[3]; 819 } ofdma_ul; 820 821 struct { 822 bool vht_mu_bfee; 823 bool partial_bw_dl_mimo; 824 u8 rsv[2]; 825 } mimo_dl; 826 827 struct { 828 bool full_ul_mimo; 829 bool partial_ul_mimo; 830 u8 rsv[2]; 831 } mimo_ul; 832 } __packed; 833 834 struct sta_rec_he { 835 __le16 tag; 836 __le16 len; 837 838 __le32 he_cap; 839 840 u8 t_frame_dur; 841 u8 max_ampdu_exp; 842 u8 bw_set; 843 u8 device_class; 844 u8 dcm_tx_mode; 845 u8 dcm_tx_max_nss; 846 u8 dcm_rx_mode; 847 u8 dcm_rx_max_nss; 848 u8 dcm_max_ru; 849 u8 punc_pream_rx; 850 u8 pkt_ext; 851 u8 rsv1; 852 853 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 854 855 u8 rsv2[2]; 856 } __packed; 857 858 struct sta_rec_ba { 859 __le16 tag; 860 __le16 len; 861 u8 tid; 862 u8 ba_type; 863 u8 amsdu; 864 u8 ba_en; 865 __le16 ssn; 866 __le16 winsize; 867 } __packed; 868 869 struct sta_rec_amsdu { 870 __le16 tag; 871 __le16 len; 872 u8 max_amsdu_num; 873 u8 max_mpdu_size; 874 u8 amsdu_en; 875 u8 rsv; 876 } __packed; 877 878 struct sec_key { 879 u8 cipher_id; 880 u8 cipher_len; 881 u8 key_id; 882 u8 key_len; 883 u8 key[32]; 884 } __packed; 885 886 struct sta_rec_sec { 887 __le16 tag; 888 __le16 len; 889 u8 add; 890 u8 n_cipher; 891 u8 rsv[2]; 892 893 struct sec_key key[2]; 894 } __packed; 895 896 struct sta_phy { 897 u8 type; 898 u8 flag; 899 u8 stbc; 900 u8 sgi; 901 u8 bw; 902 u8 ldpc; 903 u8 mcs; 904 u8 nss; 905 u8 he_ltf; 906 }; 907 908 struct sta_rec_ra { 909 __le16 tag; 910 __le16 len; 911 912 u8 valid; 913 u8 auto_rate; 914 u8 phy_mode; 915 u8 channel; 916 u8 bw; 917 u8 disable_cck; 918 u8 ht_mcs32; 919 u8 ht_gf; 920 u8 ht_mcs[4]; 921 u8 mmps_mode; 922 u8 gband_256; 923 u8 af; 924 u8 auth_wapi_mode; 925 u8 rate_len; 926 927 u8 supp_mode; 928 u8 supp_cck_rate; 929 u8 supp_ofdm_rate; 930 __le32 supp_ht_mcs; 931 __le16 supp_vht_mcs[4]; 932 933 u8 op_mode; 934 u8 op_vht_chan_width; 935 u8 op_vht_rx_nss; 936 u8 op_vht_rx_nss_type; 937 938 __le32 sta_cap; 939 940 struct sta_phy phy; 941 } __packed; 942 943 struct sta_rec_ra_fixed { 944 __le16 tag; 945 __le16 len; 946 947 __le32 field; 948 u8 op_mode; 949 u8 op_vht_chan_width; 950 u8 op_vht_rx_nss; 951 u8 op_vht_rx_nss_type; 952 953 struct sta_phy phy; 954 955 u8 spe_en; 956 u8 short_preamble; 957 u8 is_5g; 958 u8 mmps_mode; 959 } __packed; 960 961 enum { 962 RATE_PARAM_FIXED = 3, 963 RATE_PARAM_FIXED_HE_LTF = 7, 964 RATE_PARAM_FIXED_MCS, 965 RATE_PARAM_FIXED_GI = 11, 966 RATE_PARAM_AUTO = 20, 967 }; 968 969 #define RATE_CFG_MCS GENMASK(3, 0) 970 #define RATE_CFG_NSS GENMASK(7, 4) 971 #define RATE_CFG_GI GENMASK(11, 8) 972 #define RATE_CFG_BW GENMASK(15, 12) 973 #define RATE_CFG_STBC GENMASK(19, 16) 974 #define RATE_CFG_LDPC GENMASK(23, 20) 975 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 976 #define RATE_CFG_HE_LTF GENMASK(31, 28) 977 978 struct sta_rec_bf { 979 __le16 tag; 980 __le16 len; 981 982 __le16 pfmu; /* 0xffff: no access right for PFMU */ 983 bool su_mu; /* 0: SU, 1: MU */ 984 u8 bf_cap; /* 0: iBF, 1: eBF */ 985 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 986 u8 ndpa_rate; 987 u8 ndp_rate; 988 u8 rept_poll_rate; 989 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 990 u8 ncol; 991 u8 nrow; 992 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 993 994 u8 mem_total; 995 u8 mem_20m; 996 struct { 997 u8 row; 998 u8 col: 6, row_msb: 2; 999 } mem[4]; 1000 1001 __le16 smart_ant; 1002 u8 se_idx; 1003 u8 auto_sounding; /* b7: low traffic indicator 1004 * b6: Stop sounding for this entry 1005 * b5 ~ b0: postpone sounding 1006 */ 1007 u8 ibf_timeout; 1008 u8 ibf_dbw; 1009 u8 ibf_ncol; 1010 u8 ibf_nrow; 1011 u8 nrow_bw160; 1012 u8 ncol_bw160; 1013 u8 ru_start_idx; 1014 u8 ru_end_idx; 1015 1016 bool trigger_su; 1017 bool trigger_mu; 1018 bool ng16_su; 1019 bool ng16_mu; 1020 bool codebook42_su; 1021 bool codebook75_mu; 1022 1023 u8 he_ltf; 1024 u8 rsv[3]; 1025 } __packed; 1026 1027 struct sta_rec_bfee { 1028 __le16 tag; 1029 __le16 len; 1030 bool fb_identity_matrix; /* 1: feedback identity matrix */ 1031 bool ignore_feedback; /* 1: ignore */ 1032 u8 rsv[2]; 1033 } __packed; 1034 1035 enum { 1036 STA_REC_BASIC, 1037 STA_REC_RA, 1038 STA_REC_RA_CMM_INFO, 1039 STA_REC_RA_UPDATE, 1040 STA_REC_BF, 1041 STA_REC_AMSDU, 1042 STA_REC_BA, 1043 STA_REC_RED, /* not used */ 1044 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 1045 STA_REC_HT, 1046 STA_REC_VHT, 1047 STA_REC_APPS, 1048 STA_REC_KEY, 1049 STA_REC_WTBL, 1050 STA_REC_HE, 1051 STA_REC_HW_AMSDU, 1052 STA_REC_WTBL_AADOM, 1053 STA_REC_KEY_V2, 1054 STA_REC_MURU, 1055 STA_REC_MUEDCA, 1056 STA_REC_BFEE, 1057 STA_REC_MAX_NUM 1058 }; 1059 1060 enum mcu_cipher_type { 1061 MCU_CIPHER_NONE = 0, 1062 MCU_CIPHER_WEP40, 1063 MCU_CIPHER_WEP104, 1064 MCU_CIPHER_WEP128, 1065 MCU_CIPHER_TKIP, 1066 MCU_CIPHER_AES_CCMP, 1067 MCU_CIPHER_CCMP_256, 1068 MCU_CIPHER_GCMP, 1069 MCU_CIPHER_GCMP_256, 1070 MCU_CIPHER_WAPI, 1071 MCU_CIPHER_BIP_CMAC_128, 1072 }; 1073 1074 enum { 1075 CH_SWITCH_NORMAL = 0, 1076 CH_SWITCH_SCAN = 3, 1077 CH_SWITCH_MCC = 4, 1078 CH_SWITCH_DFS = 5, 1079 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1080 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1081 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1082 CH_SWITCH_SCAN_BYPASS_DPD = 9 1083 }; 1084 1085 enum { 1086 THERMAL_SENSOR_TEMP_QUERY, 1087 THERMAL_SENSOR_MANUAL_CTRL, 1088 THERMAL_SENSOR_INFO_QUERY, 1089 THERMAL_SENSOR_TASK_CTRL, 1090 }; 1091 1092 enum { 1093 THERMAL_PROTECT_PARAMETER_CTRL, 1094 THERMAL_PROTECT_BASIC_INFO, 1095 THERMAL_PROTECT_ENABLE, 1096 THERMAL_PROTECT_DISABLE, 1097 THERMAL_PROTECT_DUTY_CONFIG, 1098 THERMAL_PROTECT_MECH_INFO, 1099 THERMAL_PROTECT_DUTY_INFO, 1100 THERMAL_PROTECT_STATE_ACT, 1101 }; 1102 1103 enum { 1104 MT_BF_SOUNDING_ON = 1, 1105 MT_BF_TYPE_UPDATE = 20, 1106 MT_BF_MODULE_UPDATE = 25 1107 }; 1108 1109 enum { 1110 MURU_SET_ARB_OP_MODE = 14, 1111 MURU_SET_PLATFORM_TYPE = 25, 1112 }; 1113 1114 enum { 1115 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 1116 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 1117 }; 1118 1119 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 1120 sizeof(struct wtbl_generic) + \ 1121 sizeof(struct wtbl_rx) + \ 1122 sizeof(struct wtbl_ht) + \ 1123 sizeof(struct wtbl_vht) + \ 1124 sizeof(struct wtbl_hdr_trans) +\ 1125 sizeof(struct wtbl_ba) + \ 1126 sizeof(struct wtbl_smps)) 1127 1128 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1129 sizeof(struct sta_rec_basic) + \ 1130 sizeof(struct sta_rec_bf) + \ 1131 sizeof(struct sta_rec_ht) + \ 1132 sizeof(struct sta_rec_he) + \ 1133 sizeof(struct sta_rec_ba) + \ 1134 sizeof(struct sta_rec_vht) + \ 1135 sizeof(struct sta_rec_uapsd) + \ 1136 sizeof(struct sta_rec_amsdu) + \ 1137 sizeof(struct sta_rec_muru) + \ 1138 sizeof(struct sta_rec_bfee) + \ 1139 sizeof(struct tlv) + \ 1140 MT7915_WTBL_UPDATE_MAX_SIZE) 1141 1142 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1143 sizeof(struct bss_info_omac) + \ 1144 sizeof(struct bss_info_basic) +\ 1145 sizeof(struct bss_info_rf_ch) +\ 1146 sizeof(struct bss_info_ra) + \ 1147 sizeof(struct bss_info_hw_amsdu) +\ 1148 sizeof(struct bss_info_he) + \ 1149 sizeof(struct bss_info_bmc_rate) +\ 1150 sizeof(struct bss_info_ext_bss)) 1151 1152 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 1153 sizeof(struct bss_info_bcn_cntdwn) + \ 1154 sizeof(struct bss_info_bcn_mbss) + \ 1155 sizeof(struct bss_info_bcn_cont)) 1156 1157 #define PHY_MODE_A BIT(0) 1158 #define PHY_MODE_B BIT(1) 1159 #define PHY_MODE_G BIT(2) 1160 #define PHY_MODE_GN BIT(3) 1161 #define PHY_MODE_AN BIT(4) 1162 #define PHY_MODE_AC BIT(5) 1163 #define PHY_MODE_AX_24G BIT(6) 1164 #define PHY_MODE_AX_5G BIT(7) 1165 #define PHY_MODE_AX_6G BIT(8) 1166 1167 #define MODE_CCK BIT(0) 1168 #define MODE_OFDM BIT(1) 1169 #define MODE_HT BIT(2) 1170 #define MODE_VHT BIT(3) 1171 #define MODE_HE BIT(4) 1172 1173 #define STA_CAP_WMM BIT(0) 1174 #define STA_CAP_SGI_20 BIT(4) 1175 #define STA_CAP_SGI_40 BIT(5) 1176 #define STA_CAP_TX_STBC BIT(6) 1177 #define STA_CAP_RX_STBC BIT(7) 1178 #define STA_CAP_VHT_SGI_80 BIT(16) 1179 #define STA_CAP_VHT_SGI_160 BIT(17) 1180 #define STA_CAP_VHT_TX_STBC BIT(18) 1181 #define STA_CAP_VHT_RX_STBC BIT(19) 1182 #define STA_CAP_VHT_LDPC BIT(23) 1183 #define STA_CAP_LDPC BIT(24) 1184 #define STA_CAP_HT BIT(26) 1185 #define STA_CAP_VHT BIT(27) 1186 #define STA_CAP_HE BIT(28) 1187 1188 /* HE MAC */ 1189 #define STA_REC_HE_CAP_HTC BIT(0) 1190 #define STA_REC_HE_CAP_BQR BIT(1) 1191 #define STA_REC_HE_CAP_BSR BIT(2) 1192 #define STA_REC_HE_CAP_OM BIT(3) 1193 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 1194 /* HE PHY */ 1195 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 1196 #define STA_REC_HE_CAP_LDPC BIT(6) 1197 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 1198 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 1199 /* STBC */ 1200 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 1201 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 1202 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 1203 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 1204 /* GI */ 1205 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 1206 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 1207 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 1208 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 1209 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 1210 /* 242 TONE */ 1211 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 1212 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 1213 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 1214 1215 #endif 1216