1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 struct mt7915_mcu_txd { 10 __le32 txd[8]; 11 12 __le16 len; 13 __le16 pq_id; 14 15 u8 cid; 16 u8 pkt_type; 17 u8 set_query; /* FW don't care */ 18 u8 seq; 19 20 u8 uc_d2b0_rev; 21 u8 ext_cid; 22 u8 s2d_index; 23 u8 ext_cid_ack; 24 25 u32 reserved[5]; 26 } __packed __aligned(4); 27 28 enum { 29 MCU_ATE_SET_TRX = 0x1, 30 MCU_ATE_SET_FREQ_OFFSET = 0xa, 31 MCU_ATE_SET_SLOT_TIME = 0x13, 32 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 33 }; 34 35 struct mt7915_mcu_rxd { 36 __le32 rxd[6]; 37 38 __le16 len; 39 __le16 pkt_type_id; 40 41 u8 eid; 42 u8 seq; 43 __le16 __rsv; 44 45 u8 ext_eid; 46 u8 __rsv1[2]; 47 u8 s2d_index; 48 }; 49 50 struct mt7915_mcu_thermal_ctrl { 51 u8 ctrl_id; 52 u8 band_idx; 53 union { 54 struct { 55 u8 protect_type; /* 1: duty admit, 2: radio off */ 56 u8 trigger_type; /* 0: low, 1: high */ 57 } __packed type; 58 struct { 59 u8 duty_level; /* level 0~3 */ 60 u8 duty_cycle; 61 } __packed duty; 62 }; 63 } __packed; 64 65 struct mt7915_mcu_thermal_notify { 66 struct mt7915_mcu_rxd rxd; 67 68 struct mt7915_mcu_thermal_ctrl ctrl; 69 __le32 temperature; 70 u8 rsv[8]; 71 } __packed; 72 73 struct mt7915_mcu_csa_notify { 74 struct mt7915_mcu_rxd rxd; 75 76 u8 omac_idx; 77 u8 csa_count; 78 u8 band_idx; 79 u8 rsv; 80 } __packed; 81 82 struct mt7915_mcu_rdd_report { 83 struct mt7915_mcu_rxd rxd; 84 85 u8 band_idx; 86 u8 long_detected; 87 u8 constant_prf_detected; 88 u8 staggered_prf_detected; 89 u8 radar_type_idx; 90 u8 periodic_pulse_num; 91 u8 long_pulse_num; 92 u8 hw_pulse_num; 93 94 u8 out_lpn; 95 u8 out_spn; 96 u8 out_crpn; 97 u8 out_crpw; 98 u8 out_crbn; 99 u8 out_stgpn; 100 u8 out_stgpw; 101 102 u8 rsv; 103 104 __le32 out_pri_const; 105 __le32 out_pri_stg[3]; 106 107 struct { 108 __le32 start; 109 __le16 pulse_width; 110 __le16 pulse_power; 111 u8 mdrdy_flag; 112 u8 rsv[3]; 113 } long_pulse[32]; 114 115 struct { 116 __le32 start; 117 __le16 pulse_width; 118 __le16 pulse_power; 119 u8 mdrdy_flag; 120 u8 rsv[3]; 121 } periodic_pulse[32]; 122 123 struct { 124 __le32 start; 125 __le16 pulse_width; 126 __le16 pulse_power; 127 u8 sc_pass; 128 u8 sw_reset; 129 u8 mdrdy_flag; 130 u8 tx_active; 131 } hw_pulse[32]; 132 } __packed; 133 134 struct mt7915_mcu_eeprom { 135 u8 buffer_mode; 136 u8 format; 137 __le16 len; 138 } __packed; 139 140 struct mt7915_mcu_eeprom_info { 141 __le32 addr; 142 __le32 valid; 143 u8 data[16]; 144 } __packed; 145 146 struct mt7915_mcu_phy_rx_info { 147 u8 category; 148 u8 rate; 149 u8 mode; 150 u8 nsts; 151 u8 gi; 152 u8 coding; 153 u8 stbc; 154 u8 bw; 155 }; 156 157 struct mt7915_mcu_mib { 158 __le32 band; 159 __le32 offs; 160 __le64 data; 161 } __packed; 162 163 enum mt7915_chan_mib_offs { 164 MIB_BUSY_TIME = 14, 165 MIB_TX_TIME = 81, 166 MIB_RX_TIME, 167 MIB_OBSS_AIRTIME = 86 168 }; 169 170 struct edca { 171 u8 queue; 172 u8 set; 173 u8 aifs; 174 u8 cw_min; 175 __le16 cw_max; 176 __le16 txop; 177 }; 178 179 struct mt7915_mcu_tx { 180 u8 total; 181 u8 action; 182 u8 valid; 183 u8 mode; 184 185 struct edca edca[IEEE80211_NUM_ACS]; 186 } __packed; 187 188 struct mt7915_mcu_muru_stats { 189 __le32 event_id; 190 struct { 191 __le32 cck_cnt; 192 __le32 ofdm_cnt; 193 __le32 htmix_cnt; 194 __le32 htgf_cnt; 195 __le32 vht_su_cnt; 196 __le32 vht_2mu_cnt; 197 __le32 vht_3mu_cnt; 198 __le32 vht_4mu_cnt; 199 __le32 he_su_cnt; 200 __le32 he_ext_su_cnt; 201 __le32 he_2ru_cnt; 202 __le32 he_2mu_cnt; 203 __le32 he_3ru_cnt; 204 __le32 he_3mu_cnt; 205 __le32 he_4ru_cnt; 206 __le32 he_4mu_cnt; 207 __le32 he_5to8ru_cnt; 208 __le32 he_9to16ru_cnt; 209 __le32 he_gtr16ru_cnt; 210 } dl; 211 212 struct { 213 __le32 hetrig_su_cnt; 214 __le32 hetrig_2ru_cnt; 215 __le32 hetrig_3ru_cnt; 216 __le32 hetrig_4ru_cnt; 217 __le32 hetrig_5to8ru_cnt; 218 __le32 hetrig_9to16ru_cnt; 219 __le32 hetrig_gtr16ru_cnt; 220 __le32 hetrig_2mu_cnt; 221 __le32 hetrig_3mu_cnt; 222 __le32 hetrig_4mu_cnt; 223 } ul; 224 }; 225 226 #define WMM_AIFS_SET BIT(0) 227 #define WMM_CW_MIN_SET BIT(1) 228 #define WMM_CW_MAX_SET BIT(2) 229 #define WMM_TXOP_SET BIT(3) 230 #define WMM_PARAM_SET GENMASK(3, 0) 231 232 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 233 #define MCU_PKT_ID 0xa0 234 235 enum { 236 MCU_FW_LOG_WM, 237 MCU_FW_LOG_WA, 238 MCU_FW_LOG_TO_HOST, 239 }; 240 241 enum { 242 MCU_TWT_AGRT_ADD, 243 MCU_TWT_AGRT_MODIFY, 244 MCU_TWT_AGRT_DELETE, 245 MCU_TWT_AGRT_TEARDOWN, 246 MCU_TWT_AGRT_GET_TSF, 247 }; 248 249 enum { 250 MCU_WA_PARAM_CMD_QUERY, 251 MCU_WA_PARAM_CMD_SET, 252 MCU_WA_PARAM_CMD_CAPABILITY, 253 MCU_WA_PARAM_CMD_DEBUG, 254 }; 255 256 enum { 257 MCU_WA_PARAM_PDMA_RX = 0x04, 258 MCU_WA_PARAM_CPU_UTIL = 0x0b, 259 MCU_WA_PARAM_RED = 0x0e, 260 }; 261 262 enum mcu_mmps_mode { 263 MCU_MMPS_STATIC, 264 MCU_MMPS_DYNAMIC, 265 MCU_MMPS_RSV, 266 MCU_MMPS_DISABLE, 267 }; 268 269 #define STA_TYPE_STA BIT(0) 270 #define STA_TYPE_AP BIT(1) 271 #define STA_TYPE_ADHOC BIT(2) 272 #define STA_TYPE_WDS BIT(4) 273 #define STA_TYPE_BC BIT(5) 274 275 #define NETWORK_INFRA BIT(16) 276 #define NETWORK_P2P BIT(17) 277 #define NETWORK_IBSS BIT(18) 278 #define NETWORK_WDS BIT(21) 279 280 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 281 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 282 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 283 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 284 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 285 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 286 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 287 288 #define CONN_STATE_DISCONNECT 0 289 #define CONN_STATE_CONNECT 1 290 #define CONN_STATE_PORT_SECURE 2 291 292 enum { 293 SCS_SEND_DATA, 294 SCS_SET_MANUAL_PD_TH, 295 SCS_CONFIG, 296 SCS_ENABLE, 297 SCS_SHOW_INFO, 298 SCS_GET_GLO_ADDR, 299 SCS_GET_GLO_ADDR_EVENT, 300 }; 301 302 struct bss_info_bmc_rate { 303 __le16 tag; 304 __le16 len; 305 __le16 bc_trans; 306 __le16 mc_trans; 307 u8 short_preamble; 308 u8 rsv[7]; 309 } __packed; 310 311 struct bss_info_ra { 312 __le16 tag; 313 __le16 len; 314 u8 op_mode; 315 u8 adhoc_en; 316 u8 short_preamble; 317 u8 tx_streams; 318 u8 rx_streams; 319 u8 algo; 320 u8 force_sgi; 321 u8 force_gf; 322 u8 ht_mode; 323 u8 has_20_sta; /* Check if any sta support GF. */ 324 u8 bss_width_trigger_events; 325 u8 vht_nss_cap; 326 u8 vht_bw_signal; /* not use */ 327 u8 vht_force_sgi; /* not use */ 328 u8 se_off; 329 u8 antenna_idx; 330 u8 train_up_rule; 331 u8 rsv[3]; 332 unsigned short train_up_high_thres; 333 short train_up_rule_rssi; 334 unsigned short low_traffic_thres; 335 __le16 max_phyrate; 336 __le32 phy_cap; 337 __le32 interval; 338 __le32 fast_interval; 339 } __packed; 340 341 struct bss_info_hw_amsdu { 342 __le16 tag; 343 __le16 len; 344 __le32 cmp_bitmap_0; 345 __le32 cmp_bitmap_1; 346 __le16 trig_thres; 347 u8 enable; 348 u8 rsv; 349 } __packed; 350 351 struct bss_info_color { 352 __le16 tag; 353 __le16 len; 354 u8 disable; 355 u8 color; 356 u8 rsv[2]; 357 } __packed; 358 359 struct bss_info_he { 360 __le16 tag; 361 __le16 len; 362 u8 he_pe_duration; 363 u8 vht_op_info_present; 364 __le16 he_rts_thres; 365 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 366 u8 rsv[6]; 367 } __packed; 368 369 struct bss_info_bcn { 370 __le16 tag; 371 __le16 len; 372 u8 ver; 373 u8 enable; 374 __le16 sub_ntlv; 375 } __packed __aligned(4); 376 377 struct bss_info_bcn_cntdwn { 378 __le16 tag; 379 __le16 len; 380 u8 cnt; 381 u8 rsv[3]; 382 } __packed __aligned(4); 383 384 struct bss_info_bcn_mbss { 385 #define MAX_BEACON_NUM 32 386 __le16 tag; 387 __le16 len; 388 __le32 bitmap; 389 __le16 offset[MAX_BEACON_NUM]; 390 u8 rsv[8]; 391 } __packed __aligned(4); 392 393 struct bss_info_bcn_cont { 394 __le16 tag; 395 __le16 len; 396 __le16 tim_ofs; 397 __le16 csa_ofs; 398 __le16 bcc_ofs; 399 __le16 pkt_len; 400 } __packed __aligned(4); 401 402 enum { 403 BSS_INFO_BCN_CSA, 404 BSS_INFO_BCN_BCC, 405 BSS_INFO_BCN_MBSSID, 406 BSS_INFO_BCN_CONTENT, 407 BSS_INFO_BCN_MAX 408 }; 409 410 enum { 411 RATE_PARAM_FIXED = 3, 412 RATE_PARAM_MMPS_UPDATE = 5, 413 RATE_PARAM_FIXED_HE_LTF = 7, 414 RATE_PARAM_FIXED_MCS, 415 RATE_PARAM_FIXED_GI = 11, 416 RATE_PARAM_AUTO = 20, 417 }; 418 419 #define RATE_CFG_MCS GENMASK(3, 0) 420 #define RATE_CFG_NSS GENMASK(7, 4) 421 #define RATE_CFG_GI GENMASK(11, 8) 422 #define RATE_CFG_BW GENMASK(15, 12) 423 #define RATE_CFG_STBC GENMASK(19, 16) 424 #define RATE_CFG_LDPC GENMASK(23, 20) 425 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 426 #define RATE_CFG_HE_LTF GENMASK(31, 28) 427 428 enum { 429 THERMAL_PROTECT_PARAMETER_CTRL, 430 THERMAL_PROTECT_BASIC_INFO, 431 THERMAL_PROTECT_ENABLE, 432 THERMAL_PROTECT_DISABLE, 433 THERMAL_PROTECT_DUTY_CONFIG, 434 THERMAL_PROTECT_MECH_INFO, 435 THERMAL_PROTECT_DUTY_INFO, 436 THERMAL_PROTECT_STATE_ACT, 437 }; 438 439 enum { 440 MT_BF_SOUNDING_ON = 1, 441 MT_BF_TYPE_UPDATE = 20, 442 MT_BF_MODULE_UPDATE = 25 443 }; 444 445 enum { 446 MURU_SET_ARB_OP_MODE = 14, 447 MURU_SET_PLATFORM_TYPE = 25, 448 }; 449 450 enum { 451 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 452 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 453 }; 454 455 /* tx cmd tx statistics */ 456 enum { 457 MURU_SET_TXC_TX_STATS_EN = 150, 458 MURU_GET_TXC_TX_STATS = 151, 459 }; 460 461 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 462 sizeof(struct bss_info_omac) + \ 463 sizeof(struct bss_info_basic) +\ 464 sizeof(struct bss_info_rf_ch) +\ 465 sizeof(struct bss_info_ra) + \ 466 sizeof(struct bss_info_hw_amsdu) +\ 467 sizeof(struct bss_info_he) + \ 468 sizeof(struct bss_info_bmc_rate) +\ 469 sizeof(struct bss_info_ext_bss)) 470 471 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 472 sizeof(struct bss_info_bcn_cntdwn) + \ 473 sizeof(struct bss_info_bcn_mbss) + \ 474 sizeof(struct bss_info_bcn_cont)) 475 476 #endif 477