1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 struct mt7915_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /* event table */ 27 enum { 28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 29 MCU_EVENT_FW_START = 0x01, 30 MCU_EVENT_GENERIC = 0x01, 31 MCU_EVENT_ACCESS_REG = 0x02, 32 MCU_EVENT_MT_PATCH_SEM = 0x04, 33 MCU_EVENT_CH_PRIVILEGE = 0x18, 34 MCU_EVENT_EXT = 0xed, 35 MCU_EVENT_RESTART_DL = 0xef, 36 }; 37 38 /* ext event table */ 39 enum { 40 MCU_EXT_EVENT_PS_SYNC = 0x5, 41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 44 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 46 MCU_EXT_EVENT_RATE_REPORT = 0x87, 47 }; 48 49 struct mt7915_mcu_rxd { 50 __le32 rxd[6]; 51 52 __le16 len; 53 __le16 pkt_type_id; 54 55 u8 eid; 56 u8 seq; 57 __le16 __rsv; 58 59 u8 ext_eid; 60 u8 __rsv1[2]; 61 u8 s2d_index; 62 }; 63 64 struct mt7915_mcu_rdd_report { 65 struct mt7915_mcu_rxd rxd; 66 67 u8 idx; 68 u8 long_detected; 69 u8 constant_prf_detected; 70 u8 staggered_prf_detected; 71 u8 radar_type_idx; 72 u8 periodic_pulse_num; 73 u8 long_pulse_num; 74 u8 hw_pulse_num; 75 76 u8 out_lpn; 77 u8 out_spn; 78 u8 out_crpn; 79 u8 out_crpw; 80 u8 out_crbn; 81 u8 out_stgpn; 82 u8 out_stgpw; 83 84 u8 rsv; 85 86 __le32 out_pri_const; 87 __le32 out_pri_stg[3]; 88 89 struct { 90 __le32 start; 91 __le16 pulse_width; 92 __le16 pulse_power; 93 u8 mdrdy_flag; 94 u8 rsv[3]; 95 } long_pulse[32]; 96 97 struct { 98 __le32 start; 99 __le16 pulse_width; 100 __le16 pulse_power; 101 u8 mdrdy_flag; 102 u8 rsv[3]; 103 } periodic_pulse[32]; 104 105 struct { 106 __le32 start; 107 __le16 pulse_width; 108 __le16 pulse_power; 109 u8 sc_pass; 110 u8 sw_reset; 111 u8 mdrdy_flag; 112 u8 tx_active; 113 } hw_pulse[32]; 114 } __packed; 115 116 struct mt7915_mcu_eeprom_info { 117 __le32 addr; 118 __le32 valid; 119 u8 data[16]; 120 } __packed; 121 122 struct mt7915_mcu_ra_info { 123 struct mt7915_mcu_rxd rxd; 124 125 __le32 event_id; 126 __le16 wlan_idx; 127 __le16 ru_idx; 128 __le16 direction; 129 __le16 dump_group; 130 131 __le32 suggest_rate; 132 __le32 min_rate; /* for dynamic sounding */ 133 __le32 max_rate; /* for dynamic sounding */ 134 __le32 init_rate_down_rate; 135 136 __le16 curr_rate; 137 __le16 init_rate_down_total; 138 __le16 init_rate_down_succ; 139 __le16 success; 140 __le16 attempts; 141 142 __le16 prev_rate; 143 __le16 prob_up_rate; 144 u8 no_rate_up_cnt; 145 u8 ppdu_cnt; 146 u8 gi; 147 148 u8 try_up_fail; 149 u8 try_up_total; 150 u8 suggest_wf; 151 u8 try_up_check; 152 u8 prob_up_period; 153 u8 prob_down_pending; 154 } __packed; 155 156 #define MT_RA_RATE_NSS GENMASK(8, 6) 157 #define MT_RA_RATE_MCS GENMASK(3, 0) 158 #define MT_RA_RATE_TX_MODE GENMASK(12, 9) 159 #define MT_RA_RATE_DCM_EN BIT(4) 160 #define MT_RA_RATE_BW GENMASK(14, 13) 161 162 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 163 #define MCU_PKT_ID 0xa0 164 165 enum { 166 MCU_Q_QUERY, 167 MCU_Q_SET, 168 MCU_Q_RESERVED, 169 MCU_Q_NA 170 }; 171 172 enum { 173 MCU_S2D_H2N, 174 MCU_S2D_C2N, 175 MCU_S2D_H2C, 176 MCU_S2D_H2CN 177 }; 178 179 enum { 180 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 181 MCU_CMD_FW_START_REQ = 0x02, 182 MCU_CMD_INIT_ACCESS_REG = 0x3, 183 MCU_CMD_NIC_POWER_CTRL = 0x4, 184 MCU_CMD_PATCH_START_REQ = 0x05, 185 MCU_CMD_PATCH_FINISH_REQ = 0x07, 186 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 187 MCU_CMD_EXT_CID = 0xED, 188 MCU_CMD_FW_SCATTER = 0xEE, 189 MCU_CMD_RESTART_DL_REQ = 0xEF, 190 }; 191 192 enum { 193 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 194 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 195 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 196 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 197 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 198 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 199 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 200 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 201 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 202 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 203 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 204 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 205 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 206 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 207 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 208 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 209 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 210 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 211 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 212 MCU_EXT_CMD_SCS_CTRL = 0x82, 213 MCU_EXT_CMD_RATE_CTRL = 0x87, 214 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 215 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 216 MCU_EXT_CMD_SET_SPR = 0xa8, 217 }; 218 219 enum { 220 PATCH_SEM_RELEASE, 221 PATCH_SEM_GET 222 }; 223 224 enum { 225 PATCH_NOT_DL_SEM_FAIL, 226 PATCH_IS_DL, 227 PATCH_NOT_DL_SEM_SUCCESS, 228 PATCH_REL_SEM_SUCCESS 229 }; 230 231 enum { 232 FW_STATE_INITIAL, 233 FW_STATE_FW_DOWNLOAD, 234 FW_STATE_NORMAL_OPERATION, 235 FW_STATE_NORMAL_TRX, 236 FW_STATE_WACPU_RDY = 7 237 }; 238 239 enum { 240 EE_MODE_EFUSE, 241 EE_MODE_BUFFER, 242 }; 243 244 enum { 245 EE_FORMAT_BIN, 246 EE_FORMAT_WHOLE, 247 EE_FORMAT_MULTIPLE, 248 }; 249 250 #define STA_TYPE_STA BIT(0) 251 #define STA_TYPE_AP BIT(1) 252 #define STA_TYPE_ADHOC BIT(2) 253 #define STA_TYPE_WDS BIT(4) 254 #define STA_TYPE_BC BIT(5) 255 256 #define NETWORK_INFRA BIT(16) 257 #define NETWORK_P2P BIT(17) 258 #define NETWORK_IBSS BIT(18) 259 #define NETWORK_WDS BIT(21) 260 261 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 262 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 263 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 264 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 265 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 266 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 267 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 268 269 #define CONN_STATE_DISCONNECT 0 270 #define CONN_STATE_CONNECT 1 271 #define CONN_STATE_PORT_SECURE 2 272 273 enum { 274 DEV_INFO_ACTIVE, 275 DEV_INFO_MAX_NUM 276 }; 277 278 enum { 279 SCS_SEND_DATA, 280 SCS_SET_MANUAL_PD_TH, 281 SCS_CONFIG, 282 SCS_ENABLE, 283 SCS_SHOW_INFO, 284 SCS_GET_GLO_ADDR, 285 SCS_GET_GLO_ADDR_EVENT, 286 }; 287 288 enum { 289 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 290 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 291 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 292 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 293 CMD_CBW_10MHZ, 294 CMD_CBW_5MHZ, 295 CMD_CBW_8080MHZ, 296 297 CMD_HE_MCS_BW80 = 0, 298 CMD_HE_MCS_BW160, 299 CMD_HE_MCS_BW8080, 300 CMD_HE_MCS_BW_NUM 301 }; 302 303 struct tlv { 304 __le16 tag; 305 __le16 len; 306 } __packed; 307 308 struct bss_info_omac { 309 __le16 tag; 310 __le16 len; 311 u8 hw_bss_idx; 312 u8 omac_idx; 313 u8 band_idx; 314 u8 rsv0; 315 __le32 conn_type; 316 u32 rsv1; 317 } __packed; 318 319 struct bss_info_basic { 320 __le16 tag; 321 __le16 len; 322 __le32 network_type; 323 u8 active; 324 u8 rsv0; 325 __le16 bcn_interval; 326 u8 bssid[ETH_ALEN]; 327 u8 wmm_idx; 328 u8 dtim_period; 329 u8 bmc_wcid_lo; 330 u8 cipher; 331 u8 phy_mode; 332 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 333 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 334 u8 bmc_wcid_hi; /* high Byte and version */ 335 u8 rsv[2]; 336 } __packed; 337 338 struct bss_info_rf_ch { 339 __le16 tag; 340 __le16 len; 341 u8 pri_ch; 342 u8 center_ch0; 343 u8 center_ch1; 344 u8 bw; 345 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 346 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 347 u8 rsv[2]; 348 } __packed; 349 350 struct bss_info_ext_bss { 351 __le16 tag; 352 __le16 len; 353 __le32 mbss_tsf_offset; /* in unit of us */ 354 u8 rsv[8]; 355 } __packed; 356 357 struct bss_info_sync_mode { 358 __le16 tag; 359 __le16 len; 360 __le16 bcn_interval; 361 u8 enable; 362 u8 dtim_period; 363 u8 rsv[8]; 364 } __packed; 365 366 struct bss_info_bmc_rate { 367 __le16 tag; 368 __le16 len; 369 __le16 bc_trans; 370 __le16 mc_trans; 371 u8 short_preamble; 372 u8 rsv[7]; 373 } __packed; 374 375 struct bss_info_ra { 376 __le16 tag; 377 __le16 len; 378 u8 op_mode; 379 u8 adhoc_en; 380 u8 short_preamble; 381 u8 tx_streams; 382 u8 rx_streams; 383 u8 algo; 384 u8 force_sgi; 385 u8 force_gf; 386 u8 ht_mode; 387 u8 has_20_sta; /* Check if any sta support GF. */ 388 u8 bss_width_trigger_events; 389 u8 vht_nss_cap; 390 u8 vht_bw_signal; /* not use */ 391 u8 vht_force_sgi; /* not use */ 392 u8 se_off; 393 u8 antenna_idx; 394 u8 train_up_rule; 395 u8 rsv[3]; 396 unsigned short train_up_high_thres; 397 short train_up_rule_rssi; 398 unsigned short low_traffic_thres; 399 __le16 max_phyrate; 400 __le32 phy_cap; 401 __le32 interval; 402 __le32 fast_interval; 403 } __packed; 404 405 struct bss_info_he { 406 __le16 tag; 407 __le16 len; 408 u8 he_pe_duration; 409 u8 vht_op_info_present; 410 __le16 he_rts_thres; 411 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 412 u8 rsv[6]; 413 } __packed; 414 415 struct bss_info_bcn { 416 __le16 tag; 417 __le16 len; 418 u8 ver; 419 u8 enable; 420 __le16 sub_ntlv; 421 } __packed __aligned(4); 422 423 struct bss_info_bcn_csa { 424 __le16 tag; 425 __le16 len; 426 u8 cnt; 427 u8 rsv[3]; 428 } __packed __aligned(4); 429 430 struct bss_info_bcn_bcc { 431 __le16 tag; 432 __le16 len; 433 u8 cnt; 434 u8 rsv[3]; 435 } __packed __aligned(4); 436 437 struct bss_info_bcn_mbss { 438 #define MAX_BEACON_NUM 32 439 __le16 tag; 440 __le16 len; 441 __le32 bitmap; 442 __le16 offset[MAX_BEACON_NUM]; 443 u8 rsv[8]; 444 } __packed __aligned(4); 445 446 struct bss_info_bcn_cont { 447 __le16 tag; 448 __le16 len; 449 __le16 tim_ofs; 450 __le16 csa_ofs; 451 __le16 bcc_ofs; 452 __le16 pkt_len; 453 } __packed __aligned(4); 454 455 enum { 456 BSS_INFO_BCN_CSA, 457 BSS_INFO_BCN_BCC, 458 BSS_INFO_BCN_MBSSID, 459 BSS_INFO_BCN_CONTENT, 460 BSS_INFO_BCN_MAX 461 }; 462 463 enum { 464 BSS_INFO_OMAC, 465 BSS_INFO_BASIC, 466 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 467 BSS_INFO_PM, /* sta only */ 468 BSS_INFO_UAPSD, /* sta only */ 469 BSS_INFO_ROAM_DETECT, /* obsoleted */ 470 BSS_INFO_LQ_RM, /* obsoleted */ 471 BSS_INFO_EXT_BSS, 472 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 473 BSS_INFO_SYNC_MODE, 474 BSS_INFO_RA, 475 BSS_INFO_HW_AMSDU, 476 BSS_INFO_BSS_COLOR, 477 BSS_INFO_HE_BASIC, 478 BSS_INFO_PROTECT_INFO, 479 BSS_INFO_OFFLOAD, 480 BSS_INFO_11V_MBSSID, 481 BSS_INFO_MAX_NUM 482 }; 483 484 enum { 485 WTBL_RESET_AND_SET = 1, 486 WTBL_SET, 487 WTBL_QUERY, 488 WTBL_RESET_ALL 489 }; 490 491 struct wtbl_req_hdr { 492 u8 wlan_idx_lo; 493 u8 operation; 494 __le16 tlv_num; 495 u8 wlan_idx_hi; 496 u8 rsv[3]; 497 } __packed; 498 499 struct wtbl_generic { 500 __le16 tag; 501 __le16 len; 502 u8 peer_addr[ETH_ALEN]; 503 u8 muar_idx; 504 u8 skip_tx; 505 u8 cf_ack; 506 u8 qos; 507 u8 mesh; 508 u8 adm; 509 __le16 partial_aid; 510 u8 baf_en; 511 u8 aad_om; 512 } __packed; 513 514 struct wtbl_rx { 515 __le16 tag; 516 __le16 len; 517 u8 rcid; 518 u8 rca1; 519 u8 rca2; 520 u8 rv; 521 u8 rsv[4]; 522 } __packed; 523 524 struct wtbl_ht { 525 __le16 tag; 526 __le16 len; 527 u8 ht; 528 u8 ldpc; 529 u8 af; 530 u8 mm; 531 u8 rsv[4]; 532 } __packed; 533 534 struct wtbl_vht { 535 __le16 tag; 536 __le16 len; 537 u8 ldpc; 538 u8 dyn_bw; 539 u8 vht; 540 u8 txop_ps; 541 u8 rsv[4]; 542 } __packed; 543 544 enum { 545 MT_BA_TYPE_INVALID, 546 MT_BA_TYPE_ORIGINATOR, 547 MT_BA_TYPE_RECIPIENT 548 }; 549 550 enum { 551 RST_BA_MAC_TID_MATCH, 552 RST_BA_MAC_MATCH, 553 RST_BA_NO_MATCH 554 }; 555 556 struct wtbl_ba { 557 __le16 tag; 558 __le16 len; 559 /* common */ 560 u8 tid; 561 u8 ba_type; 562 u8 rsv0[2]; 563 /* originator only */ 564 __le16 sn; 565 u8 ba_en; 566 u8 ba_winsize_idx; 567 __le16 ba_winsize; 568 /* recipient only */ 569 u8 peer_addr[ETH_ALEN]; 570 u8 rst_ba_tid; 571 u8 rst_ba_sel; 572 u8 rst_ba_sb; 573 u8 band_idx; 574 u8 rsv1[4]; 575 } __packed; 576 577 struct wtbl_smps { 578 __le16 tag; 579 __le16 len; 580 u8 smps; 581 u8 rsv[3]; 582 } __packed; 583 584 enum { 585 WTBL_GENERIC, 586 WTBL_RX, 587 WTBL_HT, 588 WTBL_VHT, 589 WTBL_PEER_PS, /* not used */ 590 WTBL_TX_PS, 591 WTBL_HDR_TRANS, 592 WTBL_SEC_KEY, 593 WTBL_BA, 594 WTBL_RDG, /* obsoleted */ 595 WTBL_PROTECT, /* not used */ 596 WTBL_CLEAR, /* not used */ 597 WTBL_BF, 598 WTBL_SMPS, 599 WTBL_RAW_DATA, /* debug only */ 600 WTBL_PN, 601 WTBL_SPE, 602 WTBL_MAX_NUM 603 }; 604 605 struct sta_ntlv_hdr { 606 u8 rsv[2]; 607 __le16 tlv_num; 608 } __packed; 609 610 struct sta_req_hdr { 611 u8 bss_idx; 612 u8 wlan_idx_lo; 613 __le16 tlv_num; 614 u8 is_tlv_append; 615 u8 muar_idx; 616 u8 wlan_idx_hi; 617 u8 rsv; 618 } __packed; 619 620 struct sta_rec_basic { 621 __le16 tag; 622 __le16 len; 623 __le32 conn_type; 624 u8 conn_state; 625 u8 qos; 626 __le16 aid; 627 u8 peer_addr[ETH_ALEN]; 628 __le16 extra_info; 629 } __packed; 630 631 struct sta_rec_ht { 632 __le16 tag; 633 __le16 len; 634 __le16 ht_cap; 635 u16 rsv; 636 } __packed; 637 638 struct sta_rec_vht { 639 __le16 tag; 640 __le16 len; 641 __le32 vht_cap; 642 __le16 vht_rx_mcs_map; 643 __le16 vht_tx_mcs_map; 644 u8 rts_bw_sig; 645 u8 rsv[3]; 646 } __packed; 647 648 struct sta_rec_muru { 649 __le16 tag; 650 __le16 len; 651 652 struct { 653 bool ofdma_dl_en; 654 bool ofdma_ul_en; 655 bool mimo_dl_en; 656 bool mimo_ul_en; 657 u8 rsv[4]; 658 } cfg; 659 660 struct { 661 u8 punc_pream_rx; 662 bool he_20m_in_40m_2g; 663 bool he_20m_in_160m; 664 bool he_80m_in_160m; 665 bool lt16_sigb; 666 bool rx_su_comp_sigb; 667 bool rx_su_non_comp_sigb; 668 u8 rsv; 669 } ofdma_dl; 670 671 struct { 672 u8 t_frame_dur; 673 u8 mu_cascading; 674 u8 uo_ra; 675 u8 he_2x996_tone; 676 u8 rx_t_frame_11ac; 677 u8 rsv[3]; 678 } ofdma_ul; 679 680 struct { 681 bool vht_mu_bfee; 682 bool partial_bw_dl_mimo; 683 u8 rsv[2]; 684 } mimo_dl; 685 686 struct { 687 bool full_ul_mimo; 688 bool partial_ul_mimo; 689 u8 rsv[2]; 690 } mimo_ul; 691 } __packed; 692 693 struct sta_rec_he { 694 __le16 tag; 695 __le16 len; 696 697 __le32 he_cap; 698 699 u8 t_frame_dur; 700 u8 max_ampdu_exp; 701 u8 bw_set; 702 u8 device_class; 703 u8 dcm_tx_mode; 704 u8 dcm_tx_max_nss; 705 u8 dcm_rx_mode; 706 u8 dcm_rx_max_nss; 707 u8 dcm_max_ru; 708 u8 punc_pream_rx; 709 u8 pkt_ext; 710 u8 rsv1; 711 712 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 713 714 u8 rsv2[2]; 715 } __packed; 716 717 struct sta_rec_ba { 718 __le16 tag; 719 __le16 len; 720 u8 tid; 721 u8 ba_type; 722 u8 amsdu; 723 u8 ba_en; 724 __le16 ssn; 725 __le16 winsize; 726 } __packed; 727 728 struct sec_key { 729 u8 cipher_id; 730 u8 cipher_len; 731 u8 key_id; 732 u8 key_len; 733 u8 key[32]; 734 } __packed; 735 736 struct sta_rec_sec { 737 __le16 tag; 738 __le16 len; 739 u8 add; 740 u8 n_cipher; 741 u8 rsv[2]; 742 743 struct sec_key key[2]; 744 } __packed; 745 746 struct ra_phy { 747 u8 type; 748 u8 flag; 749 u8 stbc; 750 u8 sgi; 751 u8 bw; 752 u8 ldpc; 753 u8 mcs; 754 u8 nss; 755 u8 he_ltf; 756 }; 757 758 struct sta_rec_ra { 759 __le16 tag; 760 __le16 len; 761 762 u8 valid; 763 u8 auto_rate; 764 u8 phy_mode; 765 u8 channel; 766 u8 bw; 767 u8 disable_cck; 768 u8 ht_mcs32; 769 u8 ht_gf; 770 u8 ht_mcs[4]; 771 u8 mmps_mode; 772 u8 gband_256; 773 u8 af; 774 u8 auth_wapi_mode; 775 u8 rate_len; 776 777 u8 supp_mode; 778 u8 supp_cck_rate; 779 u8 supp_ofdm_rate; 780 __le32 supp_ht_mcs; 781 __le16 supp_vht_mcs[4]; 782 783 u8 op_mode; 784 u8 op_vht_chan_width; 785 u8 op_vht_rx_nss; 786 u8 op_vht_rx_nss_type; 787 788 __le32 sta_status; 789 790 struct ra_phy phy; 791 } __packed; 792 793 struct sta_rec_ra_fixed { 794 __le16 tag; 795 __le16 len; 796 797 __le32 field; 798 u8 op_mode; 799 u8 op_vht_chan_width; 800 u8 op_vht_rx_nss; 801 u8 op_vht_rx_nss_type; 802 803 struct ra_phy phy; 804 805 u8 spe_en; 806 u8 short_preamble; 807 u8 is_5g; 808 u8 mmps_mode; 809 } __packed; 810 811 #define RATE_PARAM_FIXED 3 812 #define RATE_PARAM_AUTO 20 813 #define RATE_CFG_MCS GENMASK(3, 0) 814 #define RATE_CFG_NSS GENMASK(7, 4) 815 #define RATE_CFG_GI GENMASK(11, 8) 816 #define RATE_CFG_BW GENMASK(15, 12) 817 #define RATE_CFG_STBC GENMASK(19, 16) 818 #define RATE_CFG_LDPC GENMASK(23, 20) 819 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 820 821 struct sta_rec_bf { 822 __le16 tag; 823 __le16 len; 824 825 __le16 pfmu; /* 0xffff: no access right for PFMU */ 826 bool su_mu; /* 0: SU, 1: MU */ 827 u8 bf_cap; /* 0: iBF, 1: eBF */ 828 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 829 u8 ndpa_rate; 830 u8 ndp_rate; 831 u8 rept_poll_rate; 832 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 833 u8 nc; 834 u8 nr; 835 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 836 837 u8 mem_total; 838 u8 mem_20m; 839 struct { 840 u8 row; 841 u8 col: 6, row_msb: 2; 842 } mem[4]; 843 844 __le16 smart_ant; 845 u8 se_idx; 846 u8 auto_sounding; /* b7: low traffic indicator 847 * b6: Stop sounding for this entry 848 * b5 ~ b0: postpone sounding 849 */ 850 u8 ibf_timeout; 851 u8 ibf_dbw; 852 u8 ibf_ncol; 853 u8 ibf_nrow; 854 u8 nr_bw160; 855 u8 nc_bw160; 856 u8 ru_start_idx; 857 u8 ru_end_idx; 858 859 bool trigger_su; 860 bool trigger_mu; 861 bool ng16_su; 862 bool ng16_mu; 863 bool codebook42_su; 864 bool codebook75_mu; 865 866 u8 he_ltf; 867 u8 rsv[2]; 868 } __packed; 869 870 struct sta_rec_bfee { 871 __le16 tag; 872 __le16 len; 873 bool fb_identity_matrix; /* 1: feedback identity matrix */ 874 bool ignore_feedback; /* 1: ignore */ 875 u8 rsv[2]; 876 } __packed; 877 878 enum { 879 STA_REC_BASIC, 880 STA_REC_RA, 881 STA_REC_RA_CMM_INFO, 882 STA_REC_RA_UPDATE, 883 STA_REC_BF, 884 STA_REC_AMSDU, 885 STA_REC_BA, 886 STA_REC_RED, /* not used */ 887 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 888 STA_REC_HT, 889 STA_REC_VHT, 890 STA_REC_APPS, 891 STA_REC_KEY, 892 STA_REC_WTBL, 893 STA_REC_HE, 894 STA_REC_HW_AMSDU, 895 STA_REC_WTBL_AADOM, 896 STA_REC_KEY_V2, 897 STA_REC_MURU, 898 STA_REC_MUEDCA, 899 STA_REC_BFEE, 900 STA_REC_MAX_NUM 901 }; 902 903 enum mt7915_cipher_type { 904 MT_CIPHER_NONE, 905 MT_CIPHER_WEP40, 906 MT_CIPHER_WEP104, 907 MT_CIPHER_WEP128, 908 MT_CIPHER_TKIP, 909 MT_CIPHER_AES_CCMP, 910 MT_CIPHER_CCMP_256, 911 MT_CIPHER_GCMP, 912 MT_CIPHER_GCMP_256, 913 MT_CIPHER_WAPI, 914 MT_CIPHER_BIP_CMAC_128, 915 }; 916 917 enum { 918 CH_SWITCH_NORMAL = 0, 919 CH_SWITCH_SCAN = 3, 920 CH_SWITCH_MCC = 4, 921 CH_SWITCH_DFS = 5, 922 CH_SWITCH_BACKGROUND_SCAN_START = 6, 923 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 924 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 925 CH_SWITCH_SCAN_BYPASS_DPD = 9 926 }; 927 928 enum { 929 THERMAL_SENSOR_TEMP_QUERY, 930 THERMAL_SENSOR_MANUAL_CTRL, 931 THERMAL_SENSOR_INFO_QUERY, 932 THERMAL_SENSOR_TASK_CTRL, 933 }; 934 935 enum { 936 MT_EBF = BIT(0), /* explicit beamforming */ 937 MT_IBF = BIT(1) /* implicit beamforming */ 938 }; 939 940 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 941 sizeof(struct wtbl_generic) + \ 942 sizeof(struct wtbl_rx) + \ 943 sizeof(struct wtbl_ht) + \ 944 sizeof(struct wtbl_vht) + \ 945 sizeof(struct wtbl_ba) + \ 946 sizeof(struct wtbl_smps)) 947 948 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 949 sizeof(struct sta_rec_basic) + \ 950 sizeof(struct sta_rec_ht) + \ 951 sizeof(struct sta_rec_he) + \ 952 sizeof(struct sta_rec_ba) + \ 953 sizeof(struct sta_rec_vht) + \ 954 sizeof(struct tlv) + \ 955 MT7915_WTBL_UPDATE_MAX_SIZE) 956 957 #define MT7915_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 958 sizeof(struct wtbl_ba)) 959 960 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 961 sizeof(struct bss_info_omac) + \ 962 sizeof(struct bss_info_basic) +\ 963 sizeof(struct bss_info_rf_ch) +\ 964 sizeof(struct bss_info_ra) + \ 965 sizeof(struct bss_info_he) + \ 966 sizeof(struct bss_info_bmc_rate) +\ 967 sizeof(struct bss_info_ext_bss) +\ 968 sizeof(struct bss_info_sync_mode)) 969 970 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 971 sizeof(struct bss_info_bcn_csa) + \ 972 sizeof(struct bss_info_bcn_bcc) + \ 973 sizeof(struct bss_info_bcn_mbss) + \ 974 sizeof(struct bss_info_bcn_cont)) 975 976 #define PHY_MODE_A BIT(0) 977 #define PHY_MODE_B BIT(1) 978 #define PHY_MODE_G BIT(2) 979 #define PHY_MODE_GN BIT(3) 980 #define PHY_MODE_AN BIT(4) 981 #define PHY_MODE_AC BIT(5) 982 #define PHY_MODE_AX_24G BIT(6) 983 #define PHY_MODE_AX_5G BIT(7) 984 #define PHY_MODE_AX_6G BIT(8) 985 986 #define MODE_CCK BIT(0) 987 #define MODE_OFDM BIT(1) 988 #define MODE_HT BIT(2) 989 #define MODE_VHT BIT(3) 990 #define MODE_HE BIT(4) 991 992 #define STA_CAP_WMM BIT(0) 993 #define STA_CAP_SGI_20 BIT(4) 994 #define STA_CAP_SGI_40 BIT(5) 995 #define STA_CAP_TX_STBC BIT(6) 996 #define STA_CAP_RX_STBC BIT(7) 997 #define STA_CAP_VHT_SGI_80 BIT(16) 998 #define STA_CAP_VHT_SGI_160 BIT(17) 999 #define STA_CAP_VHT_TX_STBC BIT(18) 1000 #define STA_CAP_VHT_RX_STBC BIT(19) 1001 #define STA_CAP_VHT_LDPC BIT(23) 1002 #define STA_CAP_LDPC BIT(24) 1003 #define STA_CAP_HT BIT(26) 1004 #define STA_CAP_VHT BIT(27) 1005 #define STA_CAP_HE BIT(28) 1006 1007 /* HE MAC */ 1008 #define STA_REC_HE_CAP_HTC BIT(0) 1009 #define STA_REC_HE_CAP_BQR BIT(1) 1010 #define STA_REC_HE_CAP_BSR BIT(2) 1011 #define STA_REC_HE_CAP_OM BIT(3) 1012 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 1013 /* HE PHY */ 1014 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 1015 #define STA_REC_HE_CAP_LDPC BIT(6) 1016 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 1017 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 1018 /* STBC */ 1019 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 1020 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 1021 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 1022 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 1023 /* GI */ 1024 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 1025 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 1026 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 1027 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 1028 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 1029 /* 242 TONE */ 1030 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 1031 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 1032 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 1033 1034 #endif 1035