1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 struct mt7915_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /* event table */ 27 enum { 28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 29 MCU_EVENT_FW_START = 0x01, 30 MCU_EVENT_GENERIC = 0x01, 31 MCU_EVENT_ACCESS_REG = 0x02, 32 MCU_EVENT_MT_PATCH_SEM = 0x04, 33 MCU_EVENT_CH_PRIVILEGE = 0x18, 34 MCU_EVENT_EXT = 0xed, 35 MCU_EVENT_RESTART_DL = 0xef, 36 }; 37 38 /* ext event table */ 39 enum { 40 MCU_EXT_EVENT_PS_SYNC = 0x5, 41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 44 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 46 MCU_EXT_EVENT_RATE_REPORT = 0x87, 47 }; 48 49 enum { 50 MCU_ATE_SET_TRX = 0x1, 51 MCU_ATE_SET_FREQ_OFFSET = 0xa, 52 MCU_ATE_SET_SLOT_TIME = 0x13, 53 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 54 }; 55 56 struct mt7915_mcu_rxd { 57 __le32 rxd[6]; 58 59 __le16 len; 60 __le16 pkt_type_id; 61 62 u8 eid; 63 u8 seq; 64 __le16 __rsv; 65 66 u8 ext_eid; 67 u8 __rsv1[2]; 68 u8 s2d_index; 69 }; 70 71 struct mt7915_mcu_csa_notify { 72 struct mt7915_mcu_rxd rxd; 73 74 u8 omac_idx; 75 u8 csa_count; 76 u8 band_idx; 77 u8 rsv; 78 } __packed; 79 80 struct mt7915_mcu_rdd_report { 81 struct mt7915_mcu_rxd rxd; 82 83 u8 band_idx; 84 u8 long_detected; 85 u8 constant_prf_detected; 86 u8 staggered_prf_detected; 87 u8 radar_type_idx; 88 u8 periodic_pulse_num; 89 u8 long_pulse_num; 90 u8 hw_pulse_num; 91 92 u8 out_lpn; 93 u8 out_spn; 94 u8 out_crpn; 95 u8 out_crpw; 96 u8 out_crbn; 97 u8 out_stgpn; 98 u8 out_stgpw; 99 100 u8 rsv; 101 102 __le32 out_pri_const; 103 __le32 out_pri_stg[3]; 104 105 struct { 106 __le32 start; 107 __le16 pulse_width; 108 __le16 pulse_power; 109 u8 mdrdy_flag; 110 u8 rsv[3]; 111 } long_pulse[32]; 112 113 struct { 114 __le32 start; 115 __le16 pulse_width; 116 __le16 pulse_power; 117 u8 mdrdy_flag; 118 u8 rsv[3]; 119 } periodic_pulse[32]; 120 121 struct { 122 __le32 start; 123 __le16 pulse_width; 124 __le16 pulse_power; 125 u8 sc_pass; 126 u8 sw_reset; 127 u8 mdrdy_flag; 128 u8 tx_active; 129 } hw_pulse[32]; 130 } __packed; 131 132 struct mt7915_mcu_eeprom { 133 u8 buffer_mode; 134 u8 format; 135 __le16 len; 136 } __packed; 137 138 struct mt7915_mcu_eeprom_info { 139 __le32 addr; 140 __le32 valid; 141 u8 data[16]; 142 } __packed; 143 144 struct mt7915_mcu_ra_info { 145 struct mt7915_mcu_rxd rxd; 146 147 __le32 event_id; 148 __le16 wlan_idx; 149 __le16 ru_idx; 150 __le16 direction; 151 __le16 dump_group; 152 153 __le32 suggest_rate; 154 __le32 min_rate; /* for dynamic sounding */ 155 __le32 max_rate; /* for dynamic sounding */ 156 __le32 init_rate_down_rate; 157 158 __le16 curr_rate; 159 __le16 init_rate_down_total; 160 __le16 init_rate_down_succ; 161 __le16 success; 162 __le16 attempts; 163 164 __le16 prev_rate; 165 __le16 prob_up_rate; 166 u8 no_rate_up_cnt; 167 u8 ppdu_cnt; 168 u8 gi; 169 170 u8 try_up_fail; 171 u8 try_up_total; 172 u8 suggest_wf; 173 u8 try_up_check; 174 u8 prob_up_period; 175 u8 prob_down_pending; 176 } __packed; 177 178 179 struct mt7915_mcu_phy_rx_info { 180 u8 category; 181 u8 rate; 182 u8 mode; 183 u8 nsts; 184 u8 gi; 185 u8 coding; 186 u8 stbc; 187 u8 bw; 188 }; 189 190 #define MT_RA_RATE_NSS GENMASK(8, 6) 191 #define MT_RA_RATE_MCS GENMASK(3, 0) 192 #define MT_RA_RATE_TX_MODE GENMASK(12, 9) 193 #define MT_RA_RATE_DCM_EN BIT(4) 194 #define MT_RA_RATE_BW GENMASK(14, 13) 195 196 struct edca { 197 u8 queue; 198 u8 set; 199 u8 aifs; 200 u8 cw_min; 201 __le16 cw_max; 202 __le16 txop; 203 }; 204 205 struct mt7915_mcu_tx { 206 u8 total; 207 u8 action; 208 u8 valid; 209 u8 mode; 210 211 struct edca edca[IEEE80211_NUM_ACS]; 212 } __packed; 213 214 #define WMM_AIFS_SET BIT(0) 215 #define WMM_CW_MIN_SET BIT(1) 216 #define WMM_CW_MAX_SET BIT(2) 217 #define WMM_TXOP_SET BIT(3) 218 #define WMM_PARAM_SET GENMASK(3, 0) 219 220 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 221 #define MCU_PKT_ID 0xa0 222 223 enum { 224 MCU_Q_QUERY, 225 MCU_Q_SET, 226 MCU_Q_RESERVED, 227 MCU_Q_NA 228 }; 229 230 enum { 231 MCU_S2D_H2N, 232 MCU_S2D_C2N, 233 MCU_S2D_H2C, 234 MCU_S2D_H2CN 235 }; 236 237 238 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 239 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 240 #define __MCU_CMD_FIELD_QUERY BIT(16) 241 #define __MCU_CMD_FIELD_WA BIT(17) 242 243 enum { 244 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 245 MCU_CMD_FW_START_REQ = 0x02, 246 MCU_CMD_INIT_ACCESS_REG = 0x3, 247 MCU_CMD_NIC_POWER_CTRL = 0x4, 248 MCU_CMD_PATCH_START_REQ = 0x05, 249 MCU_CMD_PATCH_FINISH_REQ = 0x07, 250 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 251 MCU_CMD_WA_PARAM = 0xC4, 252 MCU_CMD_EXT_CID = 0xED, 253 MCU_CMD_FW_SCATTER = 0xEE, 254 MCU_CMD_RESTART_DL_REQ = 0xEF, 255 }; 256 257 enum { 258 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 259 MCU_EXT_CMD_RF_TEST = 0x04, 260 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 261 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 262 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 263 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 264 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 265 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 266 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 267 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 268 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 269 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 270 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 271 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 272 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 273 MCU_EXT_CMD_ATE_CTRL = 0x3d, 274 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 275 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 276 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 277 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 278 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 279 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 280 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 281 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 282 MCU_EXT_CMD_SCS_CTRL = 0x82, 283 MCU_EXT_CMD_RATE_CTRL = 0x87, 284 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 285 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 286 MCU_EXT_CMD_SET_SPR = 0xa8, 287 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 288 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 289 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 290 }; 291 292 enum { 293 MCU_WA_PARAM_CMD_QUERY, 294 MCU_WA_PARAM_CMD_SET, 295 MCU_WA_PARAM_CMD_CAPABILITY, 296 MCU_WA_PARAM_CMD_DEBUG, 297 }; 298 299 enum { 300 MCU_WA_PARAM_RED = 0x0e, 301 }; 302 303 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, MCU_CMD_##_t) 304 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 305 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 306 MCU_EXT_CMD_##_t)) 307 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 308 309 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 310 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 311 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 312 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 313 MCU_WA_PARAM_CMD_##_t)) 314 315 enum { 316 PATCH_SEM_RELEASE, 317 PATCH_SEM_GET 318 }; 319 320 enum { 321 PATCH_NOT_DL_SEM_FAIL, 322 PATCH_IS_DL, 323 PATCH_NOT_DL_SEM_SUCCESS, 324 PATCH_REL_SEM_SUCCESS 325 }; 326 327 enum { 328 FW_STATE_INITIAL, 329 FW_STATE_FW_DOWNLOAD, 330 FW_STATE_NORMAL_OPERATION, 331 FW_STATE_NORMAL_TRX, 332 FW_STATE_WACPU_RDY = 7 333 }; 334 335 enum { 336 EE_MODE_EFUSE, 337 EE_MODE_BUFFER, 338 }; 339 340 enum { 341 EE_FORMAT_BIN, 342 EE_FORMAT_WHOLE, 343 EE_FORMAT_MULTIPLE, 344 }; 345 346 enum { 347 MCU_PHY_STATE_TX_RATE, 348 MCU_PHY_STATE_RX_RATE, 349 MCU_PHY_STATE_RSSI, 350 MCU_PHY_STATE_CONTENTION_RX_RATE, 351 MCU_PHY_STATE_OFDMLQ_CNINFO, 352 }; 353 354 #define STA_TYPE_STA BIT(0) 355 #define STA_TYPE_AP BIT(1) 356 #define STA_TYPE_ADHOC BIT(2) 357 #define STA_TYPE_WDS BIT(4) 358 #define STA_TYPE_BC BIT(5) 359 360 #define NETWORK_INFRA BIT(16) 361 #define NETWORK_P2P BIT(17) 362 #define NETWORK_IBSS BIT(18) 363 #define NETWORK_WDS BIT(21) 364 365 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 366 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 367 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 368 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 369 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 370 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 371 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 372 373 #define CONN_STATE_DISCONNECT 0 374 #define CONN_STATE_CONNECT 1 375 #define CONN_STATE_PORT_SECURE 2 376 377 enum { 378 DEV_INFO_ACTIVE, 379 DEV_INFO_MAX_NUM 380 }; 381 382 enum { 383 SCS_SEND_DATA, 384 SCS_SET_MANUAL_PD_TH, 385 SCS_CONFIG, 386 SCS_ENABLE, 387 SCS_SHOW_INFO, 388 SCS_GET_GLO_ADDR, 389 SCS_GET_GLO_ADDR_EVENT, 390 }; 391 392 enum { 393 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 394 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 395 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 396 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 397 CMD_CBW_10MHZ, 398 CMD_CBW_5MHZ, 399 CMD_CBW_8080MHZ, 400 401 CMD_HE_MCS_BW80 = 0, 402 CMD_HE_MCS_BW160, 403 CMD_HE_MCS_BW8080, 404 CMD_HE_MCS_BW_NUM 405 }; 406 407 struct tlv { 408 __le16 tag; 409 __le16 len; 410 } __packed; 411 412 struct bss_info_omac { 413 __le16 tag; 414 __le16 len; 415 u8 hw_bss_idx; 416 u8 omac_idx; 417 u8 band_idx; 418 u8 rsv0; 419 __le32 conn_type; 420 u32 rsv1; 421 } __packed; 422 423 struct bss_info_basic { 424 __le16 tag; 425 __le16 len; 426 __le32 network_type; 427 u8 active; 428 u8 rsv0; 429 __le16 bcn_interval; 430 u8 bssid[ETH_ALEN]; 431 u8 wmm_idx; 432 u8 dtim_period; 433 u8 bmc_wcid_lo; 434 u8 cipher; 435 u8 phy_mode; 436 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 437 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 438 u8 bmc_wcid_hi; /* high Byte and version */ 439 u8 rsv[2]; 440 } __packed; 441 442 struct bss_info_rf_ch { 443 __le16 tag; 444 __le16 len; 445 u8 pri_ch; 446 u8 center_ch0; 447 u8 center_ch1; 448 u8 bw; 449 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 450 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 451 u8 rsv[2]; 452 } __packed; 453 454 struct bss_info_ext_bss { 455 __le16 tag; 456 __le16 len; 457 __le32 mbss_tsf_offset; /* in unit of us */ 458 u8 rsv[8]; 459 } __packed; 460 461 struct bss_info_bmc_rate { 462 __le16 tag; 463 __le16 len; 464 __le16 bc_trans; 465 __le16 mc_trans; 466 u8 short_preamble; 467 u8 rsv[7]; 468 } __packed; 469 470 struct bss_info_ra { 471 __le16 tag; 472 __le16 len; 473 u8 op_mode; 474 u8 adhoc_en; 475 u8 short_preamble; 476 u8 tx_streams; 477 u8 rx_streams; 478 u8 algo; 479 u8 force_sgi; 480 u8 force_gf; 481 u8 ht_mode; 482 u8 has_20_sta; /* Check if any sta support GF. */ 483 u8 bss_width_trigger_events; 484 u8 vht_nss_cap; 485 u8 vht_bw_signal; /* not use */ 486 u8 vht_force_sgi; /* not use */ 487 u8 se_off; 488 u8 antenna_idx; 489 u8 train_up_rule; 490 u8 rsv[3]; 491 unsigned short train_up_high_thres; 492 short train_up_rule_rssi; 493 unsigned short low_traffic_thres; 494 __le16 max_phyrate; 495 __le32 phy_cap; 496 __le32 interval; 497 __le32 fast_interval; 498 } __packed; 499 500 struct bss_info_hw_amsdu { 501 __le16 tag; 502 __le16 len; 503 __le32 cmp_bitmap_0; 504 __le32 cmp_bitmap_1; 505 __le16 trig_thres; 506 u8 enable; 507 u8 rsv; 508 } __packed; 509 510 struct bss_info_he { 511 __le16 tag; 512 __le16 len; 513 u8 he_pe_duration; 514 u8 vht_op_info_present; 515 __le16 he_rts_thres; 516 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 517 u8 rsv[6]; 518 } __packed; 519 520 struct bss_info_bcn { 521 __le16 tag; 522 __le16 len; 523 u8 ver; 524 u8 enable; 525 __le16 sub_ntlv; 526 } __packed __aligned(4); 527 528 struct bss_info_bcn_csa { 529 __le16 tag; 530 __le16 len; 531 u8 cnt; 532 u8 rsv[3]; 533 } __packed __aligned(4); 534 535 struct bss_info_bcn_bcc { 536 __le16 tag; 537 __le16 len; 538 u8 cnt; 539 u8 rsv[3]; 540 } __packed __aligned(4); 541 542 struct bss_info_bcn_mbss { 543 #define MAX_BEACON_NUM 32 544 __le16 tag; 545 __le16 len; 546 __le32 bitmap; 547 __le16 offset[MAX_BEACON_NUM]; 548 u8 rsv[8]; 549 } __packed __aligned(4); 550 551 struct bss_info_bcn_cont { 552 __le16 tag; 553 __le16 len; 554 __le16 tim_ofs; 555 __le16 csa_ofs; 556 __le16 bcc_ofs; 557 __le16 pkt_len; 558 } __packed __aligned(4); 559 560 enum { 561 BSS_INFO_BCN_CSA, 562 BSS_INFO_BCN_BCC, 563 BSS_INFO_BCN_MBSSID, 564 BSS_INFO_BCN_CONTENT, 565 BSS_INFO_BCN_MAX 566 }; 567 568 enum { 569 BSS_INFO_OMAC, 570 BSS_INFO_BASIC, 571 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 572 BSS_INFO_PM, /* sta only */ 573 BSS_INFO_UAPSD, /* sta only */ 574 BSS_INFO_ROAM_DETECT, /* obsoleted */ 575 BSS_INFO_LQ_RM, /* obsoleted */ 576 BSS_INFO_EXT_BSS, 577 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 578 BSS_INFO_SYNC_MODE, /* obsoleted */ 579 BSS_INFO_RA, 580 BSS_INFO_HW_AMSDU, 581 BSS_INFO_BSS_COLOR, 582 BSS_INFO_HE_BASIC, 583 BSS_INFO_PROTECT_INFO, 584 BSS_INFO_OFFLOAD, 585 BSS_INFO_11V_MBSSID, 586 BSS_INFO_MAX_NUM 587 }; 588 589 enum { 590 WTBL_RESET_AND_SET = 1, 591 WTBL_SET, 592 WTBL_QUERY, 593 WTBL_RESET_ALL 594 }; 595 596 struct wtbl_req_hdr { 597 u8 wlan_idx_lo; 598 u8 operation; 599 __le16 tlv_num; 600 u8 wlan_idx_hi; 601 u8 rsv[3]; 602 } __packed; 603 604 struct wtbl_generic { 605 __le16 tag; 606 __le16 len; 607 u8 peer_addr[ETH_ALEN]; 608 u8 muar_idx; 609 u8 skip_tx; 610 u8 cf_ack; 611 u8 qos; 612 u8 mesh; 613 u8 adm; 614 __le16 partial_aid; 615 u8 baf_en; 616 u8 aad_om; 617 } __packed; 618 619 struct wtbl_rx { 620 __le16 tag; 621 __le16 len; 622 u8 rcid; 623 u8 rca1; 624 u8 rca2; 625 u8 rv; 626 u8 rsv[4]; 627 } __packed; 628 629 struct wtbl_ht { 630 __le16 tag; 631 __le16 len; 632 u8 ht; 633 u8 ldpc; 634 u8 af; 635 u8 mm; 636 u8 rsv[4]; 637 } __packed; 638 639 struct wtbl_vht { 640 __le16 tag; 641 __le16 len; 642 u8 ldpc; 643 u8 dyn_bw; 644 u8 vht; 645 u8 txop_ps; 646 u8 rsv[4]; 647 } __packed; 648 649 struct wtbl_hdr_trans { 650 __le16 tag; 651 __le16 len; 652 u8 to_ds; 653 u8 from_ds; 654 u8 no_rx_trans; 655 u8 _rsv; 656 }; 657 658 enum { 659 MT_BA_TYPE_INVALID, 660 MT_BA_TYPE_ORIGINATOR, 661 MT_BA_TYPE_RECIPIENT 662 }; 663 664 enum { 665 RST_BA_MAC_TID_MATCH, 666 RST_BA_MAC_MATCH, 667 RST_BA_NO_MATCH 668 }; 669 670 struct wtbl_ba { 671 __le16 tag; 672 __le16 len; 673 /* common */ 674 u8 tid; 675 u8 ba_type; 676 u8 rsv0[2]; 677 /* originator only */ 678 __le16 sn; 679 u8 ba_en; 680 u8 ba_winsize_idx; 681 __le16 ba_winsize; 682 /* recipient only */ 683 u8 peer_addr[ETH_ALEN]; 684 u8 rst_ba_tid; 685 u8 rst_ba_sel; 686 u8 rst_ba_sb; 687 u8 band_idx; 688 u8 rsv1[4]; 689 } __packed; 690 691 struct wtbl_smps { 692 __le16 tag; 693 __le16 len; 694 u8 smps; 695 u8 rsv[3]; 696 } __packed; 697 698 enum { 699 WTBL_GENERIC, 700 WTBL_RX, 701 WTBL_HT, 702 WTBL_VHT, 703 WTBL_PEER_PS, /* not used */ 704 WTBL_TX_PS, 705 WTBL_HDR_TRANS, 706 WTBL_SEC_KEY, 707 WTBL_BA, 708 WTBL_RDG, /* obsoleted */ 709 WTBL_PROTECT, /* not used */ 710 WTBL_CLEAR, /* not used */ 711 WTBL_BF, 712 WTBL_SMPS, 713 WTBL_RAW_DATA, /* debug only */ 714 WTBL_PN, 715 WTBL_SPE, 716 WTBL_MAX_NUM 717 }; 718 719 struct sta_ntlv_hdr { 720 u8 rsv[2]; 721 __le16 tlv_num; 722 } __packed; 723 724 struct sta_req_hdr { 725 u8 bss_idx; 726 u8 wlan_idx_lo; 727 __le16 tlv_num; 728 u8 is_tlv_append; 729 u8 muar_idx; 730 u8 wlan_idx_hi; 731 u8 rsv; 732 } __packed; 733 734 struct sta_rec_basic { 735 __le16 tag; 736 __le16 len; 737 __le32 conn_type; 738 u8 conn_state; 739 u8 qos; 740 __le16 aid; 741 u8 peer_addr[ETH_ALEN]; 742 __le16 extra_info; 743 } __packed; 744 745 struct sta_rec_ht { 746 __le16 tag; 747 __le16 len; 748 __le16 ht_cap; 749 u16 rsv; 750 } __packed; 751 752 struct sta_rec_vht { 753 __le16 tag; 754 __le16 len; 755 __le32 vht_cap; 756 __le16 vht_rx_mcs_map; 757 __le16 vht_tx_mcs_map; 758 u8 rts_bw_sig; 759 u8 rsv[3]; 760 } __packed; 761 762 struct sta_rec_uapsd { 763 __le16 tag; 764 __le16 len; 765 u8 dac_map; 766 u8 tac_map; 767 u8 max_sp; 768 u8 rsv0; 769 __le16 listen_interval; 770 u8 rsv1[2]; 771 } __packed; 772 773 struct sta_rec_muru { 774 __le16 tag; 775 __le16 len; 776 777 struct { 778 bool ofdma_dl_en; 779 bool ofdma_ul_en; 780 bool mimo_dl_en; 781 bool mimo_ul_en; 782 u8 rsv[4]; 783 } cfg; 784 785 struct { 786 u8 punc_pream_rx; 787 bool he_20m_in_40m_2g; 788 bool he_20m_in_160m; 789 bool he_80m_in_160m; 790 bool lt16_sigb; 791 bool rx_su_comp_sigb; 792 bool rx_su_non_comp_sigb; 793 u8 rsv; 794 } ofdma_dl; 795 796 struct { 797 u8 t_frame_dur; 798 u8 mu_cascading; 799 u8 uo_ra; 800 u8 he_2x996_tone; 801 u8 rx_t_frame_11ac; 802 u8 rsv[3]; 803 } ofdma_ul; 804 805 struct { 806 bool vht_mu_bfee; 807 bool partial_bw_dl_mimo; 808 u8 rsv[2]; 809 } mimo_dl; 810 811 struct { 812 bool full_ul_mimo; 813 bool partial_ul_mimo; 814 u8 rsv[2]; 815 } mimo_ul; 816 } __packed; 817 818 struct sta_rec_he { 819 __le16 tag; 820 __le16 len; 821 822 __le32 he_cap; 823 824 u8 t_frame_dur; 825 u8 max_ampdu_exp; 826 u8 bw_set; 827 u8 device_class; 828 u8 dcm_tx_mode; 829 u8 dcm_tx_max_nss; 830 u8 dcm_rx_mode; 831 u8 dcm_rx_max_nss; 832 u8 dcm_max_ru; 833 u8 punc_pream_rx; 834 u8 pkt_ext; 835 u8 rsv1; 836 837 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 838 839 u8 rsv2[2]; 840 } __packed; 841 842 struct sta_rec_ba { 843 __le16 tag; 844 __le16 len; 845 u8 tid; 846 u8 ba_type; 847 u8 amsdu; 848 u8 ba_en; 849 __le16 ssn; 850 __le16 winsize; 851 } __packed; 852 853 struct sta_rec_amsdu { 854 __le16 tag; 855 __le16 len; 856 u8 max_amsdu_num; 857 u8 max_mpdu_size; 858 u8 amsdu_en; 859 u8 rsv; 860 } __packed; 861 862 struct sec_key { 863 u8 cipher_id; 864 u8 cipher_len; 865 u8 key_id; 866 u8 key_len; 867 u8 key[32]; 868 } __packed; 869 870 struct sta_rec_sec { 871 __le16 tag; 872 __le16 len; 873 u8 add; 874 u8 n_cipher; 875 u8 rsv[2]; 876 877 struct sec_key key[2]; 878 } __packed; 879 880 struct ra_phy { 881 u8 type; 882 u8 flag; 883 u8 stbc; 884 u8 sgi; 885 u8 bw; 886 u8 ldpc; 887 u8 mcs; 888 u8 nss; 889 u8 he_ltf; 890 }; 891 892 struct sta_rec_ra { 893 __le16 tag; 894 __le16 len; 895 896 u8 valid; 897 u8 auto_rate; 898 u8 phy_mode; 899 u8 channel; 900 u8 bw; 901 u8 disable_cck; 902 u8 ht_mcs32; 903 u8 ht_gf; 904 u8 ht_mcs[4]; 905 u8 mmps_mode; 906 u8 gband_256; 907 u8 af; 908 u8 auth_wapi_mode; 909 u8 rate_len; 910 911 u8 supp_mode; 912 u8 supp_cck_rate; 913 u8 supp_ofdm_rate; 914 __le32 supp_ht_mcs; 915 __le16 supp_vht_mcs[4]; 916 917 u8 op_mode; 918 u8 op_vht_chan_width; 919 u8 op_vht_rx_nss; 920 u8 op_vht_rx_nss_type; 921 922 __le32 sta_status; 923 924 struct ra_phy phy; 925 } __packed; 926 927 struct sta_rec_ra_fixed { 928 __le16 tag; 929 __le16 len; 930 931 __le32 field; 932 u8 op_mode; 933 u8 op_vht_chan_width; 934 u8 op_vht_rx_nss; 935 u8 op_vht_rx_nss_type; 936 937 struct ra_phy phy; 938 939 u8 spe_en; 940 u8 short_preamble; 941 u8 is_5g; 942 u8 mmps_mode; 943 } __packed; 944 945 #define RATE_PARAM_FIXED 3 946 #define RATE_PARAM_AUTO 20 947 #define RATE_CFG_MCS GENMASK(3, 0) 948 #define RATE_CFG_NSS GENMASK(7, 4) 949 #define RATE_CFG_GI GENMASK(11, 8) 950 #define RATE_CFG_BW GENMASK(15, 12) 951 #define RATE_CFG_STBC GENMASK(19, 16) 952 #define RATE_CFG_LDPC GENMASK(23, 20) 953 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 954 955 struct sta_rec_bf { 956 __le16 tag; 957 __le16 len; 958 959 __le16 pfmu; /* 0xffff: no access right for PFMU */ 960 bool su_mu; /* 0: SU, 1: MU */ 961 u8 bf_cap; /* 0: iBF, 1: eBF */ 962 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 963 u8 ndpa_rate; 964 u8 ndp_rate; 965 u8 rept_poll_rate; 966 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 967 u8 nc; 968 u8 nr; 969 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 970 971 u8 mem_total; 972 u8 mem_20m; 973 struct { 974 u8 row; 975 u8 col: 6, row_msb: 2; 976 } mem[4]; 977 978 __le16 smart_ant; 979 u8 se_idx; 980 u8 auto_sounding; /* b7: low traffic indicator 981 * b6: Stop sounding for this entry 982 * b5 ~ b0: postpone sounding 983 */ 984 u8 ibf_timeout; 985 u8 ibf_dbw; 986 u8 ibf_ncol; 987 u8 ibf_nrow; 988 u8 nr_bw160; 989 u8 nc_bw160; 990 u8 ru_start_idx; 991 u8 ru_end_idx; 992 993 bool trigger_su; 994 bool trigger_mu; 995 bool ng16_su; 996 bool ng16_mu; 997 bool codebook42_su; 998 bool codebook75_mu; 999 1000 u8 he_ltf; 1001 u8 rsv[2]; 1002 } __packed; 1003 1004 struct sta_rec_bfee { 1005 __le16 tag; 1006 __le16 len; 1007 bool fb_identity_matrix; /* 1: feedback identity matrix */ 1008 bool ignore_feedback; /* 1: ignore */ 1009 u8 rsv[2]; 1010 } __packed; 1011 1012 enum { 1013 STA_REC_BASIC, 1014 STA_REC_RA, 1015 STA_REC_RA_CMM_INFO, 1016 STA_REC_RA_UPDATE, 1017 STA_REC_BF, 1018 STA_REC_AMSDU, 1019 STA_REC_BA, 1020 STA_REC_RED, /* not used */ 1021 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 1022 STA_REC_HT, 1023 STA_REC_VHT, 1024 STA_REC_APPS, 1025 STA_REC_KEY, 1026 STA_REC_WTBL, 1027 STA_REC_HE, 1028 STA_REC_HW_AMSDU, 1029 STA_REC_WTBL_AADOM, 1030 STA_REC_KEY_V2, 1031 STA_REC_MURU, 1032 STA_REC_MUEDCA, 1033 STA_REC_BFEE, 1034 STA_REC_MAX_NUM 1035 }; 1036 1037 enum mt7915_cipher_type { 1038 MT_CIPHER_NONE, 1039 MT_CIPHER_WEP40, 1040 MT_CIPHER_WEP104, 1041 MT_CIPHER_WEP128, 1042 MT_CIPHER_TKIP, 1043 MT_CIPHER_AES_CCMP, 1044 MT_CIPHER_CCMP_256, 1045 MT_CIPHER_GCMP, 1046 MT_CIPHER_GCMP_256, 1047 MT_CIPHER_WAPI, 1048 MT_CIPHER_BIP_CMAC_128, 1049 }; 1050 1051 enum { 1052 CH_SWITCH_NORMAL = 0, 1053 CH_SWITCH_SCAN = 3, 1054 CH_SWITCH_MCC = 4, 1055 CH_SWITCH_DFS = 5, 1056 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1057 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1058 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1059 CH_SWITCH_SCAN_BYPASS_DPD = 9 1060 }; 1061 1062 enum { 1063 THERMAL_SENSOR_TEMP_QUERY, 1064 THERMAL_SENSOR_MANUAL_CTRL, 1065 THERMAL_SENSOR_INFO_QUERY, 1066 THERMAL_SENSOR_TASK_CTRL, 1067 }; 1068 1069 enum { 1070 MT_EBF = BIT(0), /* explicit beamforming */ 1071 MT_IBF = BIT(1) /* implicit beamforming */ 1072 }; 1073 1074 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 1075 sizeof(struct wtbl_generic) + \ 1076 sizeof(struct wtbl_rx) + \ 1077 sizeof(struct wtbl_ht) + \ 1078 sizeof(struct wtbl_vht) + \ 1079 sizeof(struct wtbl_hdr_trans) +\ 1080 sizeof(struct wtbl_ba) + \ 1081 sizeof(struct wtbl_smps)) 1082 1083 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1084 sizeof(struct sta_rec_basic) + \ 1085 sizeof(struct sta_rec_ht) + \ 1086 sizeof(struct sta_rec_he) + \ 1087 sizeof(struct sta_rec_ba) + \ 1088 sizeof(struct sta_rec_vht) + \ 1089 sizeof(struct sta_rec_uapsd) + \ 1090 sizeof(struct sta_rec_amsdu) + \ 1091 sizeof(struct tlv) + \ 1092 MT7915_WTBL_UPDATE_MAX_SIZE) 1093 1094 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1095 sizeof(struct bss_info_omac) + \ 1096 sizeof(struct bss_info_basic) +\ 1097 sizeof(struct bss_info_rf_ch) +\ 1098 sizeof(struct bss_info_ra) + \ 1099 sizeof(struct bss_info_hw_amsdu) +\ 1100 sizeof(struct bss_info_he) + \ 1101 sizeof(struct bss_info_bmc_rate) +\ 1102 sizeof(struct bss_info_ext_bss)) 1103 1104 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 1105 sizeof(struct bss_info_bcn_csa) + \ 1106 sizeof(struct bss_info_bcn_bcc) + \ 1107 sizeof(struct bss_info_bcn_mbss) + \ 1108 sizeof(struct bss_info_bcn_cont)) 1109 1110 #define PHY_MODE_A BIT(0) 1111 #define PHY_MODE_B BIT(1) 1112 #define PHY_MODE_G BIT(2) 1113 #define PHY_MODE_GN BIT(3) 1114 #define PHY_MODE_AN BIT(4) 1115 #define PHY_MODE_AC BIT(5) 1116 #define PHY_MODE_AX_24G BIT(6) 1117 #define PHY_MODE_AX_5G BIT(7) 1118 #define PHY_MODE_AX_6G BIT(8) 1119 1120 #define MODE_CCK BIT(0) 1121 #define MODE_OFDM BIT(1) 1122 #define MODE_HT BIT(2) 1123 #define MODE_VHT BIT(3) 1124 #define MODE_HE BIT(4) 1125 1126 #define STA_CAP_WMM BIT(0) 1127 #define STA_CAP_SGI_20 BIT(4) 1128 #define STA_CAP_SGI_40 BIT(5) 1129 #define STA_CAP_TX_STBC BIT(6) 1130 #define STA_CAP_RX_STBC BIT(7) 1131 #define STA_CAP_VHT_SGI_80 BIT(16) 1132 #define STA_CAP_VHT_SGI_160 BIT(17) 1133 #define STA_CAP_VHT_TX_STBC BIT(18) 1134 #define STA_CAP_VHT_RX_STBC BIT(19) 1135 #define STA_CAP_VHT_LDPC BIT(23) 1136 #define STA_CAP_LDPC BIT(24) 1137 #define STA_CAP_HT BIT(26) 1138 #define STA_CAP_VHT BIT(27) 1139 #define STA_CAP_HE BIT(28) 1140 1141 /* HE MAC */ 1142 #define STA_REC_HE_CAP_HTC BIT(0) 1143 #define STA_REC_HE_CAP_BQR BIT(1) 1144 #define STA_REC_HE_CAP_BSR BIT(2) 1145 #define STA_REC_HE_CAP_OM BIT(3) 1146 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 1147 /* HE PHY */ 1148 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 1149 #define STA_REC_HE_CAP_LDPC BIT(6) 1150 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 1151 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 1152 /* STBC */ 1153 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 1154 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 1155 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 1156 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 1157 /* GI */ 1158 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 1159 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 1160 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 1161 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 1162 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 1163 /* 242 TONE */ 1164 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 1165 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 1166 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 1167 1168 #endif 1169