1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 struct mt7915_mcu_txd { 10 __le32 txd[8]; 11 12 __le16 len; 13 __le16 pq_id; 14 15 u8 cid; 16 u8 pkt_type; 17 u8 set_query; /* FW don't care */ 18 u8 seq; 19 20 u8 uc_d2b0_rev; 21 u8 ext_cid; 22 u8 s2d_index; 23 u8 ext_cid_ack; 24 25 u32 reserved[5]; 26 } __packed __aligned(4); 27 28 enum { 29 MCU_ATE_SET_TRX = 0x1, 30 MCU_ATE_SET_FREQ_OFFSET = 0xa, 31 MCU_ATE_SET_SLOT_TIME = 0x13, 32 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 33 }; 34 35 struct mt7915_mcu_rxd { 36 __le32 rxd[6]; 37 38 __le16 len; 39 __le16 pkt_type_id; 40 41 u8 eid; 42 u8 seq; 43 __le16 __rsv; 44 45 u8 ext_eid; 46 u8 __rsv1[2]; 47 u8 s2d_index; 48 }; 49 50 struct mt7915_mcu_thermal_ctrl { 51 u8 ctrl_id; 52 u8 band_idx; 53 union { 54 struct { 55 u8 protect_type; /* 1: duty admit, 2: radio off */ 56 u8 trigger_type; /* 0: low, 1: high */ 57 } __packed type; 58 struct { 59 u8 duty_level; /* level 0~3 */ 60 u8 duty_cycle; 61 } __packed duty; 62 }; 63 } __packed; 64 65 struct mt7915_mcu_thermal_notify { 66 struct mt7915_mcu_rxd rxd; 67 68 struct mt7915_mcu_thermal_ctrl ctrl; 69 __le32 temperature; 70 u8 rsv[8]; 71 } __packed; 72 73 struct mt7915_mcu_csa_notify { 74 struct mt7915_mcu_rxd rxd; 75 76 u8 omac_idx; 77 u8 csa_count; 78 u8 band_idx; 79 u8 rsv; 80 } __packed; 81 82 struct mt7915_mcu_bcc_notify { 83 struct mt7915_mcu_rxd rxd; 84 85 u8 band_idx; 86 u8 omac_idx; 87 u8 cca_count; 88 u8 rsv; 89 } __packed; 90 91 struct mt7915_mcu_rdd_report { 92 struct mt7915_mcu_rxd rxd; 93 94 u8 band_idx; 95 u8 long_detected; 96 u8 constant_prf_detected; 97 u8 staggered_prf_detected; 98 u8 radar_type_idx; 99 u8 periodic_pulse_num; 100 u8 long_pulse_num; 101 u8 hw_pulse_num; 102 103 u8 out_lpn; 104 u8 out_spn; 105 u8 out_crpn; 106 u8 out_crpw; 107 u8 out_crbn; 108 u8 out_stgpn; 109 u8 out_stgpw; 110 111 u8 rsv; 112 113 __le32 out_pri_const; 114 __le32 out_pri_stg[3]; 115 116 struct { 117 __le32 start; 118 __le16 pulse_width; 119 __le16 pulse_power; 120 u8 mdrdy_flag; 121 u8 rsv[3]; 122 } long_pulse[32]; 123 124 struct { 125 __le32 start; 126 __le16 pulse_width; 127 __le16 pulse_power; 128 u8 mdrdy_flag; 129 u8 rsv[3]; 130 } periodic_pulse[32]; 131 132 struct { 133 __le32 start; 134 __le16 pulse_width; 135 __le16 pulse_power; 136 u8 sc_pass; 137 u8 sw_reset; 138 u8 mdrdy_flag; 139 u8 tx_active; 140 } hw_pulse[32]; 141 } __packed; 142 143 struct mt7915_mcu_background_chain_ctrl { 144 u8 chan; /* primary channel */ 145 u8 central_chan; /* central channel */ 146 u8 bw; 147 u8 tx_stream; 148 u8 rx_stream; 149 150 u8 monitor_chan; /* monitor channel */ 151 u8 monitor_central_chan;/* monitor central channel */ 152 u8 monitor_bw; 153 u8 monitor_tx_stream; 154 u8 monitor_rx_stream; 155 156 u8 scan_mode; /* 0: ScanStop 157 * 1: ScanStart 158 * 2: ScanRunning 159 */ 160 u8 band_idx; /* DBDC */ 161 u8 monitor_scan_type; 162 u8 band; /* 0: 2.4GHz, 1: 5GHz */ 163 u8 rsv[2]; 164 } __packed; 165 166 struct mt7915_mcu_eeprom { 167 u8 buffer_mode; 168 u8 format; 169 __le16 len; 170 } __packed; 171 172 struct mt7915_mcu_eeprom_info { 173 __le32 addr; 174 __le32 valid; 175 u8 data[16]; 176 } __packed; 177 178 struct mt7915_mcu_phy_rx_info { 179 u8 category; 180 u8 rate; 181 u8 mode; 182 u8 nsts; 183 u8 gi; 184 u8 coding; 185 u8 stbc; 186 u8 bw; 187 }; 188 189 struct mt7915_mcu_mib { 190 __le32 band; 191 __le32 offs; 192 __le64 data; 193 } __packed; 194 195 enum mt7915_chan_mib_offs { 196 /* mt7915 */ 197 MIB_BUSY_TIME = 14, 198 MIB_TX_TIME = 81, 199 MIB_RX_TIME, 200 MIB_OBSS_AIRTIME = 86, 201 /* mt7916 */ 202 MIB_BUSY_TIME_V2 = 0, 203 MIB_TX_TIME_V2 = 6, 204 MIB_RX_TIME_V2 = 8, 205 MIB_OBSS_AIRTIME_V2 = 490 206 }; 207 208 struct edca { 209 u8 queue; 210 u8 set; 211 u8 aifs; 212 u8 cw_min; 213 __le16 cw_max; 214 __le16 txop; 215 }; 216 217 struct mt7915_mcu_tx { 218 u8 total; 219 u8 action; 220 u8 valid; 221 u8 mode; 222 223 struct edca edca[IEEE80211_NUM_ACS]; 224 } __packed; 225 226 struct mt7915_mcu_muru_stats { 227 __le32 event_id; 228 struct { 229 __le32 cck_cnt; 230 __le32 ofdm_cnt; 231 __le32 htmix_cnt; 232 __le32 htgf_cnt; 233 __le32 vht_su_cnt; 234 __le32 vht_2mu_cnt; 235 __le32 vht_3mu_cnt; 236 __le32 vht_4mu_cnt; 237 __le32 he_su_cnt; 238 __le32 he_ext_su_cnt; 239 __le32 he_2ru_cnt; 240 __le32 he_2mu_cnt; 241 __le32 he_3ru_cnt; 242 __le32 he_3mu_cnt; 243 __le32 he_4ru_cnt; 244 __le32 he_4mu_cnt; 245 __le32 he_5to8ru_cnt; 246 __le32 he_9to16ru_cnt; 247 __le32 he_gtr16ru_cnt; 248 } dl; 249 250 struct { 251 __le32 hetrig_su_cnt; 252 __le32 hetrig_2ru_cnt; 253 __le32 hetrig_3ru_cnt; 254 __le32 hetrig_4ru_cnt; 255 __le32 hetrig_5to8ru_cnt; 256 __le32 hetrig_9to16ru_cnt; 257 __le32 hetrig_gtr16ru_cnt; 258 __le32 hetrig_2mu_cnt; 259 __le32 hetrig_3mu_cnt; 260 __le32 hetrig_4mu_cnt; 261 } ul; 262 }; 263 264 #define WMM_AIFS_SET BIT(0) 265 #define WMM_CW_MIN_SET BIT(1) 266 #define WMM_CW_MAX_SET BIT(2) 267 #define WMM_TXOP_SET BIT(3) 268 #define WMM_PARAM_SET GENMASK(3, 0) 269 270 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 271 #define MCU_PKT_ID 0xa0 272 273 enum { 274 MCU_FW_LOG_WM, 275 MCU_FW_LOG_WA, 276 MCU_FW_LOG_TO_HOST, 277 }; 278 279 enum { 280 MCU_TWT_AGRT_ADD, 281 MCU_TWT_AGRT_MODIFY, 282 MCU_TWT_AGRT_DELETE, 283 MCU_TWT_AGRT_TEARDOWN, 284 MCU_TWT_AGRT_GET_TSF, 285 }; 286 287 enum { 288 MCU_WA_PARAM_CMD_QUERY, 289 MCU_WA_PARAM_CMD_SET, 290 MCU_WA_PARAM_CMD_CAPABILITY, 291 MCU_WA_PARAM_CMD_DEBUG, 292 }; 293 294 enum { 295 MCU_WA_PARAM_PDMA_RX = 0x04, 296 MCU_WA_PARAM_CPU_UTIL = 0x0b, 297 MCU_WA_PARAM_RED = 0x0e, 298 }; 299 300 enum mcu_mmps_mode { 301 MCU_MMPS_STATIC, 302 MCU_MMPS_DYNAMIC, 303 MCU_MMPS_RSV, 304 MCU_MMPS_DISABLE, 305 }; 306 307 enum { 308 SCS_SEND_DATA, 309 SCS_SET_MANUAL_PD_TH, 310 SCS_CONFIG, 311 SCS_ENABLE, 312 SCS_SHOW_INFO, 313 SCS_GET_GLO_ADDR, 314 SCS_GET_GLO_ADDR_EVENT, 315 }; 316 317 struct bss_info_bmc_rate { 318 __le16 tag; 319 __le16 len; 320 __le16 bc_trans; 321 __le16 mc_trans; 322 u8 short_preamble; 323 u8 rsv[7]; 324 } __packed; 325 326 struct bss_info_ra { 327 __le16 tag; 328 __le16 len; 329 u8 op_mode; 330 u8 adhoc_en; 331 u8 short_preamble; 332 u8 tx_streams; 333 u8 rx_streams; 334 u8 algo; 335 u8 force_sgi; 336 u8 force_gf; 337 u8 ht_mode; 338 u8 has_20_sta; /* Check if any sta support GF. */ 339 u8 bss_width_trigger_events; 340 u8 vht_nss_cap; 341 u8 vht_bw_signal; /* not use */ 342 u8 vht_force_sgi; /* not use */ 343 u8 se_off; 344 u8 antenna_idx; 345 u8 train_up_rule; 346 u8 rsv[3]; 347 unsigned short train_up_high_thres; 348 short train_up_rule_rssi; 349 unsigned short low_traffic_thres; 350 __le16 max_phyrate; 351 __le32 phy_cap; 352 __le32 interval; 353 __le32 fast_interval; 354 } __packed; 355 356 struct bss_info_hw_amsdu { 357 __le16 tag; 358 __le16 len; 359 __le32 cmp_bitmap_0; 360 __le32 cmp_bitmap_1; 361 __le16 trig_thres; 362 u8 enable; 363 u8 rsv; 364 } __packed; 365 366 struct bss_info_color { 367 __le16 tag; 368 __le16 len; 369 u8 disable; 370 u8 color; 371 u8 rsv[2]; 372 } __packed; 373 374 struct bss_info_he { 375 __le16 tag; 376 __le16 len; 377 u8 he_pe_duration; 378 u8 vht_op_info_present; 379 __le16 he_rts_thres; 380 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 381 u8 rsv[6]; 382 } __packed; 383 384 struct bss_info_bcn { 385 __le16 tag; 386 __le16 len; 387 u8 ver; 388 u8 enable; 389 __le16 sub_ntlv; 390 } __packed __aligned(4); 391 392 struct bss_info_bcn_cntdwn { 393 __le16 tag; 394 __le16 len; 395 u8 cnt; 396 u8 rsv[3]; 397 } __packed __aligned(4); 398 399 struct bss_info_bcn_mbss { 400 #define MAX_BEACON_NUM 32 401 __le16 tag; 402 __le16 len; 403 __le32 bitmap; 404 __le16 offset[MAX_BEACON_NUM]; 405 u8 rsv[8]; 406 } __packed __aligned(4); 407 408 struct bss_info_bcn_cont { 409 __le16 tag; 410 __le16 len; 411 __le16 tim_ofs; 412 __le16 csa_ofs; 413 __le16 bcc_ofs; 414 __le16 pkt_len; 415 } __packed __aligned(4); 416 417 enum { 418 BSS_INFO_BCN_CSA, 419 BSS_INFO_BCN_BCC, 420 BSS_INFO_BCN_MBSSID, 421 BSS_INFO_BCN_CONTENT, 422 BSS_INFO_BCN_MAX 423 }; 424 425 enum { 426 RATE_PARAM_FIXED = 3, 427 RATE_PARAM_MMPS_UPDATE = 5, 428 RATE_PARAM_FIXED_HE_LTF = 7, 429 RATE_PARAM_FIXED_MCS, 430 RATE_PARAM_FIXED_GI = 11, 431 RATE_PARAM_AUTO = 20, 432 }; 433 434 #define RATE_CFG_MCS GENMASK(3, 0) 435 #define RATE_CFG_NSS GENMASK(7, 4) 436 #define RATE_CFG_GI GENMASK(11, 8) 437 #define RATE_CFG_BW GENMASK(15, 12) 438 #define RATE_CFG_STBC GENMASK(19, 16) 439 #define RATE_CFG_LDPC GENMASK(23, 20) 440 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 441 #define RATE_CFG_HE_LTF GENMASK(31, 28) 442 443 enum { 444 THERMAL_PROTECT_PARAMETER_CTRL, 445 THERMAL_PROTECT_BASIC_INFO, 446 THERMAL_PROTECT_ENABLE, 447 THERMAL_PROTECT_DISABLE, 448 THERMAL_PROTECT_DUTY_CONFIG, 449 THERMAL_PROTECT_MECH_INFO, 450 THERMAL_PROTECT_DUTY_INFO, 451 THERMAL_PROTECT_STATE_ACT, 452 }; 453 454 enum { 455 MT_BF_SOUNDING_ON = 1, 456 MT_BF_TYPE_UPDATE = 20, 457 MT_BF_MODULE_UPDATE = 25 458 }; 459 460 enum { 461 MURU_SET_ARB_OP_MODE = 14, 462 MURU_SET_PLATFORM_TYPE = 25, 463 }; 464 465 enum { 466 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 467 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 468 }; 469 470 /* tx cmd tx statistics */ 471 enum { 472 MURU_SET_TXC_TX_STATS_EN = 150, 473 MURU_GET_TXC_TX_STATS = 151, 474 }; 475 476 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 477 sizeof(struct bss_info_omac) + \ 478 sizeof(struct bss_info_basic) +\ 479 sizeof(struct bss_info_rf_ch) +\ 480 sizeof(struct bss_info_ra) + \ 481 sizeof(struct bss_info_hw_amsdu) +\ 482 sizeof(struct bss_info_he) + \ 483 sizeof(struct bss_info_bmc_rate) +\ 484 sizeof(struct bss_info_ext_bss)) 485 486 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 487 sizeof(struct bss_info_bcn_cntdwn) + \ 488 sizeof(struct bss_info_bcn_mbss) + \ 489 sizeof(struct bss_info_bcn_cont)) 490 491 #endif 492