1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 struct mt7915_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /* event table */ 27 enum { 28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 29 MCU_EVENT_FW_START = 0x01, 30 MCU_EVENT_GENERIC = 0x01, 31 MCU_EVENT_ACCESS_REG = 0x02, 32 MCU_EVENT_MT_PATCH_SEM = 0x04, 33 MCU_EVENT_CH_PRIVILEGE = 0x18, 34 MCU_EVENT_EXT = 0xed, 35 MCU_EVENT_RESTART_DL = 0xef, 36 }; 37 38 /* ext event table */ 39 enum { 40 MCU_EXT_EVENT_PS_SYNC = 0x5, 41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 44 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 46 MCU_EXT_EVENT_RATE_REPORT = 0x87, 47 }; 48 49 enum { 50 MCU_ATE_SET_TRX = 0x1, 51 MCU_ATE_SET_FREQ_OFFSET = 0xa, 52 MCU_ATE_SET_SLOT_TIME = 0x13, 53 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 54 }; 55 56 struct mt7915_mcu_rxd { 57 __le32 rxd[6]; 58 59 __le16 len; 60 __le16 pkt_type_id; 61 62 u8 eid; 63 u8 seq; 64 __le16 __rsv; 65 66 u8 ext_eid; 67 u8 __rsv1[2]; 68 u8 s2d_index; 69 }; 70 71 struct mt7915_mcu_rdd_report { 72 struct mt7915_mcu_rxd rxd; 73 74 u8 idx; 75 u8 long_detected; 76 u8 constant_prf_detected; 77 u8 staggered_prf_detected; 78 u8 radar_type_idx; 79 u8 periodic_pulse_num; 80 u8 long_pulse_num; 81 u8 hw_pulse_num; 82 83 u8 out_lpn; 84 u8 out_spn; 85 u8 out_crpn; 86 u8 out_crpw; 87 u8 out_crbn; 88 u8 out_stgpn; 89 u8 out_stgpw; 90 91 u8 rsv; 92 93 __le32 out_pri_const; 94 __le32 out_pri_stg[3]; 95 96 struct { 97 __le32 start; 98 __le16 pulse_width; 99 __le16 pulse_power; 100 u8 mdrdy_flag; 101 u8 rsv[3]; 102 } long_pulse[32]; 103 104 struct { 105 __le32 start; 106 __le16 pulse_width; 107 __le16 pulse_power; 108 u8 mdrdy_flag; 109 u8 rsv[3]; 110 } periodic_pulse[32]; 111 112 struct { 113 __le32 start; 114 __le16 pulse_width; 115 __le16 pulse_power; 116 u8 sc_pass; 117 u8 sw_reset; 118 u8 mdrdy_flag; 119 u8 tx_active; 120 } hw_pulse[32]; 121 } __packed; 122 123 struct mt7915_mcu_eeprom { 124 u8 buffer_mode; 125 u8 format; 126 __le16 len; 127 } __packed; 128 129 struct mt7915_mcu_eeprom_info { 130 __le32 addr; 131 __le32 valid; 132 u8 data[16]; 133 } __packed; 134 135 struct mt7915_mcu_ra_info { 136 struct mt7915_mcu_rxd rxd; 137 138 __le32 event_id; 139 __le16 wlan_idx; 140 __le16 ru_idx; 141 __le16 direction; 142 __le16 dump_group; 143 144 __le32 suggest_rate; 145 __le32 min_rate; /* for dynamic sounding */ 146 __le32 max_rate; /* for dynamic sounding */ 147 __le32 init_rate_down_rate; 148 149 __le16 curr_rate; 150 __le16 init_rate_down_total; 151 __le16 init_rate_down_succ; 152 __le16 success; 153 __le16 attempts; 154 155 __le16 prev_rate; 156 __le16 prob_up_rate; 157 u8 no_rate_up_cnt; 158 u8 ppdu_cnt; 159 u8 gi; 160 161 u8 try_up_fail; 162 u8 try_up_total; 163 u8 suggest_wf; 164 u8 try_up_check; 165 u8 prob_up_period; 166 u8 prob_down_pending; 167 } __packed; 168 169 170 struct mt7915_mcu_phy_rx_info { 171 u8 category; 172 u8 rate; 173 u8 mode; 174 u8 nsts; 175 u8 gi; 176 u8 coding; 177 u8 stbc; 178 u8 bw; 179 }; 180 181 #define MT_RA_RATE_NSS GENMASK(8, 6) 182 #define MT_RA_RATE_MCS GENMASK(3, 0) 183 #define MT_RA_RATE_TX_MODE GENMASK(12, 9) 184 #define MT_RA_RATE_DCM_EN BIT(4) 185 #define MT_RA_RATE_BW GENMASK(14, 13) 186 187 struct edca { 188 u8 queue; 189 u8 set; 190 u8 aifs; 191 u8 cw_min; 192 __le16 cw_max; 193 __le16 txop; 194 }; 195 196 struct mt7915_mcu_tx { 197 u8 total; 198 u8 action; 199 u8 valid; 200 u8 mode; 201 202 struct edca edca[IEEE80211_NUM_ACS]; 203 } __packed; 204 205 #define WMM_AIFS_SET BIT(0) 206 #define WMM_CW_MIN_SET BIT(1) 207 #define WMM_CW_MAX_SET BIT(2) 208 #define WMM_TXOP_SET BIT(3) 209 #define WMM_PARAM_SET GENMASK(3, 0) 210 211 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 212 #define MCU_PKT_ID 0xa0 213 214 enum { 215 MCU_Q_QUERY, 216 MCU_Q_SET, 217 MCU_Q_RESERVED, 218 MCU_Q_NA 219 }; 220 221 enum { 222 MCU_S2D_H2N, 223 MCU_S2D_C2N, 224 MCU_S2D_H2C, 225 MCU_S2D_H2CN 226 }; 227 228 229 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 230 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 231 #define __MCU_CMD_FIELD_QUERY BIT(16) 232 #define __MCU_CMD_FIELD_WA BIT(17) 233 234 enum { 235 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 236 MCU_CMD_FW_START_REQ = 0x02, 237 MCU_CMD_INIT_ACCESS_REG = 0x3, 238 MCU_CMD_NIC_POWER_CTRL = 0x4, 239 MCU_CMD_PATCH_START_REQ = 0x05, 240 MCU_CMD_PATCH_FINISH_REQ = 0x07, 241 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 242 MCU_CMD_WA_PARAM = 0xC4, 243 MCU_CMD_EXT_CID = 0xED, 244 MCU_CMD_FW_SCATTER = 0xEE, 245 MCU_CMD_RESTART_DL_REQ = 0xEF, 246 }; 247 248 enum { 249 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 250 MCU_EXT_CMD_RF_TEST = 0x04, 251 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 252 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 253 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 254 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 255 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 256 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 257 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 258 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 259 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 260 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 261 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 262 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 263 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 264 MCU_EXT_CMD_ATE_CTRL = 0x3d, 265 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 266 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 267 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 268 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 269 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 270 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 271 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 272 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 273 MCU_EXT_CMD_SCS_CTRL = 0x82, 274 MCU_EXT_CMD_RATE_CTRL = 0x87, 275 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 276 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 277 MCU_EXT_CMD_SET_SPR = 0xa8, 278 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 279 }; 280 281 enum { 282 MCU_WA_PARAM_CMD_QUERY, 283 MCU_WA_PARAM_CMD_SET, 284 MCU_WA_PARAM_CMD_CAPABILITY, 285 MCU_WA_PARAM_CMD_DEBUG, 286 }; 287 288 enum { 289 MCU_WA_PARAM_RED = 0x0e, 290 }; 291 292 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, MCU_CMD_##_t) 293 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 294 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 295 MCU_EXT_CMD_##_t)) 296 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 297 298 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 299 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 300 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 301 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 302 MCU_WA_PARAM_CMD_##_t)) 303 304 enum { 305 PATCH_SEM_RELEASE, 306 PATCH_SEM_GET 307 }; 308 309 enum { 310 PATCH_NOT_DL_SEM_FAIL, 311 PATCH_IS_DL, 312 PATCH_NOT_DL_SEM_SUCCESS, 313 PATCH_REL_SEM_SUCCESS 314 }; 315 316 enum { 317 FW_STATE_INITIAL, 318 FW_STATE_FW_DOWNLOAD, 319 FW_STATE_NORMAL_OPERATION, 320 FW_STATE_NORMAL_TRX, 321 FW_STATE_WACPU_RDY = 7 322 }; 323 324 enum { 325 EE_MODE_EFUSE, 326 EE_MODE_BUFFER, 327 }; 328 329 enum { 330 EE_FORMAT_BIN, 331 EE_FORMAT_WHOLE, 332 EE_FORMAT_MULTIPLE, 333 }; 334 335 enum { 336 MCU_PHY_STATE_TX_RATE, 337 MCU_PHY_STATE_RX_RATE, 338 MCU_PHY_STATE_RSSI, 339 MCU_PHY_STATE_CONTENTION_RX_RATE, 340 MCU_PHY_STATE_OFDMLQ_CNINFO, 341 }; 342 343 #define STA_TYPE_STA BIT(0) 344 #define STA_TYPE_AP BIT(1) 345 #define STA_TYPE_ADHOC BIT(2) 346 #define STA_TYPE_WDS BIT(4) 347 #define STA_TYPE_BC BIT(5) 348 349 #define NETWORK_INFRA BIT(16) 350 #define NETWORK_P2P BIT(17) 351 #define NETWORK_IBSS BIT(18) 352 #define NETWORK_WDS BIT(21) 353 354 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 355 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 356 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 357 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 358 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 359 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 360 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 361 362 #define CONN_STATE_DISCONNECT 0 363 #define CONN_STATE_CONNECT 1 364 #define CONN_STATE_PORT_SECURE 2 365 366 enum { 367 DEV_INFO_ACTIVE, 368 DEV_INFO_MAX_NUM 369 }; 370 371 enum { 372 SCS_SEND_DATA, 373 SCS_SET_MANUAL_PD_TH, 374 SCS_CONFIG, 375 SCS_ENABLE, 376 SCS_SHOW_INFO, 377 SCS_GET_GLO_ADDR, 378 SCS_GET_GLO_ADDR_EVENT, 379 }; 380 381 enum { 382 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 383 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 384 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 385 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 386 CMD_CBW_10MHZ, 387 CMD_CBW_5MHZ, 388 CMD_CBW_8080MHZ, 389 390 CMD_HE_MCS_BW80 = 0, 391 CMD_HE_MCS_BW160, 392 CMD_HE_MCS_BW8080, 393 CMD_HE_MCS_BW_NUM 394 }; 395 396 struct tlv { 397 __le16 tag; 398 __le16 len; 399 } __packed; 400 401 struct bss_info_omac { 402 __le16 tag; 403 __le16 len; 404 u8 hw_bss_idx; 405 u8 omac_idx; 406 u8 band_idx; 407 u8 rsv0; 408 __le32 conn_type; 409 u32 rsv1; 410 } __packed; 411 412 struct bss_info_basic { 413 __le16 tag; 414 __le16 len; 415 __le32 network_type; 416 u8 active; 417 u8 rsv0; 418 __le16 bcn_interval; 419 u8 bssid[ETH_ALEN]; 420 u8 wmm_idx; 421 u8 dtim_period; 422 u8 bmc_wcid_lo; 423 u8 cipher; 424 u8 phy_mode; 425 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 426 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 427 u8 bmc_wcid_hi; /* high Byte and version */ 428 u8 rsv[2]; 429 } __packed; 430 431 struct bss_info_rf_ch { 432 __le16 tag; 433 __le16 len; 434 u8 pri_ch; 435 u8 center_ch0; 436 u8 center_ch1; 437 u8 bw; 438 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 439 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 440 u8 rsv[2]; 441 } __packed; 442 443 struct bss_info_ext_bss { 444 __le16 tag; 445 __le16 len; 446 __le32 mbss_tsf_offset; /* in unit of us */ 447 u8 rsv[8]; 448 } __packed; 449 450 struct bss_info_bmc_rate { 451 __le16 tag; 452 __le16 len; 453 __le16 bc_trans; 454 __le16 mc_trans; 455 u8 short_preamble; 456 u8 rsv[7]; 457 } __packed; 458 459 struct bss_info_ra { 460 __le16 tag; 461 __le16 len; 462 u8 op_mode; 463 u8 adhoc_en; 464 u8 short_preamble; 465 u8 tx_streams; 466 u8 rx_streams; 467 u8 algo; 468 u8 force_sgi; 469 u8 force_gf; 470 u8 ht_mode; 471 u8 has_20_sta; /* Check if any sta support GF. */ 472 u8 bss_width_trigger_events; 473 u8 vht_nss_cap; 474 u8 vht_bw_signal; /* not use */ 475 u8 vht_force_sgi; /* not use */ 476 u8 se_off; 477 u8 antenna_idx; 478 u8 train_up_rule; 479 u8 rsv[3]; 480 unsigned short train_up_high_thres; 481 short train_up_rule_rssi; 482 unsigned short low_traffic_thres; 483 __le16 max_phyrate; 484 __le32 phy_cap; 485 __le32 interval; 486 __le32 fast_interval; 487 } __packed; 488 489 struct bss_info_hw_amsdu { 490 __le16 tag; 491 __le16 len; 492 __le32 cmp_bitmap_0; 493 __le32 cmp_bitmap_1; 494 __le16 trig_thres; 495 u8 enable; 496 u8 rsv; 497 } __packed; 498 499 struct bss_info_he { 500 __le16 tag; 501 __le16 len; 502 u8 he_pe_duration; 503 u8 vht_op_info_present; 504 __le16 he_rts_thres; 505 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 506 u8 rsv[6]; 507 } __packed; 508 509 struct bss_info_bcn { 510 __le16 tag; 511 __le16 len; 512 u8 ver; 513 u8 enable; 514 __le16 sub_ntlv; 515 } __packed __aligned(4); 516 517 struct bss_info_bcn_csa { 518 __le16 tag; 519 __le16 len; 520 u8 cnt; 521 u8 rsv[3]; 522 } __packed __aligned(4); 523 524 struct bss_info_bcn_bcc { 525 __le16 tag; 526 __le16 len; 527 u8 cnt; 528 u8 rsv[3]; 529 } __packed __aligned(4); 530 531 struct bss_info_bcn_mbss { 532 #define MAX_BEACON_NUM 32 533 __le16 tag; 534 __le16 len; 535 __le32 bitmap; 536 __le16 offset[MAX_BEACON_NUM]; 537 u8 rsv[8]; 538 } __packed __aligned(4); 539 540 struct bss_info_bcn_cont { 541 __le16 tag; 542 __le16 len; 543 __le16 tim_ofs; 544 __le16 csa_ofs; 545 __le16 bcc_ofs; 546 __le16 pkt_len; 547 } __packed __aligned(4); 548 549 enum { 550 BSS_INFO_BCN_CSA, 551 BSS_INFO_BCN_BCC, 552 BSS_INFO_BCN_MBSSID, 553 BSS_INFO_BCN_CONTENT, 554 BSS_INFO_BCN_MAX 555 }; 556 557 enum { 558 BSS_INFO_OMAC, 559 BSS_INFO_BASIC, 560 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 561 BSS_INFO_PM, /* sta only */ 562 BSS_INFO_UAPSD, /* sta only */ 563 BSS_INFO_ROAM_DETECT, /* obsoleted */ 564 BSS_INFO_LQ_RM, /* obsoleted */ 565 BSS_INFO_EXT_BSS, 566 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 567 BSS_INFO_SYNC_MODE, /* obsoleted */ 568 BSS_INFO_RA, 569 BSS_INFO_HW_AMSDU, 570 BSS_INFO_BSS_COLOR, 571 BSS_INFO_HE_BASIC, 572 BSS_INFO_PROTECT_INFO, 573 BSS_INFO_OFFLOAD, 574 BSS_INFO_11V_MBSSID, 575 BSS_INFO_MAX_NUM 576 }; 577 578 enum { 579 WTBL_RESET_AND_SET = 1, 580 WTBL_SET, 581 WTBL_QUERY, 582 WTBL_RESET_ALL 583 }; 584 585 struct wtbl_req_hdr { 586 u8 wlan_idx_lo; 587 u8 operation; 588 __le16 tlv_num; 589 u8 wlan_idx_hi; 590 u8 rsv[3]; 591 } __packed; 592 593 struct wtbl_generic { 594 __le16 tag; 595 __le16 len; 596 u8 peer_addr[ETH_ALEN]; 597 u8 muar_idx; 598 u8 skip_tx; 599 u8 cf_ack; 600 u8 qos; 601 u8 mesh; 602 u8 adm; 603 __le16 partial_aid; 604 u8 baf_en; 605 u8 aad_om; 606 } __packed; 607 608 struct wtbl_rx { 609 __le16 tag; 610 __le16 len; 611 u8 rcid; 612 u8 rca1; 613 u8 rca2; 614 u8 rv; 615 u8 rsv[4]; 616 } __packed; 617 618 struct wtbl_ht { 619 __le16 tag; 620 __le16 len; 621 u8 ht; 622 u8 ldpc; 623 u8 af; 624 u8 mm; 625 u8 rsv[4]; 626 } __packed; 627 628 struct wtbl_vht { 629 __le16 tag; 630 __le16 len; 631 u8 ldpc; 632 u8 dyn_bw; 633 u8 vht; 634 u8 txop_ps; 635 u8 rsv[4]; 636 } __packed; 637 638 struct wtbl_hdr_trans { 639 __le16 tag; 640 __le16 len; 641 u8 to_ds; 642 u8 from_ds; 643 u8 no_rx_trans; 644 u8 _rsv; 645 }; 646 647 enum { 648 MT_BA_TYPE_INVALID, 649 MT_BA_TYPE_ORIGINATOR, 650 MT_BA_TYPE_RECIPIENT 651 }; 652 653 enum { 654 RST_BA_MAC_TID_MATCH, 655 RST_BA_MAC_MATCH, 656 RST_BA_NO_MATCH 657 }; 658 659 struct wtbl_ba { 660 __le16 tag; 661 __le16 len; 662 /* common */ 663 u8 tid; 664 u8 ba_type; 665 u8 rsv0[2]; 666 /* originator only */ 667 __le16 sn; 668 u8 ba_en; 669 u8 ba_winsize_idx; 670 __le16 ba_winsize; 671 /* recipient only */ 672 u8 peer_addr[ETH_ALEN]; 673 u8 rst_ba_tid; 674 u8 rst_ba_sel; 675 u8 rst_ba_sb; 676 u8 band_idx; 677 u8 rsv1[4]; 678 } __packed; 679 680 struct wtbl_smps { 681 __le16 tag; 682 __le16 len; 683 u8 smps; 684 u8 rsv[3]; 685 } __packed; 686 687 enum { 688 WTBL_GENERIC, 689 WTBL_RX, 690 WTBL_HT, 691 WTBL_VHT, 692 WTBL_PEER_PS, /* not used */ 693 WTBL_TX_PS, 694 WTBL_HDR_TRANS, 695 WTBL_SEC_KEY, 696 WTBL_BA, 697 WTBL_RDG, /* obsoleted */ 698 WTBL_PROTECT, /* not used */ 699 WTBL_CLEAR, /* not used */ 700 WTBL_BF, 701 WTBL_SMPS, 702 WTBL_RAW_DATA, /* debug only */ 703 WTBL_PN, 704 WTBL_SPE, 705 WTBL_MAX_NUM 706 }; 707 708 struct sta_ntlv_hdr { 709 u8 rsv[2]; 710 __le16 tlv_num; 711 } __packed; 712 713 struct sta_req_hdr { 714 u8 bss_idx; 715 u8 wlan_idx_lo; 716 __le16 tlv_num; 717 u8 is_tlv_append; 718 u8 muar_idx; 719 u8 wlan_idx_hi; 720 u8 rsv; 721 } __packed; 722 723 struct sta_rec_basic { 724 __le16 tag; 725 __le16 len; 726 __le32 conn_type; 727 u8 conn_state; 728 u8 qos; 729 __le16 aid; 730 u8 peer_addr[ETH_ALEN]; 731 __le16 extra_info; 732 } __packed; 733 734 struct sta_rec_ht { 735 __le16 tag; 736 __le16 len; 737 __le16 ht_cap; 738 u16 rsv; 739 } __packed; 740 741 struct sta_rec_vht { 742 __le16 tag; 743 __le16 len; 744 __le32 vht_cap; 745 __le16 vht_rx_mcs_map; 746 __le16 vht_tx_mcs_map; 747 u8 rts_bw_sig; 748 u8 rsv[3]; 749 } __packed; 750 751 struct sta_rec_uapsd { 752 __le16 tag; 753 __le16 len; 754 u8 dac_map; 755 u8 tac_map; 756 u8 max_sp; 757 u8 rsv0; 758 __le16 listen_interval; 759 u8 rsv1[2]; 760 } __packed; 761 762 struct sta_rec_muru { 763 __le16 tag; 764 __le16 len; 765 766 struct { 767 bool ofdma_dl_en; 768 bool ofdma_ul_en; 769 bool mimo_dl_en; 770 bool mimo_ul_en; 771 u8 rsv[4]; 772 } cfg; 773 774 struct { 775 u8 punc_pream_rx; 776 bool he_20m_in_40m_2g; 777 bool he_20m_in_160m; 778 bool he_80m_in_160m; 779 bool lt16_sigb; 780 bool rx_su_comp_sigb; 781 bool rx_su_non_comp_sigb; 782 u8 rsv; 783 } ofdma_dl; 784 785 struct { 786 u8 t_frame_dur; 787 u8 mu_cascading; 788 u8 uo_ra; 789 u8 he_2x996_tone; 790 u8 rx_t_frame_11ac; 791 u8 rsv[3]; 792 } ofdma_ul; 793 794 struct { 795 bool vht_mu_bfee; 796 bool partial_bw_dl_mimo; 797 u8 rsv[2]; 798 } mimo_dl; 799 800 struct { 801 bool full_ul_mimo; 802 bool partial_ul_mimo; 803 u8 rsv[2]; 804 } mimo_ul; 805 } __packed; 806 807 struct sta_rec_he { 808 __le16 tag; 809 __le16 len; 810 811 __le32 he_cap; 812 813 u8 t_frame_dur; 814 u8 max_ampdu_exp; 815 u8 bw_set; 816 u8 device_class; 817 u8 dcm_tx_mode; 818 u8 dcm_tx_max_nss; 819 u8 dcm_rx_mode; 820 u8 dcm_rx_max_nss; 821 u8 dcm_max_ru; 822 u8 punc_pream_rx; 823 u8 pkt_ext; 824 u8 rsv1; 825 826 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 827 828 u8 rsv2[2]; 829 } __packed; 830 831 struct sta_rec_ba { 832 __le16 tag; 833 __le16 len; 834 u8 tid; 835 u8 ba_type; 836 u8 amsdu; 837 u8 ba_en; 838 __le16 ssn; 839 __le16 winsize; 840 } __packed; 841 842 struct sta_rec_amsdu { 843 __le16 tag; 844 __le16 len; 845 u8 max_amsdu_num; 846 u8 max_mpdu_size; 847 u8 amsdu_en; 848 u8 rsv; 849 } __packed; 850 851 struct sec_key { 852 u8 cipher_id; 853 u8 cipher_len; 854 u8 key_id; 855 u8 key_len; 856 u8 key[32]; 857 } __packed; 858 859 struct sta_rec_sec { 860 __le16 tag; 861 __le16 len; 862 u8 add; 863 u8 n_cipher; 864 u8 rsv[2]; 865 866 struct sec_key key[2]; 867 } __packed; 868 869 struct ra_phy { 870 u8 type; 871 u8 flag; 872 u8 stbc; 873 u8 sgi; 874 u8 bw; 875 u8 ldpc; 876 u8 mcs; 877 u8 nss; 878 u8 he_ltf; 879 }; 880 881 struct sta_rec_ra { 882 __le16 tag; 883 __le16 len; 884 885 u8 valid; 886 u8 auto_rate; 887 u8 phy_mode; 888 u8 channel; 889 u8 bw; 890 u8 disable_cck; 891 u8 ht_mcs32; 892 u8 ht_gf; 893 u8 ht_mcs[4]; 894 u8 mmps_mode; 895 u8 gband_256; 896 u8 af; 897 u8 auth_wapi_mode; 898 u8 rate_len; 899 900 u8 supp_mode; 901 u8 supp_cck_rate; 902 u8 supp_ofdm_rate; 903 __le32 supp_ht_mcs; 904 __le16 supp_vht_mcs[4]; 905 906 u8 op_mode; 907 u8 op_vht_chan_width; 908 u8 op_vht_rx_nss; 909 u8 op_vht_rx_nss_type; 910 911 __le32 sta_status; 912 913 struct ra_phy phy; 914 } __packed; 915 916 struct sta_rec_ra_fixed { 917 __le16 tag; 918 __le16 len; 919 920 __le32 field; 921 u8 op_mode; 922 u8 op_vht_chan_width; 923 u8 op_vht_rx_nss; 924 u8 op_vht_rx_nss_type; 925 926 struct ra_phy phy; 927 928 u8 spe_en; 929 u8 short_preamble; 930 u8 is_5g; 931 u8 mmps_mode; 932 } __packed; 933 934 #define RATE_PARAM_FIXED 3 935 #define RATE_PARAM_AUTO 20 936 #define RATE_CFG_MCS GENMASK(3, 0) 937 #define RATE_CFG_NSS GENMASK(7, 4) 938 #define RATE_CFG_GI GENMASK(11, 8) 939 #define RATE_CFG_BW GENMASK(15, 12) 940 #define RATE_CFG_STBC GENMASK(19, 16) 941 #define RATE_CFG_LDPC GENMASK(23, 20) 942 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 943 944 struct sta_rec_bf { 945 __le16 tag; 946 __le16 len; 947 948 __le16 pfmu; /* 0xffff: no access right for PFMU */ 949 bool su_mu; /* 0: SU, 1: MU */ 950 u8 bf_cap; /* 0: iBF, 1: eBF */ 951 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 952 u8 ndpa_rate; 953 u8 ndp_rate; 954 u8 rept_poll_rate; 955 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 956 u8 nc; 957 u8 nr; 958 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 959 960 u8 mem_total; 961 u8 mem_20m; 962 struct { 963 u8 row; 964 u8 col: 6, row_msb: 2; 965 } mem[4]; 966 967 __le16 smart_ant; 968 u8 se_idx; 969 u8 auto_sounding; /* b7: low traffic indicator 970 * b6: Stop sounding for this entry 971 * b5 ~ b0: postpone sounding 972 */ 973 u8 ibf_timeout; 974 u8 ibf_dbw; 975 u8 ibf_ncol; 976 u8 ibf_nrow; 977 u8 nr_bw160; 978 u8 nc_bw160; 979 u8 ru_start_idx; 980 u8 ru_end_idx; 981 982 bool trigger_su; 983 bool trigger_mu; 984 bool ng16_su; 985 bool ng16_mu; 986 bool codebook42_su; 987 bool codebook75_mu; 988 989 u8 he_ltf; 990 u8 rsv[2]; 991 } __packed; 992 993 struct sta_rec_bfee { 994 __le16 tag; 995 __le16 len; 996 bool fb_identity_matrix; /* 1: feedback identity matrix */ 997 bool ignore_feedback; /* 1: ignore */ 998 u8 rsv[2]; 999 } __packed; 1000 1001 enum { 1002 STA_REC_BASIC, 1003 STA_REC_RA, 1004 STA_REC_RA_CMM_INFO, 1005 STA_REC_RA_UPDATE, 1006 STA_REC_BF, 1007 STA_REC_AMSDU, 1008 STA_REC_BA, 1009 STA_REC_RED, /* not used */ 1010 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 1011 STA_REC_HT, 1012 STA_REC_VHT, 1013 STA_REC_APPS, 1014 STA_REC_KEY, 1015 STA_REC_WTBL, 1016 STA_REC_HE, 1017 STA_REC_HW_AMSDU, 1018 STA_REC_WTBL_AADOM, 1019 STA_REC_KEY_V2, 1020 STA_REC_MURU, 1021 STA_REC_MUEDCA, 1022 STA_REC_BFEE, 1023 STA_REC_MAX_NUM 1024 }; 1025 1026 enum mt7915_cipher_type { 1027 MT_CIPHER_NONE, 1028 MT_CIPHER_WEP40, 1029 MT_CIPHER_WEP104, 1030 MT_CIPHER_WEP128, 1031 MT_CIPHER_TKIP, 1032 MT_CIPHER_AES_CCMP, 1033 MT_CIPHER_CCMP_256, 1034 MT_CIPHER_GCMP, 1035 MT_CIPHER_GCMP_256, 1036 MT_CIPHER_WAPI, 1037 MT_CIPHER_BIP_CMAC_128, 1038 }; 1039 1040 enum { 1041 CH_SWITCH_NORMAL = 0, 1042 CH_SWITCH_SCAN = 3, 1043 CH_SWITCH_MCC = 4, 1044 CH_SWITCH_DFS = 5, 1045 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1046 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1047 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1048 CH_SWITCH_SCAN_BYPASS_DPD = 9 1049 }; 1050 1051 enum { 1052 THERMAL_SENSOR_TEMP_QUERY, 1053 THERMAL_SENSOR_MANUAL_CTRL, 1054 THERMAL_SENSOR_INFO_QUERY, 1055 THERMAL_SENSOR_TASK_CTRL, 1056 }; 1057 1058 enum { 1059 MT_EBF = BIT(0), /* explicit beamforming */ 1060 MT_IBF = BIT(1) /* implicit beamforming */ 1061 }; 1062 1063 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 1064 sizeof(struct wtbl_generic) + \ 1065 sizeof(struct wtbl_rx) + \ 1066 sizeof(struct wtbl_ht) + \ 1067 sizeof(struct wtbl_vht) + \ 1068 sizeof(struct wtbl_hdr_trans) +\ 1069 sizeof(struct wtbl_ba) + \ 1070 sizeof(struct wtbl_smps)) 1071 1072 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1073 sizeof(struct sta_rec_basic) + \ 1074 sizeof(struct sta_rec_ht) + \ 1075 sizeof(struct sta_rec_he) + \ 1076 sizeof(struct sta_rec_ba) + \ 1077 sizeof(struct sta_rec_vht) + \ 1078 sizeof(struct sta_rec_uapsd) + \ 1079 sizeof(struct sta_rec_amsdu) + \ 1080 sizeof(struct tlv) + \ 1081 MT7915_WTBL_UPDATE_MAX_SIZE) 1082 1083 #define MT7915_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 1084 sizeof(struct wtbl_ba)) 1085 1086 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 1087 sizeof(struct bss_info_omac) + \ 1088 sizeof(struct bss_info_basic) +\ 1089 sizeof(struct bss_info_rf_ch) +\ 1090 sizeof(struct bss_info_ra) + \ 1091 sizeof(struct bss_info_hw_amsdu) +\ 1092 sizeof(struct bss_info_he) + \ 1093 sizeof(struct bss_info_bmc_rate) +\ 1094 sizeof(struct bss_info_ext_bss)) 1095 1096 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 1097 sizeof(struct bss_info_bcn_csa) + \ 1098 sizeof(struct bss_info_bcn_bcc) + \ 1099 sizeof(struct bss_info_bcn_mbss) + \ 1100 sizeof(struct bss_info_bcn_cont)) 1101 1102 #define PHY_MODE_A BIT(0) 1103 #define PHY_MODE_B BIT(1) 1104 #define PHY_MODE_G BIT(2) 1105 #define PHY_MODE_GN BIT(3) 1106 #define PHY_MODE_AN BIT(4) 1107 #define PHY_MODE_AC BIT(5) 1108 #define PHY_MODE_AX_24G BIT(6) 1109 #define PHY_MODE_AX_5G BIT(7) 1110 #define PHY_MODE_AX_6G BIT(8) 1111 1112 #define MODE_CCK BIT(0) 1113 #define MODE_OFDM BIT(1) 1114 #define MODE_HT BIT(2) 1115 #define MODE_VHT BIT(3) 1116 #define MODE_HE BIT(4) 1117 1118 #define STA_CAP_WMM BIT(0) 1119 #define STA_CAP_SGI_20 BIT(4) 1120 #define STA_CAP_SGI_40 BIT(5) 1121 #define STA_CAP_TX_STBC BIT(6) 1122 #define STA_CAP_RX_STBC BIT(7) 1123 #define STA_CAP_VHT_SGI_80 BIT(16) 1124 #define STA_CAP_VHT_SGI_160 BIT(17) 1125 #define STA_CAP_VHT_TX_STBC BIT(18) 1126 #define STA_CAP_VHT_RX_STBC BIT(19) 1127 #define STA_CAP_VHT_LDPC BIT(23) 1128 #define STA_CAP_LDPC BIT(24) 1129 #define STA_CAP_HT BIT(26) 1130 #define STA_CAP_VHT BIT(27) 1131 #define STA_CAP_HE BIT(28) 1132 1133 /* HE MAC */ 1134 #define STA_REC_HE_CAP_HTC BIT(0) 1135 #define STA_REC_HE_CAP_BQR BIT(1) 1136 #define STA_REC_HE_CAP_BSR BIT(2) 1137 #define STA_REC_HE_CAP_OM BIT(3) 1138 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 1139 /* HE PHY */ 1140 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 1141 #define STA_REC_HE_CAP_LDPC BIT(6) 1142 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 1143 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 1144 /* STBC */ 1145 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 1146 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 1147 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 1148 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 1149 /* GI */ 1150 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 1151 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 1152 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 1153 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 1154 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 1155 /* 242 TONE */ 1156 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 1157 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 1158 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 1159 1160 #endif 1161