1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "coredump.h" 7 #include "mt7915.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 13 14 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 15 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 16 .radar_pattern = { 17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 25 }, 26 }; 27 28 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 29 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 30 .radar_pattern = { 31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 33 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 34 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 35 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 36 }, 37 }; 38 39 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 41 .radar_pattern = { 42 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 43 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 44 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 45 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 46 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 47 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 48 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 49 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 50 }, 51 }; 52 53 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 54 u16 idx, bool unicast) 55 { 56 struct mt7915_sta *sta; 57 struct mt76_wcid *wcid; 58 59 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 60 return NULL; 61 62 wcid = rcu_dereference(dev->mt76.wcid[idx]); 63 if (unicast || !wcid) 64 return wcid; 65 66 if (!wcid->sta) 67 return NULL; 68 69 sta = container_of(wcid, struct mt7915_sta, wcid); 70 if (!sta->vif) 71 return NULL; 72 73 return &sta->vif->sta.wcid; 74 } 75 76 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 77 { 78 } 79 80 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 81 { 82 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 83 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 84 85 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 86 0, 5000); 87 } 88 89 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 90 { 91 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 92 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 93 94 return MT_WTBL_LMAC_OFFS(wcid, dw); 95 } 96 97 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 98 { 99 static const u8 ac_to_tid[] = { 100 [IEEE80211_AC_BE] = 0, 101 [IEEE80211_AC_BK] = 1, 102 [IEEE80211_AC_VI] = 4, 103 [IEEE80211_AC_VO] = 6 104 }; 105 struct ieee80211_sta *sta; 106 struct mt7915_sta *msta; 107 struct rate_info *rate; 108 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 109 LIST_HEAD(sta_poll_list); 110 int i; 111 112 spin_lock_bh(&dev->sta_poll_lock); 113 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 114 spin_unlock_bh(&dev->sta_poll_lock); 115 116 rcu_read_lock(); 117 118 while (true) { 119 bool clear = false; 120 u32 addr, val; 121 u16 idx; 122 s8 rssi[4]; 123 u8 bw; 124 125 spin_lock_bh(&dev->sta_poll_lock); 126 if (list_empty(&sta_poll_list)) { 127 spin_unlock_bh(&dev->sta_poll_lock); 128 break; 129 } 130 msta = list_first_entry(&sta_poll_list, 131 struct mt7915_sta, poll_list); 132 list_del_init(&msta->poll_list); 133 spin_unlock_bh(&dev->sta_poll_lock); 134 135 idx = msta->wcid.idx; 136 137 /* refresh peer's airtime reporting */ 138 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 139 140 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 141 u32 tx_last = msta->airtime_ac[i]; 142 u32 rx_last = msta->airtime_ac[i + 4]; 143 144 msta->airtime_ac[i] = mt76_rr(dev, addr); 145 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 146 147 tx_time[i] = msta->airtime_ac[i] - tx_last; 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 queue = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[queue]; 170 u32 rx_cur = rx_time[queue]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 217 /* get signal strength of resp frames (CTS/BA/ACK) */ 218 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 219 val = mt76_rr(dev, addr); 220 221 rssi[0] = to_rssi(GENMASK(7, 0), val); 222 rssi[1] = to_rssi(GENMASK(15, 8), val); 223 rssi[2] = to_rssi(GENMASK(23, 16), val); 224 rssi[3] = to_rssi(GENMASK(31, 14), val); 225 226 msta->ack_signal = 227 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 228 229 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 230 } 231 232 rcu_read_unlock(); 233 } 234 235 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 236 struct ieee80211_vif *vif, bool enable) 237 { 238 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 239 u32 addr; 240 241 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 242 if (enable) 243 mt76_set(dev, addr, BIT(5)); 244 else 245 mt76_clear(dev, addr, BIT(5)); 246 } 247 248 static void 249 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 250 struct mt7915_sta *msta, struct sk_buff *skb, 251 u32 info) 252 { 253 struct ieee80211_vif *vif; 254 struct wireless_dev *wdev; 255 256 if (!msta || !msta->vif) 257 return; 258 259 if (!(q->flags & MT_QFLAG_WED) || 260 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) != MT76_WED_Q_RX) 261 return; 262 263 if (!(info & MT_DMA_INFO_PPE_VLD)) 264 return; 265 266 vif = container_of((void *)msta->vif, struct ieee80211_vif, 267 drv_priv); 268 wdev = ieee80211_vif_to_wdev(vif); 269 skb->dev = wdev->netdev; 270 271 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 272 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 273 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 274 } 275 276 static int 277 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 278 enum mt76_rxq_id q, u32 *info) 279 { 280 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 281 struct mt76_phy *mphy = &dev->mt76.phy; 282 struct mt7915_phy *phy = &dev->phy; 283 struct ieee80211_supported_band *sband; 284 __le32 *rxd = (__le32 *)skb->data; 285 __le32 *rxv = NULL; 286 u32 rxd0 = le32_to_cpu(rxd[0]); 287 u32 rxd1 = le32_to_cpu(rxd[1]); 288 u32 rxd2 = le32_to_cpu(rxd[2]); 289 u32 rxd3 = le32_to_cpu(rxd[3]); 290 u32 rxd4 = le32_to_cpu(rxd[4]); 291 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 292 bool unicast, insert_ccmp_hdr = false; 293 u8 remove_pad, amsdu_info; 294 u8 mode = 0, qos_ctl = 0; 295 struct mt7915_sta *msta = NULL; 296 u32 csum_status = *(u32 *)skb->cb; 297 bool hdr_trans; 298 u16 hdr_gap; 299 u16 seq_ctrl = 0; 300 __le16 fc = 0; 301 int idx; 302 303 memset(status, 0, sizeof(*status)); 304 305 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 306 mphy = dev->mt76.phys[MT_BAND1]; 307 if (!mphy) 308 return -EINVAL; 309 310 phy = mphy->priv; 311 status->phy_idx = 1; 312 } 313 314 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 315 return -EINVAL; 316 317 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 318 return -EINVAL; 319 320 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 321 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 322 return -EINVAL; 323 324 /* ICV error or CCMP/BIP/WPI MIC error */ 325 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 326 status->flag |= RX_FLAG_ONLY_MONITOR; 327 328 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 329 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 330 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 331 332 if (status->wcid) { 333 msta = container_of(status->wcid, struct mt7915_sta, wcid); 334 spin_lock_bh(&dev->sta_poll_lock); 335 if (list_empty(&msta->poll_list)) 336 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 337 spin_unlock_bh(&dev->sta_poll_lock); 338 } 339 340 status->freq = mphy->chandef.chan->center_freq; 341 status->band = mphy->chandef.chan->band; 342 if (status->band == NL80211_BAND_5GHZ) 343 sband = &mphy->sband_5g.sband; 344 else if (status->band == NL80211_BAND_6GHZ) 345 sband = &mphy->sband_6g.sband; 346 else 347 sband = &mphy->sband_2g.sband; 348 349 if (!sband->channels) 350 return -EINVAL; 351 352 if ((rxd0 & csum_mask) == csum_mask && 353 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 354 skb->ip_summed = CHECKSUM_UNNECESSARY; 355 356 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 357 status->flag |= RX_FLAG_FAILED_FCS_CRC; 358 359 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 360 status->flag |= RX_FLAG_MMIC_ERROR; 361 362 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 363 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 364 status->flag |= RX_FLAG_DECRYPTED; 365 status->flag |= RX_FLAG_IV_STRIPPED; 366 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 367 } 368 369 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 370 371 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 372 return -EINVAL; 373 374 rxd += 6; 375 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 376 u32 v0 = le32_to_cpu(rxd[0]); 377 u32 v2 = le32_to_cpu(rxd[2]); 378 379 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 380 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 381 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 382 383 rxd += 4; 384 if ((u8 *)rxd - skb->data >= skb->len) 385 return -EINVAL; 386 } 387 388 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 389 u8 *data = (u8 *)rxd; 390 391 if (status->flag & RX_FLAG_DECRYPTED) { 392 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 393 case MT_CIPHER_AES_CCMP: 394 case MT_CIPHER_CCMP_CCX: 395 case MT_CIPHER_CCMP_256: 396 insert_ccmp_hdr = 397 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 398 fallthrough; 399 case MT_CIPHER_TKIP: 400 case MT_CIPHER_TKIP_NO_MIC: 401 case MT_CIPHER_GCMP: 402 case MT_CIPHER_GCMP_256: 403 status->iv[0] = data[5]; 404 status->iv[1] = data[4]; 405 status->iv[2] = data[3]; 406 status->iv[3] = data[2]; 407 status->iv[4] = data[1]; 408 status->iv[5] = data[0]; 409 break; 410 default: 411 break; 412 } 413 } 414 rxd += 4; 415 if ((u8 *)rxd - skb->data >= skb->len) 416 return -EINVAL; 417 } 418 419 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 420 status->timestamp = le32_to_cpu(rxd[0]); 421 status->flag |= RX_FLAG_MACTIME_START; 422 423 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 424 status->flag |= RX_FLAG_AMPDU_DETAILS; 425 426 /* all subframes of an A-MPDU have the same timestamp */ 427 if (phy->rx_ampdu_ts != status->timestamp) { 428 if (!++phy->ampdu_ref) 429 phy->ampdu_ref++; 430 } 431 phy->rx_ampdu_ts = status->timestamp; 432 433 status->ampdu_ref = phy->ampdu_ref; 434 } 435 436 rxd += 2; 437 if ((u8 *)rxd - skb->data >= skb->len) 438 return -EINVAL; 439 } 440 441 /* RXD Group 3 - P-RXV */ 442 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 443 u32 v0, v1; 444 int ret; 445 446 rxv = rxd; 447 rxd += 2; 448 if ((u8 *)rxd - skb->data >= skb->len) 449 return -EINVAL; 450 451 v0 = le32_to_cpu(rxv[0]); 452 v1 = le32_to_cpu(rxv[1]); 453 454 if (v0 & MT_PRXV_HT_AD_CODE) 455 status->enc_flags |= RX_ENC_FLAG_LDPC; 456 457 status->chains = mphy->antenna_mask; 458 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 459 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 460 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 461 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 462 463 /* RXD Group 5 - C-RXV */ 464 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 465 rxd += 18; 466 if ((u8 *)rxd - skb->data >= skb->len) 467 return -EINVAL; 468 } 469 470 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 471 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 472 sband, rxv, &mode); 473 if (ret < 0) 474 return ret; 475 } 476 } 477 478 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 479 status->amsdu = !!amsdu_info; 480 if (status->amsdu) { 481 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 482 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 483 } 484 485 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 486 if (hdr_trans && ieee80211_has_morefrags(fc)) { 487 struct ieee80211_vif *vif; 488 int err; 489 490 if (!msta || !msta->vif) 491 return -EINVAL; 492 493 vif = container_of((void *)msta->vif, struct ieee80211_vif, 494 drv_priv); 495 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 496 if (err) 497 return err; 498 499 hdr_trans = false; 500 } else { 501 int pad_start = 0; 502 503 skb_pull(skb, hdr_gap); 504 if (!hdr_trans && status->amsdu) { 505 pad_start = ieee80211_get_hdrlen_from_skb(skb); 506 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 507 /* 508 * When header translation failure is indicated, 509 * the hardware will insert an extra 2-byte field 510 * containing the data length after the protocol 511 * type field. This happens either when the LLC-SNAP 512 * pattern did not match, or if a VLAN header was 513 * detected. 514 */ 515 pad_start = 12; 516 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 517 pad_start += 4; 518 else 519 pad_start = 0; 520 } 521 522 if (pad_start) { 523 memmove(skb->data + 2, skb->data, pad_start); 524 skb_pull(skb, 2); 525 } 526 } 527 528 if (!hdr_trans) { 529 struct ieee80211_hdr *hdr; 530 531 if (insert_ccmp_hdr) { 532 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 533 534 mt76_insert_ccmp_hdr(skb, key_id); 535 } 536 537 hdr = mt76_skb_get_hdr(skb); 538 fc = hdr->frame_control; 539 if (ieee80211_is_data_qos(fc)) { 540 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 541 qos_ctl = *ieee80211_get_qos_ctl(hdr); 542 } 543 } else { 544 status->flag |= RX_FLAG_8023; 545 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 546 *info); 547 } 548 549 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 550 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 551 552 if (!status->wcid || !ieee80211_is_data_qos(fc)) 553 return 0; 554 555 status->aggr = unicast && 556 !ieee80211_is_qos_nullfunc(fc); 557 status->qos_ctl = qos_ctl; 558 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 559 560 return 0; 561 } 562 563 static void 564 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 565 { 566 #ifdef CONFIG_NL80211_TESTMODE 567 struct mt7915_phy *phy = &dev->phy; 568 __le32 *rxd = (__le32 *)skb->data; 569 __le32 *rxv_hdr = rxd + 2; 570 __le32 *rxv = rxd + 4; 571 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 572 u8 band_idx; 573 s32 foe; 574 u8 snr; 575 int i; 576 577 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 578 if (band_idx && !phy->mt76->band_idx) { 579 phy = mt7915_ext_phy(dev); 580 if (!phy) 581 goto out; 582 } 583 584 rcpi = le32_to_cpu(rxv[6]); 585 ib_rssi = le32_to_cpu(rxv[7]); 586 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 587 588 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 589 if (i == 3) 590 wb_rssi = le32_to_cpu(rxv[9]); 591 592 phy->test.last_rcpi[i] = rcpi & 0xff; 593 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 594 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 595 } 596 597 v20 = le32_to_cpu(rxv[20]); 598 v21 = le32_to_cpu(rxv[21]); 599 600 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 601 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 602 603 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 604 605 phy->test.last_freq_offset = foe; 606 phy->test.last_snr = snr; 607 out: 608 #endif 609 dev_kfree_skb(skb); 610 } 611 612 static void 613 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 614 struct sk_buff *skb) 615 { 616 #ifdef CONFIG_NL80211_TESTMODE 617 struct mt76_testmode_data *td = &phy->mt76->test; 618 const struct ieee80211_rate *r; 619 u8 bw, mode, nss = td->tx_rate_nss; 620 u8 rate_idx = td->tx_rate_idx; 621 u16 rateval = 0; 622 u32 val; 623 bool cck = false; 624 int band; 625 626 if (skb != phy->mt76->test.tx_skb) 627 return; 628 629 switch (td->tx_rate_mode) { 630 case MT76_TM_TX_MODE_HT: 631 nss = 1 + (rate_idx >> 3); 632 mode = MT_PHY_TYPE_HT; 633 break; 634 case MT76_TM_TX_MODE_VHT: 635 mode = MT_PHY_TYPE_VHT; 636 break; 637 case MT76_TM_TX_MODE_HE_SU: 638 mode = MT_PHY_TYPE_HE_SU; 639 break; 640 case MT76_TM_TX_MODE_HE_EXT_SU: 641 mode = MT_PHY_TYPE_HE_EXT_SU; 642 break; 643 case MT76_TM_TX_MODE_HE_TB: 644 mode = MT_PHY_TYPE_HE_TB; 645 break; 646 case MT76_TM_TX_MODE_HE_MU: 647 mode = MT_PHY_TYPE_HE_MU; 648 break; 649 case MT76_TM_TX_MODE_CCK: 650 cck = true; 651 fallthrough; 652 case MT76_TM_TX_MODE_OFDM: 653 band = phy->mt76->chandef.chan->band; 654 if (band == NL80211_BAND_2GHZ && !cck) 655 rate_idx += 4; 656 657 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 658 val = cck ? r->hw_value_short : r->hw_value; 659 660 mode = val >> 8; 661 rate_idx = val & 0xff; 662 break; 663 default: 664 mode = MT_PHY_TYPE_OFDM; 665 break; 666 } 667 668 switch (phy->mt76->chandef.width) { 669 case NL80211_CHAN_WIDTH_40: 670 bw = 1; 671 break; 672 case NL80211_CHAN_WIDTH_80: 673 bw = 2; 674 break; 675 case NL80211_CHAN_WIDTH_80P80: 676 case NL80211_CHAN_WIDTH_160: 677 bw = 3; 678 break; 679 default: 680 bw = 0; 681 break; 682 } 683 684 if (td->tx_rate_stbc && nss == 1) { 685 nss++; 686 rateval |= MT_TX_RATE_STBC; 687 } 688 689 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 690 FIELD_PREP(MT_TX_RATE_MODE, mode) | 691 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 692 693 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 694 695 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 696 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 697 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 698 699 val = MT_TXD6_FIXED_BW | 700 FIELD_PREP(MT_TXD6_BW, bw) | 701 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 702 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 703 704 /* for HE_SU/HE_EXT_SU PPDU 705 * - 1x, 2x, 4x LTF + 0.8us GI 706 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 707 * for HE_MU PPDU 708 * - 2x, 4x LTF + 0.8us GI 709 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 710 * for HE_TB PPDU 711 * - 1x, 2x LTF + 1.6us GI 712 * - 4x LTF + 3.2us GI 713 */ 714 if (mode >= MT_PHY_TYPE_HE_SU) 715 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 716 717 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 718 val |= MT_TXD6_LDPC; 719 720 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 721 txwi[6] |= cpu_to_le32(val); 722 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 723 phy->test.spe_idx)); 724 #endif 725 } 726 727 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 728 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 729 struct ieee80211_key_conf *key, 730 enum mt76_txq_id qid, u32 changed) 731 { 732 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 733 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 734 struct mt76_phy *mphy = &dev->phy; 735 736 if (phy_idx && dev->phys[MT_BAND1]) 737 mphy = dev->phys[MT_BAND1]; 738 739 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 740 741 if (mt76_testmode_enabled(mphy)) 742 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 743 } 744 745 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 746 enum mt76_txq_id qid, struct mt76_wcid *wcid, 747 struct ieee80211_sta *sta, 748 struct mt76_tx_info *tx_info) 749 { 750 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 751 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 752 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 753 struct ieee80211_key_conf *key = info->control.hw_key; 754 struct ieee80211_vif *vif = info->control.vif; 755 struct mt76_connac_fw_txp *txp; 756 struct mt76_txwi_cache *t; 757 int id, i, nbuf = tx_info->nbuf - 1; 758 u8 *txwi = (u8 *)txwi_ptr; 759 int pid; 760 761 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 762 return -EINVAL; 763 764 if (!wcid) 765 wcid = &dev->mt76.global_wcid; 766 767 if (sta) { 768 struct mt7915_sta *msta; 769 770 msta = (struct mt7915_sta *)sta->drv_priv; 771 772 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 773 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 774 msta->jiffies = jiffies; 775 } 776 } 777 778 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 779 t->skb = tx_info->skb; 780 781 id = mt76_token_consume(mdev, &t); 782 if (id < 0) 783 return id; 784 785 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 786 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 787 qid, 0); 788 789 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 790 for (i = 0; i < nbuf; i++) { 791 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 792 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 793 } 794 txp->nbuf = nbuf; 795 796 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 797 798 if (!key) 799 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 800 801 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 802 ieee80211_is_mgmt(hdr->frame_control)) 803 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 804 805 if (vif) { 806 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 807 808 txp->bss_idx = mvif->mt76.idx; 809 } 810 811 txp->token = cpu_to_le16(id); 812 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 813 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 814 else 815 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 816 tx_info->skb = DMA_DUMMY_DATA; 817 818 /* pass partial skb header to fw */ 819 tx_info->buf[1].len = MT_CT_PARSE_LEN; 820 tx_info->buf[1].skip_unmap = true; 821 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 822 823 return 0; 824 } 825 826 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 827 { 828 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 829 __le32 *txwi = ptr; 830 u32 val; 831 832 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 833 834 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 835 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 836 txwi[0] = cpu_to_le32(val); 837 838 val = MT_TXD1_LONG_FORMAT | 839 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 840 txwi[1] = cpu_to_le32(val); 841 842 txp->token = cpu_to_le16(token_id); 843 txp->nbuf = 1; 844 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 845 846 return MT_TXD_SIZE + sizeof(*txp); 847 } 848 849 static void 850 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 851 { 852 struct mt7915_sta *msta; 853 u16 fc, tid; 854 u32 val; 855 856 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 857 return; 858 859 tid = le32_get_bits(txwi[1], MT_TXD1_TID); 860 if (tid >= 6) /* skip VO queue */ 861 return; 862 863 val = le32_to_cpu(txwi[2]); 864 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 865 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 866 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 867 return; 868 869 msta = (struct mt7915_sta *)sta->drv_priv; 870 if (!test_and_set_bit(tid, &msta->ampdu_state)) 871 ieee80211_start_tx_ba_session(sta, tid, 0); 872 } 873 874 static void 875 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, 876 struct ieee80211_sta *sta, struct list_head *free_list) 877 { 878 struct mt76_dev *mdev = &dev->mt76; 879 struct mt7915_sta *msta; 880 struct mt76_wcid *wcid; 881 __le32 *txwi; 882 u16 wcid_idx; 883 884 mt76_connac_txp_skb_unmap(mdev, t); 885 if (!t->skb) 886 goto out; 887 888 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 889 if (sta) { 890 wcid = (struct mt76_wcid *)sta->drv_priv; 891 wcid_idx = wcid->idx; 892 } else { 893 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); 894 wcid = rcu_dereference(dev->mt76.wcid[wcid_idx]); 895 896 if (wcid && wcid->sta) { 897 msta = container_of(wcid, struct mt7915_sta, wcid); 898 sta = container_of((void *)msta, struct ieee80211_sta, 899 drv_priv); 900 spin_lock_bh(&dev->sta_poll_lock); 901 if (list_empty(&msta->poll_list)) 902 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 903 spin_unlock_bh(&dev->sta_poll_lock); 904 } 905 } 906 907 if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 908 mt7915_tx_check_aggr(sta, txwi); 909 910 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 911 912 out: 913 t->skb = NULL; 914 mt76_put_txwi(mdev, t); 915 } 916 917 static void 918 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 919 { 920 struct mt76_dev *mdev = &dev->mt76; 921 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 922 923 /* clean DMA queues and unmap buffers first */ 924 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 925 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 926 if (mphy_ext) { 927 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 928 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 929 } 930 } 931 932 static void 933 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 934 struct list_head *free_list, bool wake) 935 { 936 struct sk_buff *skb, *tmp; 937 938 mt7915_mac_sta_poll(dev); 939 940 if (wake) 941 mt76_set_tx_blocked(&dev->mt76, false); 942 943 mt76_worker_schedule(&dev->mt76.tx_worker); 944 945 list_for_each_entry_safe(skb, tmp, free_list, list) { 946 skb_list_del_init(skb); 947 napi_consume_skb(skb, 1); 948 } 949 } 950 951 static void 952 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 953 { 954 struct mt76_connac_tx_free *free = data; 955 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 956 struct mt76_dev *mdev = &dev->mt76; 957 struct mt76_txwi_cache *txwi; 958 struct ieee80211_sta *sta = NULL; 959 LIST_HEAD(free_list); 960 void *end = data + len; 961 bool v3, wake = false; 962 u16 total, count = 0; 963 u32 txd = le32_to_cpu(free->txd); 964 __le32 *cur_info; 965 966 mt7915_mac_tx_free_prepare(dev); 967 968 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 969 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 970 971 for (cur_info = tx_info; count < total; cur_info++) { 972 u32 msdu, info; 973 u8 i; 974 975 if (WARN_ON_ONCE((void *)cur_info >= end)) 976 return; 977 978 /* 979 * 1'b1: new wcid pair. 980 * 1'b0: msdu_id with the same 'wcid pair' as above. 981 */ 982 info = le32_to_cpu(*cur_info); 983 if (info & MT_TX_FREE_PAIR) { 984 struct mt7915_sta *msta; 985 struct mt76_wcid *wcid; 986 u16 idx; 987 988 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 989 wcid = rcu_dereference(dev->mt76.wcid[idx]); 990 sta = wcid_to_sta(wcid); 991 if (!sta) 992 continue; 993 994 msta = container_of(wcid, struct mt7915_sta, wcid); 995 spin_lock_bh(&dev->sta_poll_lock); 996 if (list_empty(&msta->poll_list)) 997 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 998 spin_unlock_bh(&dev->sta_poll_lock); 999 continue; 1000 } 1001 1002 if (v3 && (info & MT_TX_FREE_MPDU_HEADER)) 1003 continue; 1004 1005 for (i = 0; i < 1 + v3; i++) { 1006 if (v3) { 1007 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 1008 if (msdu == MT_TX_FREE_MSDU_ID_V3) 1009 continue; 1010 } else { 1011 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 1012 } 1013 count++; 1014 txwi = mt76_token_release(mdev, msdu, &wake); 1015 if (!txwi) 1016 continue; 1017 1018 mt7915_txwi_free(dev, txwi, sta, &free_list); 1019 } 1020 } 1021 1022 mt7915_mac_tx_free_done(dev, &free_list, wake); 1023 } 1024 1025 static void 1026 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 1027 { 1028 struct mt76_connac_tx_free *free = data; 1029 __le16 *info = (__le16 *)(data + sizeof(*free)); 1030 struct mt76_dev *mdev = &dev->mt76; 1031 void *end = data + len; 1032 LIST_HEAD(free_list); 1033 bool wake = false; 1034 u8 i, count; 1035 1036 mt7915_mac_tx_free_prepare(dev); 1037 1038 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 1039 if (WARN_ON_ONCE((void *)&info[count] > end)) 1040 return; 1041 1042 for (i = 0; i < count; i++) { 1043 struct mt76_txwi_cache *txwi; 1044 u16 msdu = le16_to_cpu(info[i]); 1045 1046 txwi = mt76_token_release(mdev, msdu, &wake); 1047 if (!txwi) 1048 continue; 1049 1050 mt7915_txwi_free(dev, txwi, NULL, &free_list); 1051 } 1052 1053 mt7915_mac_tx_free_done(dev, &free_list, wake); 1054 } 1055 1056 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1057 { 1058 struct mt7915_sta *msta = NULL; 1059 struct mt76_wcid *wcid; 1060 __le32 *txs_data = data; 1061 u16 wcidx; 1062 u8 pid; 1063 1064 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1) 1065 return; 1066 1067 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1068 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1069 1070 if (pid < MT_PACKET_ID_WED) 1071 return; 1072 1073 if (wcidx >= mt7915_wtbl_size(dev)) 1074 return; 1075 1076 rcu_read_lock(); 1077 1078 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1079 if (!wcid) 1080 goto out; 1081 1082 msta = container_of(wcid, struct mt7915_sta, wcid); 1083 1084 if (pid == MT_PACKET_ID_WED) 1085 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1086 else 1087 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1088 1089 if (!wcid->sta) 1090 goto out; 1091 1092 spin_lock_bh(&dev->sta_poll_lock); 1093 if (list_empty(&msta->poll_list)) 1094 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1095 spin_unlock_bh(&dev->sta_poll_lock); 1096 1097 out: 1098 rcu_read_unlock(); 1099 } 1100 1101 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1102 { 1103 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1104 __le32 *rxd = (__le32 *)data; 1105 __le32 *end = (__le32 *)&rxd[len / 4]; 1106 enum rx_pkt_type type; 1107 1108 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1109 1110 switch (type) { 1111 case PKT_TYPE_TXRX_NOTIFY: 1112 mt7915_mac_tx_free(dev, data, len); 1113 return false; 1114 case PKT_TYPE_TXRX_NOTIFY_V0: 1115 mt7915_mac_tx_free_v0(dev, data, len); 1116 return false; 1117 case PKT_TYPE_TXS: 1118 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1119 mt7915_mac_add_txs(dev, rxd); 1120 return false; 1121 case PKT_TYPE_RX_FW_MONITOR: 1122 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1123 return false; 1124 default: 1125 return true; 1126 } 1127 } 1128 1129 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1130 struct sk_buff *skb, u32 *info) 1131 { 1132 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1133 __le32 *rxd = (__le32 *)skb->data; 1134 __le32 *end = (__le32 *)&skb->data[skb->len]; 1135 enum rx_pkt_type type; 1136 1137 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1138 1139 switch (type) { 1140 case PKT_TYPE_TXRX_NOTIFY: 1141 mt7915_mac_tx_free(dev, skb->data, skb->len); 1142 napi_consume_skb(skb, 1); 1143 break; 1144 case PKT_TYPE_TXRX_NOTIFY_V0: 1145 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1146 napi_consume_skb(skb, 1); 1147 break; 1148 case PKT_TYPE_RX_EVENT: 1149 mt7915_mcu_rx_event(dev, skb); 1150 break; 1151 case PKT_TYPE_TXRXV: 1152 mt7915_mac_fill_rx_vector(dev, skb); 1153 break; 1154 case PKT_TYPE_TXS: 1155 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1156 mt7915_mac_add_txs(dev, rxd); 1157 dev_kfree_skb(skb); 1158 break; 1159 case PKT_TYPE_RX_FW_MONITOR: 1160 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1161 dev_kfree_skb(skb); 1162 break; 1163 case PKT_TYPE_NORMAL: 1164 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1165 mt76_rx(&dev->mt76, q, skb); 1166 return; 1167 } 1168 fallthrough; 1169 default: 1170 dev_kfree_skb(skb); 1171 break; 1172 } 1173 } 1174 1175 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1176 { 1177 struct mt7915_dev *dev = phy->dev; 1178 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1179 1180 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1181 mt76_set(dev, reg, BIT(11) | BIT(9)); 1182 } 1183 1184 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1185 { 1186 struct mt7915_dev *dev = phy->dev; 1187 int i; 1188 1189 for (i = 0; i < 4; i++) { 1190 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1191 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1192 } 1193 1194 phy->mt76->survey_time = ktime_get_boottime(); 1195 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1196 1197 /* reset airtime counters */ 1198 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1199 MT_WF_RMAC_MIB_RXTIME_CLR); 1200 1201 mt7915_mcu_get_chan_mib_info(phy, true); 1202 } 1203 1204 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1205 { 1206 s16 coverage_class = phy->coverage_class; 1207 struct mt7915_dev *dev = phy->dev; 1208 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1209 u32 val, reg_offset; 1210 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1211 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1212 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1213 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1214 u8 band = phy->mt76->band_idx; 1215 int eifs_ofdm = 360, sifs = 10, offset; 1216 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1217 1218 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1219 return; 1220 1221 if (ext_phy) 1222 coverage_class = max_t(s16, dev->phy.coverage_class, 1223 ext_phy->coverage_class); 1224 1225 mt76_set(dev, MT_ARB_SCR(band), 1226 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1227 udelay(1); 1228 1229 offset = 3 * coverage_class; 1230 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1231 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1232 1233 if (!is_mt7915(&dev->mt76)) { 1234 if (!a_band) { 1235 mt76_wr(dev, MT_TMAC_ICR1(band), 1236 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1237 eifs_ofdm = 78; 1238 } else { 1239 eifs_ofdm = 84; 1240 } 1241 } else if (a_band) { 1242 sifs = 16; 1243 } 1244 1245 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1246 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1247 mt76_wr(dev, MT_TMAC_ICR0(band), 1248 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1249 FIELD_PREP(MT_IFS_RIFS, 2) | 1250 FIELD_PREP(MT_IFS_SIFS, sifs) | 1251 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1252 1253 if (phy->slottime < 20 || a_band) 1254 val = MT7915_CFEND_RATE_DEFAULT; 1255 else 1256 val = MT7915_CFEND_RATE_11B; 1257 1258 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1259 mt76_clear(dev, MT_ARB_SCR(band), 1260 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1261 } 1262 1263 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1264 { 1265 u32 reg; 1266 1267 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1268 MT_WF_PHY_RXTD12_MT7916(band); 1269 mt76_set(dev, reg, 1270 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1271 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1272 1273 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1274 MT_WF_PHY_RX_CTRL1_MT7916(band); 1275 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1276 } 1277 1278 static u8 1279 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1280 { 1281 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1282 struct mt7915_dev *dev = phy->dev; 1283 u32 val, sum = 0, n = 0; 1284 int nss, i; 1285 1286 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1287 u32 reg = is_mt7915(&dev->mt76) ? 1288 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1289 MT_WF_IRPI_NSS_MT7916(idx, nss); 1290 1291 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1292 val = mt76_rr(dev, reg); 1293 sum += val * nf_power[i]; 1294 n += val; 1295 } 1296 } 1297 1298 if (!n) 1299 return 0; 1300 1301 return sum / n; 1302 } 1303 1304 void mt7915_update_channel(struct mt76_phy *mphy) 1305 { 1306 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv; 1307 struct mt76_channel_state *state = mphy->chan_state; 1308 int nf; 1309 1310 mt7915_mcu_get_chan_mib_info(phy, false); 1311 1312 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1313 if (!phy->noise) 1314 phy->noise = nf << 4; 1315 else if (nf) 1316 phy->noise += nf - (phy->noise >> 4); 1317 1318 state->noise = -(phy->noise >> 4); 1319 } 1320 1321 static bool 1322 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1323 { 1324 bool ret; 1325 1326 ret = wait_event_timeout(dev->reset_wait, 1327 (READ_ONCE(dev->recovery.state) & state), 1328 MT7915_RESET_TIMEOUT); 1329 1330 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1331 return ret; 1332 } 1333 1334 static void 1335 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1336 { 1337 struct ieee80211_hw *hw = priv; 1338 1339 switch (vif->type) { 1340 case NL80211_IFTYPE_MESH_POINT: 1341 case NL80211_IFTYPE_ADHOC: 1342 case NL80211_IFTYPE_AP: 1343 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1344 BSS_CHANGED_BEACON_ENABLED); 1345 break; 1346 default: 1347 break; 1348 } 1349 } 1350 1351 static void 1352 mt7915_update_beacons(struct mt7915_dev *dev) 1353 { 1354 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1355 1356 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1357 IEEE80211_IFACE_ITER_RESUME_ALL, 1358 mt7915_update_vif_beacon, dev->mt76.hw); 1359 1360 if (!mphy_ext) 1361 return; 1362 1363 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1364 IEEE80211_IFACE_ITER_RESUME_ALL, 1365 mt7915_update_vif_beacon, mphy_ext->hw); 1366 } 1367 1368 void mt7915_tx_token_put(struct mt7915_dev *dev) 1369 { 1370 struct mt76_txwi_cache *txwi; 1371 int id; 1372 1373 spin_lock_bh(&dev->mt76.token_lock); 1374 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1375 mt7915_txwi_free(dev, txwi, NULL, NULL); 1376 dev->mt76.token_count--; 1377 } 1378 spin_unlock_bh(&dev->mt76.token_lock); 1379 idr_destroy(&dev->mt76.token); 1380 } 1381 1382 static int 1383 mt7915_mac_restart(struct mt7915_dev *dev) 1384 { 1385 struct mt7915_phy *phy2; 1386 struct mt76_phy *ext_phy; 1387 struct mt76_dev *mdev = &dev->mt76; 1388 int i, ret; 1389 1390 ext_phy = dev->mt76.phys[MT_BAND1]; 1391 phy2 = ext_phy ? ext_phy->priv : NULL; 1392 1393 if (dev->hif2) { 1394 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1395 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1396 } 1397 1398 if (dev_is_pci(mdev->dev)) { 1399 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1400 if (dev->hif2) 1401 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1402 } 1403 1404 set_bit(MT76_RESET, &dev->mphy.state); 1405 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1406 wake_up(&dev->mt76.mcu.wait); 1407 if (ext_phy) { 1408 set_bit(MT76_RESET, &ext_phy->state); 1409 set_bit(MT76_MCU_RESET, &ext_phy->state); 1410 } 1411 1412 /* lock/unlock all queues to ensure that no tx is pending */ 1413 mt76_txq_schedule_all(&dev->mphy); 1414 if (ext_phy) 1415 mt76_txq_schedule_all(ext_phy); 1416 1417 /* disable all tx/rx napi */ 1418 mt76_worker_disable(&dev->mt76.tx_worker); 1419 mt76_for_each_q_rx(mdev, i) { 1420 if (mdev->q_rx[i].ndesc) 1421 napi_disable(&dev->mt76.napi[i]); 1422 } 1423 napi_disable(&dev->mt76.tx_napi); 1424 1425 /* token reinit */ 1426 mt7915_tx_token_put(dev); 1427 idr_init(&dev->mt76.token); 1428 1429 mt7915_dma_reset(dev, true); 1430 1431 local_bh_disable(); 1432 mt76_for_each_q_rx(mdev, i) { 1433 if (mdev->q_rx[i].ndesc) { 1434 napi_enable(&dev->mt76.napi[i]); 1435 napi_schedule(&dev->mt76.napi[i]); 1436 } 1437 } 1438 local_bh_enable(); 1439 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1440 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1441 1442 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1443 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1444 1445 if (dev->hif2) { 1446 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1447 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1448 } 1449 if (dev_is_pci(mdev->dev)) { 1450 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1451 if (dev->hif2) 1452 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1453 } 1454 1455 /* load firmware */ 1456 ret = mt7915_mcu_init_firmware(dev); 1457 if (ret) 1458 goto out; 1459 1460 /* set the necessary init items */ 1461 ret = mt7915_mcu_set_eeprom(dev); 1462 if (ret) 1463 goto out; 1464 1465 mt7915_mac_init(dev); 1466 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 1467 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 1468 ret = mt7915_txbf_init(dev); 1469 1470 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1471 ret = mt7915_run(dev->mphy.hw); 1472 if (ret) 1473 goto out; 1474 } 1475 1476 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1477 ret = mt7915_run(ext_phy->hw); 1478 if (ret) 1479 goto out; 1480 } 1481 1482 out: 1483 /* reset done */ 1484 clear_bit(MT76_RESET, &dev->mphy.state); 1485 if (phy2) 1486 clear_bit(MT76_RESET, &phy2->mt76->state); 1487 1488 local_bh_disable(); 1489 napi_enable(&dev->mt76.tx_napi); 1490 napi_schedule(&dev->mt76.tx_napi); 1491 local_bh_enable(); 1492 1493 mt76_worker_enable(&dev->mt76.tx_worker); 1494 1495 return ret; 1496 } 1497 1498 static void 1499 mt7915_mac_full_reset(struct mt7915_dev *dev) 1500 { 1501 struct mt76_phy *ext_phy; 1502 int i; 1503 1504 ext_phy = dev->mt76.phys[MT_BAND1]; 1505 1506 dev->recovery.hw_full_reset = true; 1507 1508 wake_up(&dev->mt76.mcu.wait); 1509 ieee80211_stop_queues(mt76_hw(dev)); 1510 if (ext_phy) 1511 ieee80211_stop_queues(ext_phy->hw); 1512 1513 cancel_delayed_work_sync(&dev->mphy.mac_work); 1514 if (ext_phy) 1515 cancel_delayed_work_sync(&ext_phy->mac_work); 1516 1517 mutex_lock(&dev->mt76.mutex); 1518 for (i = 0; i < 10; i++) { 1519 if (!mt7915_mac_restart(dev)) 1520 break; 1521 } 1522 mutex_unlock(&dev->mt76.mutex); 1523 1524 if (i == 10) 1525 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1526 1527 ieee80211_restart_hw(mt76_hw(dev)); 1528 if (ext_phy) 1529 ieee80211_restart_hw(ext_phy->hw); 1530 1531 ieee80211_wake_queues(mt76_hw(dev)); 1532 if (ext_phy) 1533 ieee80211_wake_queues(ext_phy->hw); 1534 1535 dev->recovery.hw_full_reset = false; 1536 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1537 MT7915_WATCHDOG_TIME); 1538 if (ext_phy) 1539 ieee80211_queue_delayed_work(ext_phy->hw, 1540 &ext_phy->mac_work, 1541 MT7915_WATCHDOG_TIME); 1542 } 1543 1544 /* system error recovery */ 1545 void mt7915_mac_reset_work(struct work_struct *work) 1546 { 1547 struct mt7915_phy *phy2; 1548 struct mt76_phy *ext_phy; 1549 struct mt7915_dev *dev; 1550 int i; 1551 1552 dev = container_of(work, struct mt7915_dev, reset_work); 1553 ext_phy = dev->mt76.phys[MT_BAND1]; 1554 phy2 = ext_phy ? ext_phy->priv : NULL; 1555 1556 /* chip full reset */ 1557 if (dev->recovery.restart) { 1558 /* disable WA/WM WDT */ 1559 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1560 MT_MCU_CMD_WDT_MASK); 1561 1562 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1563 dev->recovery.wa_reset_count++; 1564 else 1565 dev->recovery.wm_reset_count++; 1566 1567 mt7915_mac_full_reset(dev); 1568 1569 /* enable mcu irq */ 1570 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1571 mt7915_irq_disable(dev, 0); 1572 1573 /* enable WA/WM WDT */ 1574 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1575 1576 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1577 dev->recovery.restart = false; 1578 return; 1579 } 1580 1581 /* chip partial reset */ 1582 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1583 return; 1584 1585 ieee80211_stop_queues(mt76_hw(dev)); 1586 if (ext_phy) 1587 ieee80211_stop_queues(ext_phy->hw); 1588 1589 set_bit(MT76_RESET, &dev->mphy.state); 1590 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1591 wake_up(&dev->mt76.mcu.wait); 1592 cancel_delayed_work_sync(&dev->mphy.mac_work); 1593 if (phy2) { 1594 set_bit(MT76_RESET, &phy2->mt76->state); 1595 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1596 } 1597 mt76_worker_disable(&dev->mt76.tx_worker); 1598 mt76_for_each_q_rx(&dev->mt76, i) 1599 napi_disable(&dev->mt76.napi[i]); 1600 napi_disable(&dev->mt76.tx_napi); 1601 1602 mutex_lock(&dev->mt76.mutex); 1603 1604 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1605 1606 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1607 mt7915_dma_reset(dev, false); 1608 1609 mt7915_tx_token_put(dev); 1610 idr_init(&dev->mt76.token); 1611 1612 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1613 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1614 } 1615 1616 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1617 clear_bit(MT76_RESET, &dev->mphy.state); 1618 if (phy2) 1619 clear_bit(MT76_RESET, &phy2->mt76->state); 1620 1621 local_bh_disable(); 1622 mt76_for_each_q_rx(&dev->mt76, i) { 1623 napi_enable(&dev->mt76.napi[i]); 1624 napi_schedule(&dev->mt76.napi[i]); 1625 } 1626 local_bh_enable(); 1627 1628 tasklet_schedule(&dev->irq_tasklet); 1629 1630 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1631 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1632 1633 mt76_worker_enable(&dev->mt76.tx_worker); 1634 1635 local_bh_disable(); 1636 napi_enable(&dev->mt76.tx_napi); 1637 napi_schedule(&dev->mt76.tx_napi); 1638 local_bh_enable(); 1639 1640 ieee80211_wake_queues(mt76_hw(dev)); 1641 if (ext_phy) 1642 ieee80211_wake_queues(ext_phy->hw); 1643 1644 mutex_unlock(&dev->mt76.mutex); 1645 1646 mt7915_update_beacons(dev); 1647 1648 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1649 MT7915_WATCHDOG_TIME); 1650 if (phy2) 1651 ieee80211_queue_delayed_work(ext_phy->hw, 1652 &phy2->mt76->mac_work, 1653 MT7915_WATCHDOG_TIME); 1654 } 1655 1656 /* firmware coredump */ 1657 void mt7915_mac_dump_work(struct work_struct *work) 1658 { 1659 const struct mt7915_mem_region *mem_region; 1660 struct mt7915_crash_data *crash_data; 1661 struct mt7915_dev *dev; 1662 struct mt7915_mem_hdr *hdr; 1663 size_t buf_len; 1664 int i; 1665 u32 num; 1666 u8 *buf; 1667 1668 dev = container_of(work, struct mt7915_dev, dump_work); 1669 1670 mutex_lock(&dev->dump_mutex); 1671 1672 crash_data = mt7915_coredump_new(dev); 1673 if (!crash_data) { 1674 mutex_unlock(&dev->dump_mutex); 1675 goto skip_coredump; 1676 } 1677 1678 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1679 if (!mem_region || !crash_data->memdump_buf_len) { 1680 mutex_unlock(&dev->dump_mutex); 1681 goto skip_memdump; 1682 } 1683 1684 buf = crash_data->memdump_buf; 1685 buf_len = crash_data->memdump_buf_len; 1686 1687 /* dumping memory content... */ 1688 memset(buf, 0, buf_len); 1689 for (i = 0; i < num; i++) { 1690 if (mem_region->len > buf_len) { 1691 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1692 mem_region->name, 1693 (unsigned long)mem_region->len); 1694 break; 1695 } 1696 1697 /* reserve space for the header */ 1698 hdr = (void *)buf; 1699 buf += sizeof(*hdr); 1700 buf_len -= sizeof(*hdr); 1701 1702 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1703 mem_region->len); 1704 1705 hdr->start = mem_region->start; 1706 hdr->len = mem_region->len; 1707 1708 if (!mem_region->len) 1709 /* note: the header remains, just with zero length */ 1710 break; 1711 1712 buf += mem_region->len; 1713 buf_len -= mem_region->len; 1714 1715 mem_region++; 1716 } 1717 1718 mutex_unlock(&dev->dump_mutex); 1719 1720 skip_memdump: 1721 mt7915_coredump_submit(dev); 1722 skip_coredump: 1723 queue_work(dev->mt76.wq, &dev->reset_work); 1724 } 1725 1726 void mt7915_reset(struct mt7915_dev *dev) 1727 { 1728 if (!dev->recovery.hw_init_done) 1729 return; 1730 1731 if (dev->recovery.hw_full_reset) 1732 return; 1733 1734 /* wm/wa exception: do full recovery */ 1735 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1736 dev->recovery.restart = true; 1737 dev_info(dev->mt76.dev, 1738 "%s indicated firmware crash, attempting recovery\n", 1739 wiphy_name(dev->mt76.hw->wiphy)); 1740 1741 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1742 queue_work(dev->mt76.wq, &dev->dump_work); 1743 return; 1744 } 1745 1746 queue_work(dev->mt76.wq, &dev->reset_work); 1747 wake_up(&dev->reset_wait); 1748 } 1749 1750 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1751 { 1752 struct mt7915_dev *dev = phy->dev; 1753 struct mib_stats *mib = &phy->mib; 1754 int i, aggr0 = 0, aggr1, cnt; 1755 u8 band = phy->mt76->band_idx; 1756 u32 val; 1757 1758 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1759 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1760 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1761 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1762 1763 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1764 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1765 1766 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1767 mib->rx_mpdu_cnt += cnt; 1768 1769 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1770 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1771 1772 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1773 mib->rx_vector_mismatch_cnt += 1774 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1775 1776 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1777 mib->rx_delimiter_fail_cnt += 1778 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1779 1780 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1781 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1782 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1783 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1784 1785 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1786 mib->rx_len_mismatch_cnt += 1787 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1788 1789 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1790 mib->tx_ampdu_cnt += cnt; 1791 1792 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1793 mib->tx_stop_q_empty_cnt += 1794 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1795 1796 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1797 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1798 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1799 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1800 1801 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1802 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1803 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1804 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1805 1806 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1807 mib->primary_cca_busy_time += 1808 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1809 1810 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1811 mib->secondary_cca_busy_time += 1812 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1813 1814 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1815 mib->primary_energy_detect_time += 1816 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1817 1818 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1819 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1820 1821 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1822 mib->ofdm_mdrdy_time += 1823 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1824 1825 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1826 mib->green_mdrdy_time += 1827 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1828 1829 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1830 mib->rx_ampdu_cnt += cnt; 1831 1832 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1833 mib->rx_ampdu_bytes_cnt += cnt; 1834 1835 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1836 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1837 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1838 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1839 1840 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1841 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1842 1843 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1844 mib->tx_rwp_fail_cnt += 1845 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1846 1847 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1848 mib->tx_rwp_need_cnt += 1849 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1850 1851 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1852 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1853 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1854 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1855 1856 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1857 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1858 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1859 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1860 1861 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1862 mib->rx_ba_cnt += cnt; 1863 1864 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1865 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1866 1867 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1868 mib->tx_mu_mpdu_cnt += cnt; 1869 1870 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1871 mib->tx_mu_acked_mpdu_cnt += cnt; 1872 1873 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1874 mib->tx_su_acked_mpdu_cnt += cnt; 1875 1876 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1877 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1878 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1879 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1880 1881 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1882 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1883 mib->tx_amsdu[i] += cnt; 1884 mib->tx_amsdu_cnt += cnt; 1885 } 1886 1887 if (is_mt7915(&dev->mt76)) { 1888 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1889 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1890 mib->ba_miss_cnt += 1891 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1892 mib->ack_fail_cnt += 1893 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1894 1895 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1896 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1897 mib->rts_retries_cnt += 1898 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1899 1900 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1901 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1902 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1903 1904 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1905 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1906 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1907 } 1908 1909 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1910 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1911 1912 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1913 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1914 1915 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1916 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1917 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1918 1919 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1920 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1921 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1922 1923 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1924 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1925 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1926 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1927 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1928 } else { 1929 for (i = 0; i < 2; i++) { 1930 /* rts count */ 1931 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1932 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1933 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1934 1935 /* rts retry count */ 1936 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1937 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1938 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1939 1940 /* ba miss count */ 1941 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1942 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1943 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1944 1945 /* ack fail count */ 1946 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1947 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1948 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1949 } 1950 1951 for (i = 0; i < 8; i++) { 1952 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1953 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1954 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1955 } 1956 1957 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1958 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1959 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1960 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1961 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1962 1963 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1964 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1965 1966 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1967 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1968 1969 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1970 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1971 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1972 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1973 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1974 1975 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1976 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1977 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1978 } 1979 } 1980 1981 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1982 { 1983 struct mt7915_dev *dev = phy->dev; 1984 u32 trb; 1985 1986 if (!phy->omac_mask) 1987 return; 1988 1989 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1990 * stopping Rx, so check status periodically to see if TRB hardware 1991 * requires minimal recovery. 1992 */ 1993 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1994 1995 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1996 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1997 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1998 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1999 trb == phy->trb_ts) 2000 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 2001 phy->mt76->band_idx); 2002 2003 phy->trb_ts = trb; 2004 } 2005 2006 void mt7915_mac_sta_rc_work(struct work_struct *work) 2007 { 2008 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 2009 struct ieee80211_sta *sta; 2010 struct ieee80211_vif *vif; 2011 struct mt7915_sta *msta; 2012 u32 changed; 2013 LIST_HEAD(list); 2014 2015 spin_lock_bh(&dev->sta_poll_lock); 2016 list_splice_init(&dev->sta_rc_list, &list); 2017 2018 while (!list_empty(&list)) { 2019 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2020 list_del_init(&msta->rc_list); 2021 changed = msta->changed; 2022 msta->changed = 0; 2023 spin_unlock_bh(&dev->sta_poll_lock); 2024 2025 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2026 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2027 2028 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2029 IEEE80211_RC_NSS_CHANGED | 2030 IEEE80211_RC_BW_CHANGED)) 2031 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2032 2033 if (changed & IEEE80211_RC_SMPS_CHANGED) 2034 mt7915_mcu_add_smps(dev, vif, sta); 2035 2036 spin_lock_bh(&dev->sta_poll_lock); 2037 } 2038 2039 spin_unlock_bh(&dev->sta_poll_lock); 2040 } 2041 2042 void mt7915_mac_work(struct work_struct *work) 2043 { 2044 struct mt7915_phy *phy; 2045 struct mt76_phy *mphy; 2046 2047 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2048 mac_work.work); 2049 phy = mphy->priv; 2050 2051 mutex_lock(&mphy->dev->mutex); 2052 2053 mt76_update_survey(mphy); 2054 if (++mphy->mac_work_count == 5) { 2055 mphy->mac_work_count = 0; 2056 2057 mt7915_mac_update_stats(phy); 2058 mt7915_mac_severe_check(phy); 2059 } 2060 2061 mutex_unlock(&mphy->dev->mutex); 2062 2063 mt76_tx_status_check(mphy->dev, false); 2064 2065 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2066 MT7915_WATCHDOG_TIME); 2067 } 2068 2069 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2070 { 2071 struct mt7915_dev *dev = phy->dev; 2072 2073 if (phy->rdd_state & BIT(0)) 2074 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2075 MT_RX_SEL0, 0); 2076 if (phy->rdd_state & BIT(1)) 2077 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2078 MT_RX_SEL0, 0); 2079 } 2080 2081 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2082 { 2083 int err, region; 2084 2085 switch (dev->mt76.region) { 2086 case NL80211_DFS_ETSI: 2087 region = 0; 2088 break; 2089 case NL80211_DFS_JP: 2090 region = 2; 2091 break; 2092 case NL80211_DFS_FCC: 2093 default: 2094 region = 1; 2095 break; 2096 } 2097 2098 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2099 MT_RX_SEL0, region); 2100 if (err < 0) 2101 return err; 2102 2103 if (is_mt7915(&dev->mt76)) { 2104 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, chain, 2105 0, dev->dbdc_support ? 2 : 0); 2106 if (err < 0) 2107 return err; 2108 } 2109 2110 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2111 MT_RX_SEL0, 1); 2112 } 2113 2114 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2115 { 2116 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2117 struct mt7915_dev *dev = phy->dev; 2118 int err; 2119 2120 /* start CAC */ 2121 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, 2122 phy->mt76->band_idx, MT_RX_SEL0, 0); 2123 if (err < 0) 2124 return err; 2125 2126 err = mt7915_dfs_start_rdd(dev, phy->mt76->band_idx); 2127 if (err < 0) 2128 return err; 2129 2130 phy->rdd_state |= BIT(phy->mt76->band_idx); 2131 2132 if (!is_mt7915(&dev->mt76)) 2133 return 0; 2134 2135 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2136 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2137 err = mt7915_dfs_start_rdd(dev, 1); 2138 if (err < 0) 2139 return err; 2140 2141 phy->rdd_state |= BIT(1); 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int 2148 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2149 { 2150 const struct mt7915_dfs_radar_spec *radar_specs; 2151 struct mt7915_dev *dev = phy->dev; 2152 int err, i; 2153 2154 switch (dev->mt76.region) { 2155 case NL80211_DFS_FCC: 2156 radar_specs = &fcc_radar_specs; 2157 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2158 if (err < 0) 2159 return err; 2160 break; 2161 case NL80211_DFS_ETSI: 2162 radar_specs = &etsi_radar_specs; 2163 break; 2164 case NL80211_DFS_JP: 2165 radar_specs = &jp_radar_specs; 2166 break; 2167 default: 2168 return -EINVAL; 2169 } 2170 2171 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2172 err = mt7915_mcu_set_radar_th(dev, i, 2173 &radar_specs->radar_pattern[i]); 2174 if (err < 0) 2175 return err; 2176 } 2177 2178 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2179 } 2180 2181 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2182 { 2183 struct mt7915_dev *dev = phy->dev; 2184 enum mt76_dfs_state dfs_state, prev_state; 2185 int err; 2186 2187 prev_state = phy->mt76->dfs_state; 2188 dfs_state = mt76_phy_dfs_state(phy->mt76); 2189 2190 if (prev_state == dfs_state) 2191 return 0; 2192 2193 if (prev_state == MT_DFS_STATE_UNKNOWN) 2194 mt7915_dfs_stop_radar_detector(phy); 2195 2196 if (dfs_state == MT_DFS_STATE_DISABLED) 2197 goto stop; 2198 2199 if (prev_state <= MT_DFS_STATE_DISABLED) { 2200 err = mt7915_dfs_init_radar_specs(phy); 2201 if (err < 0) 2202 return err; 2203 2204 err = mt7915_dfs_start_radar_detector(phy); 2205 if (err < 0) 2206 return err; 2207 2208 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2209 } 2210 2211 if (dfs_state == MT_DFS_STATE_CAC) 2212 return 0; 2213 2214 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2215 phy->mt76->band_idx, MT_RX_SEL0, 0); 2216 if (err < 0) { 2217 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2218 return err; 2219 } 2220 2221 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2222 return 0; 2223 2224 stop: 2225 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, 2226 phy->mt76->band_idx, MT_RX_SEL0, 0); 2227 if (err < 0) 2228 return err; 2229 2230 if (is_mt7915(&dev->mt76)) { 2231 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2232 phy->mt76->band_idx, 0, 2233 dev->dbdc_support ? 2 : 0); 2234 if (err < 0) 2235 return err; 2236 } 2237 2238 mt7915_dfs_stop_radar_detector(phy); 2239 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2240 2241 return 0; 2242 } 2243 2244 static int 2245 mt7915_mac_twt_duration_align(int duration) 2246 { 2247 return duration << 8; 2248 } 2249 2250 static u64 2251 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2252 struct mt7915_twt_flow *flow) 2253 { 2254 struct mt7915_twt_flow *iter, *iter_next; 2255 u32 duration = flow->duration << 8; 2256 u64 start_tsf; 2257 2258 iter = list_first_entry_or_null(&dev->twt_list, 2259 struct mt7915_twt_flow, list); 2260 if (!iter || !iter->sched || iter->start_tsf > duration) { 2261 /* add flow as first entry in the list */ 2262 list_add(&flow->list, &dev->twt_list); 2263 return 0; 2264 } 2265 2266 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2267 start_tsf = iter->start_tsf + 2268 mt7915_mac_twt_duration_align(iter->duration); 2269 if (list_is_last(&iter->list, &dev->twt_list)) 2270 break; 2271 2272 if (!iter_next->sched || 2273 iter_next->start_tsf > start_tsf + duration) { 2274 list_add(&flow->list, &iter->list); 2275 goto out; 2276 } 2277 } 2278 2279 /* add flow as last entry in the list */ 2280 list_add_tail(&flow->list, &dev->twt_list); 2281 out: 2282 return start_tsf; 2283 } 2284 2285 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2286 { 2287 struct ieee80211_twt_params *twt_agrt; 2288 u64 interval, duration; 2289 u16 mantissa; 2290 u8 exp; 2291 2292 /* only individual agreement supported */ 2293 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2294 return -EOPNOTSUPP; 2295 2296 /* only 256us unit supported */ 2297 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2298 return -EOPNOTSUPP; 2299 2300 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2301 2302 /* explicit agreement not supported */ 2303 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2304 return -EOPNOTSUPP; 2305 2306 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2307 le16_to_cpu(twt_agrt->req_type)); 2308 mantissa = le16_to_cpu(twt_agrt->mantissa); 2309 duration = twt_agrt->min_twt_dur << 8; 2310 2311 interval = (u64)mantissa << exp; 2312 if (interval < duration) 2313 return -EOPNOTSUPP; 2314 2315 return 0; 2316 } 2317 2318 static bool 2319 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2320 struct ieee80211_twt_params *twt_agrt) 2321 { 2322 u16 type = le16_to_cpu(twt_agrt->req_type); 2323 u8 exp; 2324 int i; 2325 2326 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2327 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2328 struct mt7915_twt_flow *f; 2329 2330 if (!(msta->twt.flowid_mask & BIT(i))) 2331 continue; 2332 2333 f = &msta->twt.flow[i]; 2334 if (f->duration == twt_agrt->min_twt_dur && 2335 f->mantissa == twt_agrt->mantissa && 2336 f->exp == exp && 2337 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2338 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2339 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2340 return true; 2341 } 2342 2343 return false; 2344 } 2345 2346 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2347 struct ieee80211_sta *sta, 2348 struct ieee80211_twt_setup *twt) 2349 { 2350 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2351 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2352 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2353 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2354 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2355 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2356 struct mt7915_twt_flow *flow; 2357 int flowid, table_id; 2358 u8 exp; 2359 2360 if (mt7915_mac_check_twt_req(twt)) 2361 goto out; 2362 2363 mutex_lock(&dev->mt76.mutex); 2364 2365 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2366 goto unlock; 2367 2368 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2369 goto unlock; 2370 2371 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2372 setup_cmd = TWT_SETUP_CMD_DICTATE; 2373 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2374 goto unlock; 2375 } 2376 2377 flowid = ffs(~msta->twt.flowid_mask) - 1; 2378 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2379 twt_agrt->req_type |= le16_encode_bits(flowid, 2380 IEEE80211_TWT_REQTYPE_FLOWID); 2381 2382 table_id = ffs(~dev->twt.table_mask) - 1; 2383 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2384 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2385 2386 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2387 goto unlock; 2388 2389 flow = &msta->twt.flow[flowid]; 2390 memset(flow, 0, sizeof(*flow)); 2391 INIT_LIST_HEAD(&flow->list); 2392 flow->wcid = msta->wcid.idx; 2393 flow->table_id = table_id; 2394 flow->id = flowid; 2395 flow->duration = twt_agrt->min_twt_dur; 2396 flow->mantissa = twt_agrt->mantissa; 2397 flow->exp = exp; 2398 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2399 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2400 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2401 2402 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2403 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2404 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2405 u64 flow_tsf, curr_tsf; 2406 u32 rem; 2407 2408 flow->sched = true; 2409 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2410 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2411 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2412 flow_tsf = curr_tsf + interval - rem; 2413 twt_agrt->twt = cpu_to_le64(flow_tsf); 2414 } else { 2415 list_add_tail(&flow->list, &dev->twt_list); 2416 } 2417 flow->tsf = le64_to_cpu(twt_agrt->twt); 2418 2419 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2420 goto unlock; 2421 2422 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2423 dev->twt.table_mask |= BIT(table_id); 2424 msta->twt.flowid_mask |= BIT(flowid); 2425 dev->twt.n_agrt++; 2426 2427 unlock: 2428 mutex_unlock(&dev->mt76.mutex); 2429 out: 2430 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2431 twt_agrt->req_type |= 2432 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2433 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2434 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2435 } 2436 2437 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2438 struct mt7915_sta *msta, 2439 u8 flowid) 2440 { 2441 struct mt7915_twt_flow *flow; 2442 2443 lockdep_assert_held(&dev->mt76.mutex); 2444 2445 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2446 return; 2447 2448 if (!(msta->twt.flowid_mask & BIT(flowid))) 2449 return; 2450 2451 flow = &msta->twt.flow[flowid]; 2452 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2453 MCU_TWT_AGRT_DELETE)) 2454 return; 2455 2456 list_del_init(&flow->list); 2457 msta->twt.flowid_mask &= ~BIT(flowid); 2458 dev->twt.table_mask &= ~BIT(flow->table_id); 2459 dev->twt.n_agrt--; 2460 } 2461