1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "mt7915.h" 7 #include "../dma.h" 8 #include "mac.h" 9 #include "mcu.h" 10 11 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 12 13 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 14 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 15 IEEE80211_RADIOTAP_HE_##f) 16 17 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 18 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 19 .radar_pattern = { 20 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 21 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 22 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 23 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 24 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 25 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 26 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 27 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 28 }, 29 }; 30 31 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 32 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 33 .radar_pattern = { 34 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 35 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 36 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 37 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 38 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 39 }, 40 }; 41 42 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 43 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 44 .radar_pattern = { 45 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 46 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 47 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 48 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 49 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 50 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 51 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 52 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 53 }, 54 }; 55 56 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 57 u16 idx, bool unicast) 58 { 59 struct mt7915_sta *sta; 60 struct mt76_wcid *wcid; 61 62 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 63 return NULL; 64 65 wcid = rcu_dereference(dev->mt76.wcid[idx]); 66 if (unicast || !wcid) 67 return wcid; 68 69 if (!wcid->sta) 70 return NULL; 71 72 sta = container_of(wcid, struct mt7915_sta, wcid); 73 if (!sta->vif) 74 return NULL; 75 76 return &sta->vif->sta.wcid; 77 } 78 79 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 80 { 81 } 82 83 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 84 { 85 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 86 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 87 88 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 89 0, 5000); 90 } 91 92 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 93 { 94 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 95 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 96 97 return MT_WTBL_LMAC_OFFS(wcid, dw); 98 } 99 100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 101 { 102 static const u8 ac_to_tid[] = { 103 [IEEE80211_AC_BE] = 0, 104 [IEEE80211_AC_BK] = 1, 105 [IEEE80211_AC_VI] = 4, 106 [IEEE80211_AC_VO] = 6 107 }; 108 struct ieee80211_sta *sta; 109 struct mt7915_sta *msta; 110 struct rate_info *rate; 111 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 112 LIST_HEAD(sta_poll_list); 113 int i; 114 115 spin_lock_bh(&dev->sta_poll_lock); 116 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 117 spin_unlock_bh(&dev->sta_poll_lock); 118 119 rcu_read_lock(); 120 121 while (true) { 122 bool clear = false; 123 u32 addr, val; 124 u16 idx; 125 u8 bw; 126 127 spin_lock_bh(&dev->sta_poll_lock); 128 if (list_empty(&sta_poll_list)) { 129 spin_unlock_bh(&dev->sta_poll_lock); 130 break; 131 } 132 msta = list_first_entry(&sta_poll_list, 133 struct mt7915_sta, poll_list); 134 list_del_init(&msta->poll_list); 135 spin_unlock_bh(&dev->sta_poll_lock); 136 137 idx = msta->wcid.idx; 138 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 139 140 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 141 u32 tx_last = msta->airtime_ac[i]; 142 u32 rx_last = msta->airtime_ac[i + 4]; 143 144 msta->airtime_ac[i] = mt76_rr(dev, addr); 145 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 146 147 tx_time[i] = msta->airtime_ac[i] - tx_last; 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 q = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[q]; 170 u32 rx_cur = rx_time[q]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 } 217 218 rcu_read_unlock(); 219 } 220 221 static void 222 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 223 struct ieee80211_radiotap_he *he, 224 __le32 *rxv) 225 { 226 u32 ru_h, ru_l; 227 u8 ru, offs = 0; 228 229 ru_l = le32_get_bits(rxv[0], MT_PRXV_HE_RU_ALLOC_L); 230 ru_h = le32_get_bits(rxv[1], MT_PRXV_HE_RU_ALLOC_H); 231 ru = (u8)(ru_l | ru_h << 4); 232 233 status->bw = RATE_INFO_BW_HE_RU; 234 235 switch (ru) { 236 case 0 ... 36: 237 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 238 offs = ru; 239 break; 240 case 37 ... 52: 241 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 242 offs = ru - 37; 243 break; 244 case 53 ... 60: 245 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 246 offs = ru - 53; 247 break; 248 case 61 ... 64: 249 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 250 offs = ru - 61; 251 break; 252 case 65 ... 66: 253 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 254 offs = ru - 65; 255 break; 256 case 67: 257 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 258 break; 259 case 68: 260 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 261 break; 262 } 263 264 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 265 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 266 le16_encode_bits(offs, 267 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 268 } 269 270 static void 271 mt7915_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv) 272 { 273 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 274 static const struct ieee80211_radiotap_he_mu mu_known = { 275 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 276 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 277 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 278 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN), 279 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN), 280 }; 281 struct ieee80211_radiotap_he_mu *he_mu = NULL; 282 283 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 284 285 he_mu = skb_push(skb, sizeof(mu_known)); 286 memcpy(he_mu, &mu_known, sizeof(mu_known)); 287 288 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 289 290 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 291 if (status->he_dcm) 292 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 293 294 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 295 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 296 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 297 298 he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0); 299 300 if (status->bw >= RATE_INFO_BW_40) { 301 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 302 he_mu->ru_ch2[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU1); 303 } 304 305 if (status->bw >= RATE_INFO_BW_80) { 306 he_mu->ru_ch1[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU2); 307 he_mu->ru_ch2[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU3); 308 } 309 } 310 311 static void 312 mt7915_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u32 mode) 313 { 314 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 315 static const struct ieee80211_radiotap_he known = { 316 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 317 HE_BITS(DATA1_DATA_DCM_KNOWN) | 318 HE_BITS(DATA1_STBC_KNOWN) | 319 HE_BITS(DATA1_CODING_KNOWN) | 320 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 321 HE_BITS(DATA1_DOPPLER_KNOWN) | 322 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 323 HE_BITS(DATA1_BSS_COLOR_KNOWN), 324 .data2 = HE_BITS(DATA2_GI_KNOWN) | 325 HE_BITS(DATA2_TXBF_KNOWN) | 326 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 327 HE_BITS(DATA2_TXOP_KNOWN), 328 }; 329 struct ieee80211_radiotap_he *he = NULL; 330 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 331 332 status->flag |= RX_FLAG_RADIOTAP_HE; 333 334 he = skb_push(skb, sizeof(known)); 335 memcpy(he, &known, sizeof(known)); 336 337 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 338 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 339 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 340 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 341 le16_encode_bits(ltf_size, 342 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 343 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 344 he->data5 |= HE_BITS(DATA5_TXBF); 345 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 346 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 347 348 switch (mode) { 349 case MT_PHY_TYPE_HE_SU: 350 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 351 HE_BITS(DATA1_UL_DL_KNOWN) | 352 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) | 353 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 354 355 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 356 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 357 break; 358 case MT_PHY_TYPE_HE_EXT_SU: 359 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 360 HE_BITS(DATA1_UL_DL_KNOWN) | 361 HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 362 363 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 364 break; 365 case MT_PHY_TYPE_HE_MU: 366 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 367 HE_BITS(DATA1_UL_DL_KNOWN); 368 369 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 370 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 371 372 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 373 mt7915_mac_decode_he_mu_radiotap(skb, rxv); 374 break; 375 case MT_PHY_TYPE_HE_TB: 376 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 377 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 378 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 379 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 380 381 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 382 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 383 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 384 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 385 386 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 387 break; 388 default: 389 break; 390 } 391 } 392 393 /* The HW does not translate the mac header to 802.3 for mesh point */ 394 static int mt7915_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 395 { 396 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 397 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 398 struct mt7915_sta *msta = (struct mt7915_sta *)status->wcid; 399 __le32 *rxd = (__le32 *)skb->data; 400 struct ieee80211_sta *sta; 401 struct ieee80211_vif *vif; 402 struct ieee80211_hdr hdr; 403 u16 frame_control; 404 405 if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != 406 MT_RXD3_NORMAL_U2M) 407 return -EINVAL; 408 409 if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) 410 return -EINVAL; 411 412 if (!msta || !msta->vif) 413 return -EINVAL; 414 415 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 416 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 417 418 /* store the info from RXD and ethhdr to avoid being overridden */ 419 frame_control = le32_get_bits(rxd[6], MT_RXD6_FRAME_CONTROL); 420 hdr.frame_control = cpu_to_le16(frame_control); 421 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_SEQ_CTRL)); 422 hdr.duration_id = 0; 423 424 ether_addr_copy(hdr.addr1, vif->addr); 425 ether_addr_copy(hdr.addr2, sta->addr); 426 switch (frame_control & (IEEE80211_FCTL_TODS | 427 IEEE80211_FCTL_FROMDS)) { 428 case 0: 429 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 430 break; 431 case IEEE80211_FCTL_FROMDS: 432 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 433 break; 434 case IEEE80211_FCTL_TODS: 435 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 436 break; 437 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 438 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 439 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 440 break; 441 default: 442 break; 443 } 444 445 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 446 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 447 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 448 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 449 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 450 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 451 else 452 skb_pull(skb, 2); 453 454 if (ieee80211_has_order(hdr.frame_control)) 455 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[9], 456 IEEE80211_HT_CTL_LEN); 457 if (ieee80211_is_data_qos(hdr.frame_control)) { 458 __le16 qos_ctrl; 459 460 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_QOS_CTL)); 461 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 462 IEEE80211_QOS_CTL_LEN); 463 } 464 465 if (ieee80211_has_a4(hdr.frame_control)) 466 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 467 else 468 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 469 470 return 0; 471 } 472 473 static int 474 mt7915_mac_fill_rx_rate(struct mt7915_dev *dev, 475 struct mt76_rx_status *status, 476 struct ieee80211_supported_band *sband, 477 __le32 *rxv) 478 { 479 u32 v0, v2; 480 u8 stbc, gi, bw, dcm, mode, nss; 481 int i, idx; 482 bool cck = false; 483 484 v0 = le32_to_cpu(rxv[0]); 485 v2 = le32_to_cpu(rxv[2]); 486 487 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 488 nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; 489 490 if (!is_mt7915(&dev->mt76)) { 491 stbc = FIELD_GET(MT_PRXV_HT_STBC, v0); 492 gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v0); 493 mode = FIELD_GET(MT_PRXV_TX_MODE, v0); 494 dcm = FIELD_GET(MT_PRXV_DCM, v0); 495 bw = FIELD_GET(MT_PRXV_FRAME_MODE, v0); 496 } else { 497 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2); 498 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2); 499 mode = FIELD_GET(MT_CRXV_TX_MODE, v2); 500 dcm = !!(idx & GENMASK(3, 0) & MT_PRXV_TX_DCM); 501 bw = FIELD_GET(MT_CRXV_FRAME_MODE, v2); 502 } 503 504 switch (mode) { 505 case MT_PHY_TYPE_CCK: 506 cck = true; 507 fallthrough; 508 case MT_PHY_TYPE_OFDM: 509 i = mt76_get_rate(&dev->mt76, sband, i, cck); 510 break; 511 case MT_PHY_TYPE_HT_GF: 512 case MT_PHY_TYPE_HT: 513 status->encoding = RX_ENC_HT; 514 if (gi) 515 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 516 if (i > 31) 517 return -EINVAL; 518 break; 519 case MT_PHY_TYPE_VHT: 520 status->nss = nss; 521 status->encoding = RX_ENC_VHT; 522 if (gi) 523 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 524 if (i > 9) 525 return -EINVAL; 526 break; 527 case MT_PHY_TYPE_HE_MU: 528 case MT_PHY_TYPE_HE_SU: 529 case MT_PHY_TYPE_HE_EXT_SU: 530 case MT_PHY_TYPE_HE_TB: 531 status->nss = nss; 532 status->encoding = RX_ENC_HE; 533 i &= GENMASK(3, 0); 534 535 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 536 status->he_gi = gi; 537 538 status->he_dcm = dcm; 539 break; 540 default: 541 return -EINVAL; 542 } 543 status->rate_idx = i; 544 545 switch (bw) { 546 case IEEE80211_STA_RX_BW_20: 547 break; 548 case IEEE80211_STA_RX_BW_40: 549 if (mode & MT_PHY_TYPE_HE_EXT_SU && 550 (idx & MT_PRXV_TX_ER_SU_106T)) { 551 status->bw = RATE_INFO_BW_HE_RU; 552 status->he_ru = 553 NL80211_RATE_INFO_HE_RU_ALLOC_106; 554 } else { 555 status->bw = RATE_INFO_BW_40; 556 } 557 break; 558 case IEEE80211_STA_RX_BW_80: 559 status->bw = RATE_INFO_BW_80; 560 break; 561 case IEEE80211_STA_RX_BW_160: 562 status->bw = RATE_INFO_BW_160; 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 569 if (mode < MT_PHY_TYPE_HE_SU && gi) 570 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 571 572 return 0; 573 } 574 575 static int 576 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) 577 { 578 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 579 struct mt76_phy *mphy = &dev->mt76.phy; 580 struct mt7915_phy *phy = &dev->phy; 581 struct ieee80211_supported_band *sband; 582 __le32 *rxd = (__le32 *)skb->data; 583 __le32 *rxv = NULL; 584 u32 mode = 0; 585 u32 rxd0 = le32_to_cpu(rxd[0]); 586 u32 rxd1 = le32_to_cpu(rxd[1]); 587 u32 rxd2 = le32_to_cpu(rxd[2]); 588 u32 rxd3 = le32_to_cpu(rxd[3]); 589 u32 rxd4 = le32_to_cpu(rxd[4]); 590 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 591 bool unicast, insert_ccmp_hdr = false; 592 u8 remove_pad, amsdu_info; 593 bool hdr_trans; 594 u16 hdr_gap; 595 u16 seq_ctrl = 0; 596 u8 qos_ctl = 0; 597 __le16 fc = 0; 598 int idx; 599 600 memset(status, 0, sizeof(*status)); 601 602 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->band_idx) { 603 mphy = dev->mt76.phy2; 604 if (!mphy) 605 return -EINVAL; 606 607 phy = mphy->priv; 608 status->ext_phy = true; 609 } 610 611 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 612 return -EINVAL; 613 614 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 615 return -EINVAL; 616 617 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 618 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 619 return -EINVAL; 620 621 /* ICV error or CCMP/BIP/WPI MIC error */ 622 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 623 status->flag |= RX_FLAG_ONLY_MONITOR; 624 625 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 626 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 627 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 628 629 if (status->wcid) { 630 struct mt7915_sta *msta; 631 632 msta = container_of(status->wcid, struct mt7915_sta, wcid); 633 spin_lock_bh(&dev->sta_poll_lock); 634 if (list_empty(&msta->poll_list)) 635 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 636 spin_unlock_bh(&dev->sta_poll_lock); 637 } 638 639 status->freq = mphy->chandef.chan->center_freq; 640 status->band = mphy->chandef.chan->band; 641 if (status->band == NL80211_BAND_5GHZ) 642 sband = &mphy->sband_5g.sband; 643 else if (status->band == NL80211_BAND_6GHZ) 644 sband = &mphy->sband_6g.sband; 645 else 646 sband = &mphy->sband_2g.sband; 647 648 if (!sband->channels) 649 return -EINVAL; 650 651 if ((rxd0 & csum_mask) == csum_mask) 652 skb->ip_summed = CHECKSUM_UNNECESSARY; 653 654 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 655 status->flag |= RX_FLAG_FAILED_FCS_CRC; 656 657 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 658 status->flag |= RX_FLAG_MMIC_ERROR; 659 660 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 661 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 662 status->flag |= RX_FLAG_DECRYPTED; 663 status->flag |= RX_FLAG_IV_STRIPPED; 664 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 665 } 666 667 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 668 669 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 670 return -EINVAL; 671 672 rxd += 6; 673 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 674 u32 v0 = le32_to_cpu(rxd[0]); 675 u32 v2 = le32_to_cpu(rxd[2]); 676 677 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 678 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 679 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 680 681 rxd += 4; 682 if ((u8 *)rxd - skb->data >= skb->len) 683 return -EINVAL; 684 } 685 686 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 687 u8 *data = (u8 *)rxd; 688 689 if (status->flag & RX_FLAG_DECRYPTED) { 690 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 691 case MT_CIPHER_AES_CCMP: 692 case MT_CIPHER_CCMP_CCX: 693 case MT_CIPHER_CCMP_256: 694 insert_ccmp_hdr = 695 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 696 fallthrough; 697 case MT_CIPHER_TKIP: 698 case MT_CIPHER_TKIP_NO_MIC: 699 case MT_CIPHER_GCMP: 700 case MT_CIPHER_GCMP_256: 701 status->iv[0] = data[5]; 702 status->iv[1] = data[4]; 703 status->iv[2] = data[3]; 704 status->iv[3] = data[2]; 705 status->iv[4] = data[1]; 706 status->iv[5] = data[0]; 707 break; 708 default: 709 break; 710 } 711 } 712 rxd += 4; 713 if ((u8 *)rxd - skb->data >= skb->len) 714 return -EINVAL; 715 } 716 717 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 718 status->timestamp = le32_to_cpu(rxd[0]); 719 status->flag |= RX_FLAG_MACTIME_START; 720 721 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 722 status->flag |= RX_FLAG_AMPDU_DETAILS; 723 724 /* all subframes of an A-MPDU have the same timestamp */ 725 if (phy->rx_ampdu_ts != status->timestamp) { 726 if (!++phy->ampdu_ref) 727 phy->ampdu_ref++; 728 } 729 phy->rx_ampdu_ts = status->timestamp; 730 731 status->ampdu_ref = phy->ampdu_ref; 732 } 733 734 rxd += 2; 735 if ((u8 *)rxd - skb->data >= skb->len) 736 return -EINVAL; 737 } 738 739 /* RXD Group 3 - P-RXV */ 740 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 741 u32 v0, v1; 742 int ret; 743 744 rxv = rxd; 745 rxd += 2; 746 if ((u8 *)rxd - skb->data >= skb->len) 747 return -EINVAL; 748 749 v0 = le32_to_cpu(rxv[0]); 750 v1 = le32_to_cpu(rxv[1]); 751 752 if (v0 & MT_PRXV_HT_AD_CODE) 753 status->enc_flags |= RX_ENC_FLAG_LDPC; 754 755 status->chains = mphy->antenna_mask; 756 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 757 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 758 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 759 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 760 761 /* RXD Group 5 - C-RXV */ 762 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 763 rxd += 18; 764 if ((u8 *)rxd - skb->data >= skb->len) 765 return -EINVAL; 766 } 767 768 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 769 ret = mt7915_mac_fill_rx_rate(dev, status, sband, rxv); 770 if (ret < 0) 771 return ret; 772 } 773 } 774 775 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 776 status->amsdu = !!amsdu_info; 777 if (status->amsdu) { 778 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 779 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 780 } 781 782 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 783 if (hdr_trans && ieee80211_has_morefrags(fc)) { 784 if (mt7915_reverse_frag0_hdr_trans(skb, hdr_gap)) 785 return -EINVAL; 786 hdr_trans = false; 787 } else { 788 int pad_start = 0; 789 790 skb_pull(skb, hdr_gap); 791 if (!hdr_trans && status->amsdu) { 792 pad_start = ieee80211_get_hdrlen_from_skb(skb); 793 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 794 /* 795 * When header translation failure is indicated, 796 * the hardware will insert an extra 2-byte field 797 * containing the data length after the protocol 798 * type field. 799 */ 800 pad_start = 12; 801 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 802 pad_start += 4; 803 804 if (get_unaligned_be16(skb->data + pad_start) != 805 skb->len - pad_start - 2) 806 pad_start = 0; 807 } 808 809 if (pad_start) { 810 memmove(skb->data + 2, skb->data, pad_start); 811 skb_pull(skb, 2); 812 } 813 } 814 815 if (!hdr_trans) { 816 struct ieee80211_hdr *hdr; 817 818 if (insert_ccmp_hdr) { 819 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 820 821 mt76_insert_ccmp_hdr(skb, key_id); 822 } 823 824 hdr = mt76_skb_get_hdr(skb); 825 fc = hdr->frame_control; 826 if (ieee80211_is_data_qos(fc)) { 827 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 828 qos_ctl = *ieee80211_get_qos_ctl(hdr); 829 } 830 } else { 831 status->flag |= RX_FLAG_8023; 832 } 833 834 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 835 mt7915_mac_decode_he_radiotap(skb, rxv, mode); 836 837 if (!status->wcid || !ieee80211_is_data_qos(fc)) 838 return 0; 839 840 /* drop no data frame */ 841 if (fc & cpu_to_le16(IEEE80211_STYPE_NULLFUNC)) 842 return -EINVAL; 843 844 status->aggr = unicast && 845 !ieee80211_is_qos_nullfunc(fc); 846 status->qos_ctl = qos_ctl; 847 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 848 849 return 0; 850 } 851 852 static void 853 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 854 { 855 #ifdef CONFIG_NL80211_TESTMODE 856 struct mt7915_phy *phy = &dev->phy; 857 __le32 *rxd = (__le32 *)skb->data; 858 __le32 *rxv_hdr = rxd + 2; 859 __le32 *rxv = rxd + 4; 860 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 861 u8 band_idx; 862 s32 foe; 863 u8 snr; 864 int i; 865 866 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 867 if (band_idx && !phy->band_idx) 868 phy = mt7915_ext_phy(dev); 869 870 rcpi = le32_to_cpu(rxv[6]); 871 ib_rssi = le32_to_cpu(rxv[7]); 872 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 873 874 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 875 if (i == 3) 876 wb_rssi = le32_to_cpu(rxv[9]); 877 878 phy->test.last_rcpi[i] = rcpi & 0xff; 879 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 880 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 881 } 882 883 v20 = le32_to_cpu(rxv[20]); 884 v21 = le32_to_cpu(rxv[21]); 885 886 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 887 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 888 889 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 890 891 phy->test.last_freq_offset = foe; 892 phy->test.last_snr = snr; 893 #endif 894 895 dev_kfree_skb(skb); 896 } 897 898 static void 899 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 900 struct sk_buff *skb) 901 { 902 #ifdef CONFIG_NL80211_TESTMODE 903 struct mt76_testmode_data *td = &phy->mt76->test; 904 const struct ieee80211_rate *r; 905 u8 bw, mode, nss = td->tx_rate_nss; 906 u8 rate_idx = td->tx_rate_idx; 907 u16 rateval = 0; 908 u32 val; 909 bool cck = false; 910 int band; 911 912 if (skb != phy->mt76->test.tx_skb) 913 return; 914 915 switch (td->tx_rate_mode) { 916 case MT76_TM_TX_MODE_HT: 917 nss = 1 + (rate_idx >> 3); 918 mode = MT_PHY_TYPE_HT; 919 break; 920 case MT76_TM_TX_MODE_VHT: 921 mode = MT_PHY_TYPE_VHT; 922 break; 923 case MT76_TM_TX_MODE_HE_SU: 924 mode = MT_PHY_TYPE_HE_SU; 925 break; 926 case MT76_TM_TX_MODE_HE_EXT_SU: 927 mode = MT_PHY_TYPE_HE_EXT_SU; 928 break; 929 case MT76_TM_TX_MODE_HE_TB: 930 mode = MT_PHY_TYPE_HE_TB; 931 break; 932 case MT76_TM_TX_MODE_HE_MU: 933 mode = MT_PHY_TYPE_HE_MU; 934 break; 935 case MT76_TM_TX_MODE_CCK: 936 cck = true; 937 fallthrough; 938 case MT76_TM_TX_MODE_OFDM: 939 band = phy->mt76->chandef.chan->band; 940 if (band == NL80211_BAND_2GHZ && !cck) 941 rate_idx += 4; 942 943 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 944 val = cck ? r->hw_value_short : r->hw_value; 945 946 mode = val >> 8; 947 rate_idx = val & 0xff; 948 break; 949 default: 950 mode = MT_PHY_TYPE_OFDM; 951 break; 952 } 953 954 switch (phy->mt76->chandef.width) { 955 case NL80211_CHAN_WIDTH_40: 956 bw = 1; 957 break; 958 case NL80211_CHAN_WIDTH_80: 959 bw = 2; 960 break; 961 case NL80211_CHAN_WIDTH_80P80: 962 case NL80211_CHAN_WIDTH_160: 963 bw = 3; 964 break; 965 default: 966 bw = 0; 967 break; 968 } 969 970 if (td->tx_rate_stbc && nss == 1) { 971 nss++; 972 rateval |= MT_TX_RATE_STBC; 973 } 974 975 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 976 FIELD_PREP(MT_TX_RATE_MODE, mode) | 977 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 978 979 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 980 981 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 982 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 983 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 984 985 val = MT_TXD6_FIXED_BW | 986 FIELD_PREP(MT_TXD6_BW, bw) | 987 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 988 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 989 990 /* for HE_SU/HE_EXT_SU PPDU 991 * - 1x, 2x, 4x LTF + 0.8us GI 992 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 993 * for HE_MU PPDU 994 * - 2x, 4x LTF + 0.8us GI 995 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 996 * for HE_TB PPDU 997 * - 1x, 2x LTF + 1.6us GI 998 * - 4x LTF + 3.2us GI 999 */ 1000 if (mode >= MT_PHY_TYPE_HE_SU) 1001 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 1002 1003 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 1004 val |= MT_TXD6_LDPC; 1005 1006 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 1007 txwi[6] |= cpu_to_le32(val); 1008 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 1009 phy->test.spe_idx)); 1010 #endif 1011 } 1012 1013 static void 1014 mt7915_mac_write_txwi_8023(struct mt7915_dev *dev, __le32 *txwi, 1015 struct sk_buff *skb, struct mt76_wcid *wcid) 1016 { 1017 1018 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1019 u8 fc_type, fc_stype; 1020 bool wmm = false; 1021 u32 val; 1022 1023 if (wcid->sta) { 1024 struct ieee80211_sta *sta; 1025 1026 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 1027 wmm = sta->wme; 1028 } 1029 1030 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 1031 FIELD_PREP(MT_TXD1_TID, tid); 1032 1033 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 1034 val |= MT_TXD1_ETH_802_3; 1035 1036 txwi[1] |= cpu_to_le32(val); 1037 1038 fc_type = IEEE80211_FTYPE_DATA >> 2; 1039 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 1040 1041 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 1042 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 1043 1044 txwi[2] |= cpu_to_le32(val); 1045 1046 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 1047 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 1048 txwi[7] |= cpu_to_le32(val); 1049 } 1050 1051 static void 1052 mt7915_mac_write_txwi_80211(struct mt7915_dev *dev, __le32 *txwi, 1053 struct sk_buff *skb, struct ieee80211_key_conf *key, 1054 bool *mcast) 1055 { 1056 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1057 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1058 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1059 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1060 __le16 fc = hdr->frame_control; 1061 u8 fc_type, fc_stype; 1062 u32 val; 1063 1064 *mcast = is_multicast_ether_addr(hdr->addr1); 1065 1066 if (ieee80211_is_action(fc) && 1067 mgmt->u.action.category == WLAN_CATEGORY_BACK && 1068 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 1069 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 1070 1071 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 1072 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 1073 } else if (ieee80211_is_back_req(hdr->frame_control)) { 1074 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 1075 u16 control = le16_to_cpu(bar->control); 1076 1077 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 1078 } 1079 1080 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 1081 FIELD_PREP(MT_TXD1_HDR_INFO, 1082 ieee80211_get_hdrlen_from_skb(skb) / 2) | 1083 FIELD_PREP(MT_TXD1_TID, tid); 1084 txwi[1] |= cpu_to_le32(val); 1085 1086 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 1087 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 1088 1089 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 1090 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 1091 FIELD_PREP(MT_TXD2_MULTICAST, *mcast); 1092 1093 if (key && *mcast && ieee80211_is_robust_mgmt_frame(skb) && 1094 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 1095 val |= MT_TXD2_BIP; 1096 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 1097 } 1098 1099 if (!ieee80211_is_data(fc) || *mcast || 1100 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 1101 val |= MT_TXD2_FIX_RATE; 1102 1103 txwi[2] |= cpu_to_le32(val); 1104 1105 if (ieee80211_is_beacon(fc)) { 1106 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 1107 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 1108 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 0x18)); 1109 } 1110 1111 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 1112 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 1113 1114 if (ieee80211_is_back_req(hdr->frame_control)) { 1115 struct ieee80211_bar *bar; 1116 1117 bar = (struct ieee80211_bar *)skb->data; 1118 seqno = le16_to_cpu(bar->start_seq_num); 1119 } 1120 1121 val = MT_TXD3_SN_VALID | 1122 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 1123 txwi[3] |= cpu_to_le32(val); 1124 txwi[7] &= ~cpu_to_le32(MT_TXD7_HW_AMSDU); 1125 } 1126 1127 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 1128 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 1129 txwi[7] |= cpu_to_le32(val); 1130 } 1131 1132 static u16 1133 mt7915_mac_tx_rate_val(struct mt76_phy *mphy, struct ieee80211_vif *vif, 1134 bool beacon, bool mcast) 1135 { 1136 u8 mode = 0, band = mphy->chandef.chan->band; 1137 int rateidx = 0, mcast_rate; 1138 1139 if (beacon) { 1140 struct cfg80211_bitrate_mask *mask; 1141 1142 mask = &vif->bss_conf.beacon_tx_rate; 1143 if (hweight16(mask->control[band].he_mcs[0]) == 1) { 1144 rateidx = ffs(mask->control[band].he_mcs[0]) - 1; 1145 mode = MT_PHY_TYPE_HE_SU; 1146 goto out; 1147 } else if (hweight16(mask->control[band].vht_mcs[0]) == 1) { 1148 rateidx = ffs(mask->control[band].vht_mcs[0]) - 1; 1149 mode = MT_PHY_TYPE_VHT; 1150 goto out; 1151 } else if (hweight8(mask->control[band].ht_mcs[0]) == 1) { 1152 rateidx = ffs(mask->control[band].ht_mcs[0]) - 1; 1153 mode = MT_PHY_TYPE_HT; 1154 goto out; 1155 } else if (hweight32(mask->control[band].legacy) == 1) { 1156 rateidx = ffs(mask->control[band].legacy) - 1; 1157 goto legacy; 1158 } 1159 } 1160 1161 mcast_rate = vif->bss_conf.mcast_rate[band]; 1162 if (mcast && mcast_rate > 0) 1163 rateidx = mcast_rate - 1; 1164 else 1165 rateidx = ffs(vif->bss_conf.basic_rates) - 1; 1166 1167 legacy: 1168 rateidx = mt76_calculate_default_rate(mphy, rateidx); 1169 mode = rateidx >> 8; 1170 rateidx &= GENMASK(7, 0); 1171 1172 out: 1173 return FIELD_PREP(MT_TX_RATE_IDX, rateidx) | 1174 FIELD_PREP(MT_TX_RATE_MODE, mode); 1175 } 1176 1177 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, 1178 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 1179 struct ieee80211_key_conf *key, bool beacon) 1180 { 1181 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1182 struct ieee80211_vif *vif = info->control.vif; 1183 struct mt76_phy *mphy = &dev->mphy; 1184 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; 1185 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0, band_idx = 0; 1186 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1187 bool mcast = false; 1188 u16 tx_count = 15; 1189 u32 val; 1190 1191 if (vif) { 1192 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1193 1194 omac_idx = mvif->mt76.omac_idx; 1195 wmm_idx = mvif->mt76.wmm_idx; 1196 band_idx = mvif->mt76.band_idx; 1197 } 1198 1199 if (ext_phy && dev->mt76.phy2) 1200 mphy = dev->mt76.phy2; 1201 1202 if (beacon) { 1203 p_fmt = MT_TX_TYPE_FW; 1204 q_idx = MT_LMAC_BCN0; 1205 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 1206 p_fmt = MT_TX_TYPE_CT; 1207 q_idx = MT_LMAC_ALTX0; 1208 } else { 1209 p_fmt = MT_TX_TYPE_CT; 1210 q_idx = wmm_idx * MT7915_MAX_WMM_SETS + 1211 mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); 1212 } 1213 1214 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 1215 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 1216 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 1217 txwi[0] = cpu_to_le32(val); 1218 1219 val = MT_TXD1_LONG_FORMAT | MT_TXD1_VTA | 1220 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 1221 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 1222 1223 if (ext_phy || band_idx) 1224 val |= MT_TXD1_TGID; 1225 1226 txwi[1] = cpu_to_le32(val); 1227 1228 txwi[2] = 0; 1229 1230 val = MT_TXD3_SW_POWER_MGMT | 1231 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 1232 if (key) 1233 val |= MT_TXD3_PROTECT_FRAME; 1234 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1235 val |= MT_TXD3_NO_ACK; 1236 1237 txwi[3] = cpu_to_le32(val); 1238 txwi[4] = 0; 1239 1240 val = FIELD_PREP(MT_TXD5_PID, pid); 1241 if (pid >= MT_PACKET_ID_FIRST) 1242 val |= MT_TXD5_TX_STATUS_HOST; 1243 txwi[5] = cpu_to_le32(val); 1244 1245 txwi[6] = 0; 1246 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 1247 1248 if (is_8023) 1249 mt7915_mac_write_txwi_8023(dev, txwi, skb, wcid); 1250 else 1251 mt7915_mac_write_txwi_80211(dev, txwi, skb, key, &mcast); 1252 1253 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 1254 u16 rate = mt7915_mac_tx_rate_val(mphy, vif, beacon, mcast); 1255 1256 /* hardware won't add HTC for mgmt/ctrl frame */ 1257 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 1258 1259 val = MT_TXD6_FIXED_BW | 1260 FIELD_PREP(MT_TXD6_TX_RATE, rate); 1261 txwi[6] |= cpu_to_le32(val); 1262 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1263 } 1264 1265 if (mt76_testmode_enabled(mphy)) 1266 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 1267 } 1268 1269 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1270 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1271 struct ieee80211_sta *sta, 1272 struct mt76_tx_info *tx_info) 1273 { 1274 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 1275 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1276 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1277 struct ieee80211_key_conf *key = info->control.hw_key; 1278 struct ieee80211_vif *vif = info->control.vif; 1279 struct mt76_txwi_cache *t; 1280 struct mt7915_txp *txp; 1281 int id, i, nbuf = tx_info->nbuf - 1; 1282 u8 *txwi = (u8 *)txwi_ptr; 1283 int pid; 1284 1285 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1286 return -EINVAL; 1287 1288 if (!wcid) 1289 wcid = &dev->mt76.global_wcid; 1290 1291 if (sta) { 1292 struct mt7915_sta *msta; 1293 1294 msta = (struct mt7915_sta *)sta->drv_priv; 1295 1296 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 1297 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 1298 msta->jiffies = jiffies; 1299 } 1300 } 1301 1302 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 1303 t->skb = tx_info->skb; 1304 1305 id = mt76_token_consume(mdev, &t); 1306 if (id < 0) 1307 return id; 1308 1309 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1310 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, pid, key, 1311 false); 1312 1313 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE); 1314 for (i = 0; i < nbuf; i++) { 1315 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1316 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 1317 } 1318 txp->nbuf = nbuf; 1319 1320 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 1321 1322 if (!key) 1323 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1324 1325 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 1326 ieee80211_is_mgmt(hdr->frame_control)) 1327 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1328 1329 if (vif) { 1330 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1331 1332 txp->bss_idx = mvif->mt76.idx; 1333 } 1334 1335 txp->token = cpu_to_le16(id); 1336 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 1337 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 1338 else 1339 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 1340 tx_info->skb = DMA_DUMMY_DATA; 1341 1342 /* pass partial skb header to fw */ 1343 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1344 tx_info->buf[1].skip_unmap = true; 1345 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1346 1347 return 0; 1348 } 1349 1350 static void 1351 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1352 { 1353 struct mt7915_sta *msta; 1354 u16 fc, tid; 1355 u32 val; 1356 1357 if (!sta || !(sta->ht_cap.ht_supported || sta->he_cap.has_he)) 1358 return; 1359 1360 tid = le32_get_bits(txwi[1], MT_TXD1_TID); 1361 if (tid >= 6) /* skip VO queue */ 1362 return; 1363 1364 val = le32_to_cpu(txwi[2]); 1365 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1366 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1367 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1368 return; 1369 1370 msta = (struct mt7915_sta *)sta->drv_priv; 1371 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1372 ieee80211_start_tx_ba_session(sta, tid, 0); 1373 } 1374 1375 static void 1376 mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1377 { 1378 struct mt7915_txp *txp; 1379 int i; 1380 1381 txp = mt7915_txwi_to_txp(dev, t); 1382 for (i = 0; i < txp->nbuf; i++) 1383 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), 1384 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); 1385 } 1386 1387 static void 1388 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, 1389 struct ieee80211_sta *sta, struct list_head *free_list) 1390 { 1391 struct mt76_dev *mdev = &dev->mt76; 1392 struct mt76_wcid *wcid; 1393 __le32 *txwi; 1394 u16 wcid_idx; 1395 1396 mt7915_txp_skb_unmap(mdev, t); 1397 if (!t->skb) 1398 goto out; 1399 1400 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1401 if (sta) { 1402 wcid = (struct mt76_wcid *)sta->drv_priv; 1403 wcid_idx = wcid->idx; 1404 1405 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1406 mt7915_tx_check_aggr(sta, txwi); 1407 } else { 1408 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); 1409 } 1410 1411 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1412 1413 out: 1414 t->skb = NULL; 1415 mt76_put_txwi(mdev, t); 1416 } 1417 1418 static void 1419 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 1420 { 1421 struct mt7915_tx_free *free = (struct mt7915_tx_free *)data; 1422 struct mt76_dev *mdev = &dev->mt76; 1423 struct mt76_phy *mphy_ext = mdev->phy2; 1424 struct mt76_txwi_cache *txwi; 1425 struct ieee80211_sta *sta = NULL; 1426 LIST_HEAD(free_list); 1427 struct sk_buff *skb, *tmp; 1428 void *end = data + len; 1429 bool v3, wake = false; 1430 u16 total, count = 0; 1431 u32 txd = le32_to_cpu(free->txd); 1432 __le32 *cur_info; 1433 1434 /* clean DMA queues and unmap buffers first */ 1435 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1436 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1437 if (mphy_ext) { 1438 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 1439 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 1440 } 1441 1442 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 1443 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 1444 if (WARN_ON_ONCE((void *)&free->info[total >> v3] > end)) 1445 return; 1446 1447 for (cur_info = &free->info[0]; count < total; cur_info++) { 1448 u32 msdu, info = le32_to_cpu(*cur_info); 1449 u8 i; 1450 1451 /* 1452 * 1'b1: new wcid pair. 1453 * 1'b0: msdu_id with the same 'wcid pair' as above. 1454 */ 1455 if (info & MT_TX_FREE_PAIR) { 1456 struct mt7915_sta *msta; 1457 struct mt76_wcid *wcid; 1458 u16 idx; 1459 1460 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 1461 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1462 sta = wcid_to_sta(wcid); 1463 if (!sta) 1464 continue; 1465 1466 msta = container_of(wcid, struct mt7915_sta, wcid); 1467 spin_lock_bh(&dev->sta_poll_lock); 1468 if (list_empty(&msta->poll_list)) 1469 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1470 spin_unlock_bh(&dev->sta_poll_lock); 1471 continue; 1472 } 1473 1474 if (v3 && (info & MT_TX_FREE_MPDU_HEADER)) 1475 continue; 1476 1477 for (i = 0; i < 1 + v3; i++) { 1478 if (v3) { 1479 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 1480 if (msdu == MT_TX_FREE_MSDU_ID_V3) 1481 continue; 1482 } else { 1483 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 1484 } 1485 count++; 1486 txwi = mt76_token_release(mdev, msdu, &wake); 1487 if (!txwi) 1488 continue; 1489 1490 mt7915_txwi_free(dev, txwi, sta, &free_list); 1491 } 1492 } 1493 1494 mt7915_mac_sta_poll(dev); 1495 1496 if (wake) 1497 mt76_set_tx_blocked(&dev->mt76, false); 1498 1499 mt76_worker_schedule(&dev->mt76.tx_worker); 1500 1501 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1502 skb_list_del_init(skb); 1503 napi_consume_skb(skb, 1); 1504 } 1505 } 1506 1507 static bool 1508 mt7915_mac_add_txs_skb(struct mt7915_dev *dev, struct mt76_wcid *wcid, int pid, 1509 __le32 *txs_data, struct mt76_sta_stats *stats) 1510 { 1511 struct ieee80211_supported_band *sband; 1512 struct mt76_dev *mdev = &dev->mt76; 1513 struct mt76_phy *mphy; 1514 struct ieee80211_tx_info *info; 1515 struct sk_buff_head list; 1516 struct rate_info rate = {}; 1517 struct sk_buff *skb; 1518 bool cck = false; 1519 u32 txrate, txs, mode; 1520 1521 mt76_tx_status_lock(mdev, &list); 1522 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1523 if (!skb) 1524 goto out_no_skb; 1525 1526 txs = le32_to_cpu(txs_data[0]); 1527 1528 info = IEEE80211_SKB_CB(skb); 1529 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1530 info->flags |= IEEE80211_TX_STAT_ACK; 1531 1532 info->status.ampdu_len = 1; 1533 info->status.ampdu_ack_len = !!(info->flags & 1534 IEEE80211_TX_STAT_ACK); 1535 1536 info->status.rates[0].idx = -1; 1537 1538 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1539 1540 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1541 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1542 1543 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1544 stats->tx_nss[rate.nss - 1]++; 1545 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1546 stats->tx_mcs[rate.mcs]++; 1547 1548 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1549 switch (mode) { 1550 case MT_PHY_TYPE_CCK: 1551 cck = true; 1552 fallthrough; 1553 case MT_PHY_TYPE_OFDM: 1554 mphy = &dev->mphy; 1555 if (wcid->ext_phy && dev->mt76.phy2) 1556 mphy = dev->mt76.phy2; 1557 1558 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1559 sband = &mphy->sband_5g.sband; 1560 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 1561 sband = &mphy->sband_6g.sband; 1562 else 1563 sband = &mphy->sband_2g.sband; 1564 1565 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1566 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1567 break; 1568 case MT_PHY_TYPE_HT: 1569 case MT_PHY_TYPE_HT_GF: 1570 if (rate.mcs > 31) 1571 goto out; 1572 1573 rate.flags = RATE_INFO_FLAGS_MCS; 1574 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1575 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1576 break; 1577 case MT_PHY_TYPE_VHT: 1578 if (rate.mcs > 9) 1579 goto out; 1580 1581 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1582 break; 1583 case MT_PHY_TYPE_HE_SU: 1584 case MT_PHY_TYPE_HE_EXT_SU: 1585 case MT_PHY_TYPE_HE_TB: 1586 case MT_PHY_TYPE_HE_MU: 1587 if (rate.mcs > 11) 1588 goto out; 1589 1590 rate.he_gi = wcid->rate.he_gi; 1591 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1592 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1593 break; 1594 default: 1595 goto out; 1596 } 1597 1598 stats->tx_mode[mode]++; 1599 1600 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1601 case IEEE80211_STA_RX_BW_160: 1602 rate.bw = RATE_INFO_BW_160; 1603 stats->tx_bw[3]++; 1604 break; 1605 case IEEE80211_STA_RX_BW_80: 1606 rate.bw = RATE_INFO_BW_80; 1607 stats->tx_bw[2]++; 1608 break; 1609 case IEEE80211_STA_RX_BW_40: 1610 rate.bw = RATE_INFO_BW_40; 1611 stats->tx_bw[1]++; 1612 break; 1613 default: 1614 rate.bw = RATE_INFO_BW_20; 1615 stats->tx_bw[0]++; 1616 break; 1617 } 1618 wcid->rate = rate; 1619 1620 out: 1621 mt76_tx_status_skb_done(mdev, skb, &list); 1622 1623 out_no_skb: 1624 mt76_tx_status_unlock(mdev, &list); 1625 1626 return !!skb; 1627 } 1628 1629 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1630 { 1631 struct mt7915_sta *msta = NULL; 1632 struct mt76_wcid *wcid; 1633 __le32 *txs_data = data; 1634 u16 wcidx; 1635 u8 pid; 1636 1637 if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1) 1638 return; 1639 1640 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1641 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1642 1643 if (pid < MT_PACKET_ID_FIRST) 1644 return; 1645 1646 if (wcidx >= mt7915_wtbl_size(dev)) 1647 return; 1648 1649 rcu_read_lock(); 1650 1651 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1652 if (!wcid) 1653 goto out; 1654 1655 msta = container_of(wcid, struct mt7915_sta, wcid); 1656 1657 mt7915_mac_add_txs_skb(dev, wcid, pid, txs_data, &msta->stats); 1658 1659 if (!wcid->sta) 1660 goto out; 1661 1662 spin_lock_bh(&dev->sta_poll_lock); 1663 if (list_empty(&msta->poll_list)) 1664 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1665 spin_unlock_bh(&dev->sta_poll_lock); 1666 1667 out: 1668 rcu_read_unlock(); 1669 } 1670 1671 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1672 { 1673 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1674 __le32 *rxd = (__le32 *)data; 1675 __le32 *end = (__le32 *)&rxd[len / 4]; 1676 enum rx_pkt_type type; 1677 1678 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1679 1680 switch (type) { 1681 case PKT_TYPE_TXRX_NOTIFY: 1682 mt7915_mac_tx_free(dev, data, len); 1683 return false; 1684 case PKT_TYPE_TXS: 1685 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1686 mt7915_mac_add_txs(dev, rxd); 1687 return false; 1688 case PKT_TYPE_RX_FW_MONITOR: 1689 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1690 return false; 1691 default: 1692 return true; 1693 } 1694 } 1695 1696 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1697 struct sk_buff *skb) 1698 { 1699 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1700 __le32 *rxd = (__le32 *)skb->data; 1701 __le32 *end = (__le32 *)&skb->data[skb->len]; 1702 enum rx_pkt_type type; 1703 1704 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1705 1706 switch (type) { 1707 case PKT_TYPE_TXRX_NOTIFY: 1708 mt7915_mac_tx_free(dev, skb->data, skb->len); 1709 napi_consume_skb(skb, 1); 1710 break; 1711 case PKT_TYPE_RX_EVENT: 1712 mt7915_mcu_rx_event(dev, skb); 1713 break; 1714 case PKT_TYPE_TXRXV: 1715 mt7915_mac_fill_rx_vector(dev, skb); 1716 break; 1717 case PKT_TYPE_TXS: 1718 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1719 mt7915_mac_add_txs(dev, rxd); 1720 dev_kfree_skb(skb); 1721 break; 1722 case PKT_TYPE_RX_FW_MONITOR: 1723 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1724 dev_kfree_skb(skb); 1725 break; 1726 case PKT_TYPE_NORMAL: 1727 if (!mt7915_mac_fill_rx(dev, skb)) { 1728 mt76_rx(&dev->mt76, q, skb); 1729 return; 1730 } 1731 fallthrough; 1732 default: 1733 dev_kfree_skb(skb); 1734 break; 1735 } 1736 } 1737 1738 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1739 { 1740 if (!e->txwi) { 1741 dev_kfree_skb_any(e->skb); 1742 return; 1743 } 1744 1745 /* error path */ 1746 if (e->skb == DMA_DUMMY_DATA) { 1747 struct mt76_txwi_cache *t; 1748 struct mt7915_txp *txp; 1749 1750 txp = mt7915_txwi_to_txp(mdev, e->txwi); 1751 t = mt76_token_put(mdev, le16_to_cpu(txp->token)); 1752 e->skb = t ? t->skb : NULL; 1753 } 1754 1755 if (e->skb) 1756 mt76_tx_complete_skb(mdev, e->wcid, e->skb); 1757 } 1758 1759 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1760 { 1761 struct mt7915_dev *dev = phy->dev; 1762 u32 reg = MT_WF_PHY_RX_CTRL1(phy->band_idx); 1763 1764 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1765 mt76_set(dev, reg, BIT(11) | BIT(9)); 1766 } 1767 1768 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1769 { 1770 struct mt7915_dev *dev = phy->dev; 1771 int i; 1772 1773 for (i = 0; i < 4; i++) { 1774 mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i)); 1775 mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i)); 1776 } 1777 1778 i = 0; 1779 phy->mt76->survey_time = ktime_get_boottime(); 1780 if (phy->band_idx) 1781 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2; 1782 1783 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2); 1784 1785 /* reset airtime counters */ 1786 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->band_idx), 1787 MT_WF_RMAC_MIB_RXTIME_CLR); 1788 1789 mt7915_mcu_get_chan_mib_info(phy, true); 1790 } 1791 1792 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1793 { 1794 s16 coverage_class = phy->coverage_class; 1795 struct mt7915_dev *dev = phy->dev; 1796 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1797 u32 val, reg_offset; 1798 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1799 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1800 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1801 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1802 int offset; 1803 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1804 1805 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1806 return; 1807 1808 if (ext_phy) 1809 coverage_class = max_t(s16, dev->phy.coverage_class, 1810 ext_phy->coverage_class); 1811 1812 mt76_set(dev, MT_ARB_SCR(phy->band_idx), 1813 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1814 udelay(1); 1815 1816 offset = 3 * coverage_class; 1817 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1818 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1819 1820 mt76_wr(dev, MT_TMAC_CDTR(phy->band_idx), cck + reg_offset); 1821 mt76_wr(dev, MT_TMAC_ODTR(phy->band_idx), ofdm + reg_offset); 1822 mt76_wr(dev, MT_TMAC_ICR0(phy->band_idx), 1823 FIELD_PREP(MT_IFS_EIFS_OFDM, a_band ? 84 : 78) | 1824 FIELD_PREP(MT_IFS_RIFS, 2) | 1825 FIELD_PREP(MT_IFS_SIFS, 10) | 1826 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1827 1828 mt76_wr(dev, MT_TMAC_ICR1(phy->band_idx), 1829 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1830 1831 if (phy->slottime < 20 || a_band) 1832 val = MT7915_CFEND_RATE_DEFAULT; 1833 else 1834 val = MT7915_CFEND_RATE_11B; 1835 1836 mt76_rmw_field(dev, MT_AGG_ACR0(phy->band_idx), MT_AGG_ACR_CFEND_RATE, val); 1837 mt76_clear(dev, MT_ARB_SCR(phy->band_idx), 1838 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1839 } 1840 1841 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy) 1842 { 1843 u32 reg; 1844 1845 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(ext_phy) : 1846 MT_WF_PHY_RXTD12_MT7916(ext_phy); 1847 mt76_set(dev, reg, 1848 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1849 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1850 1851 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(ext_phy) : 1852 MT_WF_PHY_RX_CTRL1_MT7916(ext_phy); 1853 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1854 } 1855 1856 static u8 1857 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1858 { 1859 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1860 struct mt7915_dev *dev = phy->dev; 1861 u32 val, sum = 0, n = 0; 1862 int nss, i; 1863 1864 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1865 u32 reg = is_mt7915(&dev->mt76) ? 1866 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1867 MT_WF_IRPI_NSS_MT7916(idx, nss); 1868 1869 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1870 val = mt76_rr(dev, reg); 1871 sum += val * nf_power[i]; 1872 n += val; 1873 } 1874 } 1875 1876 if (!n) 1877 return 0; 1878 1879 return sum / n; 1880 } 1881 1882 void mt7915_update_channel(struct mt76_phy *mphy) 1883 { 1884 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv; 1885 struct mt76_channel_state *state = mphy->chan_state; 1886 int nf; 1887 1888 mt7915_mcu_get_chan_mib_info(phy, false); 1889 1890 nf = mt7915_phy_get_nf(phy, phy->band_idx); 1891 if (!phy->noise) 1892 phy->noise = nf << 4; 1893 else if (nf) 1894 phy->noise += nf - (phy->noise >> 4); 1895 1896 state->noise = -(phy->noise >> 4); 1897 } 1898 1899 static bool 1900 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1901 { 1902 bool ret; 1903 1904 ret = wait_event_timeout(dev->reset_wait, 1905 (READ_ONCE(dev->reset_state) & state), 1906 MT7915_RESET_TIMEOUT); 1907 1908 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1909 return ret; 1910 } 1911 1912 static void 1913 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1914 { 1915 struct ieee80211_hw *hw = priv; 1916 1917 switch (vif->type) { 1918 case NL80211_IFTYPE_MESH_POINT: 1919 case NL80211_IFTYPE_ADHOC: 1920 case NL80211_IFTYPE_AP: 1921 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1922 break; 1923 default: 1924 break; 1925 } 1926 } 1927 1928 static void 1929 mt7915_update_beacons(struct mt7915_dev *dev) 1930 { 1931 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1932 IEEE80211_IFACE_ITER_RESUME_ALL, 1933 mt7915_update_vif_beacon, dev->mt76.hw); 1934 1935 if (!dev->mt76.phy2) 1936 return; 1937 1938 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw, 1939 IEEE80211_IFACE_ITER_RESUME_ALL, 1940 mt7915_update_vif_beacon, dev->mt76.phy2->hw); 1941 } 1942 1943 static void 1944 mt7915_dma_reset(struct mt7915_dev *dev) 1945 { 1946 struct mt76_phy *mphy_ext = dev->mt76.phy2; 1947 u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 1948 int i; 1949 1950 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 1951 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1952 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1953 1954 if (is_mt7915(&dev->mt76)) 1955 mt76_clear(dev, MT_WFDMA1_GLO_CFG, 1956 MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1957 MT_WFDMA1_GLO_CFG_RX_DMA_EN); 1958 if (dev->hif2) { 1959 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1960 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1961 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1962 1963 if (is_mt7915(&dev->mt76)) 1964 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 1965 MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1966 MT_WFDMA1_GLO_CFG_RX_DMA_EN); 1967 } 1968 1969 usleep_range(1000, 2000); 1970 1971 for (i = 0; i < __MT_TXQ_MAX; i++) { 1972 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 1973 if (mphy_ext) 1974 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true); 1975 } 1976 1977 for (i = 0; i < __MT_MCUQ_MAX; i++) 1978 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); 1979 1980 mt76_for_each_q_rx(&dev->mt76, i) 1981 mt76_queue_rx_reset(dev, i); 1982 1983 mt76_tx_status_check(&dev->mt76, true); 1984 1985 /* re-init prefetch settings after reset */ 1986 mt7915_dma_prefetch(dev); 1987 1988 mt76_set(dev, MT_WFDMA0_GLO_CFG, 1989 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1990 if (is_mt7915(&dev->mt76)) 1991 mt76_set(dev, MT_WFDMA1_GLO_CFG, 1992 MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1993 MT_WFDMA1_GLO_CFG_RX_DMA_EN | 1994 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 1995 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 1996 if (dev->hif2) { 1997 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1998 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1999 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 2000 2001 if (is_mt7915(&dev->mt76)) 2002 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 2003 MT_WFDMA1_GLO_CFG_TX_DMA_EN | 2004 MT_WFDMA1_GLO_CFG_RX_DMA_EN | 2005 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 2006 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 2007 } 2008 } 2009 2010 void mt7915_tx_token_put(struct mt7915_dev *dev) 2011 { 2012 struct mt76_txwi_cache *txwi; 2013 int id; 2014 2015 spin_lock_bh(&dev->mt76.token_lock); 2016 idr_for_each_entry(&dev->mt76.token, txwi, id) { 2017 mt7915_txwi_free(dev, txwi, NULL, NULL); 2018 dev->mt76.token_count--; 2019 } 2020 spin_unlock_bh(&dev->mt76.token_lock); 2021 idr_destroy(&dev->mt76.token); 2022 } 2023 2024 /* system error recovery */ 2025 void mt7915_mac_reset_work(struct work_struct *work) 2026 { 2027 struct mt7915_phy *phy2; 2028 struct mt76_phy *ext_phy; 2029 struct mt7915_dev *dev; 2030 2031 dev = container_of(work, struct mt7915_dev, reset_work); 2032 ext_phy = dev->mt76.phy2; 2033 phy2 = ext_phy ? ext_phy->priv : NULL; 2034 2035 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA)) 2036 return; 2037 2038 ieee80211_stop_queues(mt76_hw(dev)); 2039 if (ext_phy) 2040 ieee80211_stop_queues(ext_phy->hw); 2041 2042 set_bit(MT76_RESET, &dev->mphy.state); 2043 set_bit(MT76_MCU_RESET, &dev->mphy.state); 2044 wake_up(&dev->mt76.mcu.wait); 2045 cancel_delayed_work_sync(&dev->mphy.mac_work); 2046 if (phy2) { 2047 set_bit(MT76_RESET, &phy2->mt76->state); 2048 cancel_delayed_work_sync(&phy2->mt76->mac_work); 2049 } 2050 mt76_worker_disable(&dev->mt76.tx_worker); 2051 napi_disable(&dev->mt76.napi[0]); 2052 napi_disable(&dev->mt76.napi[1]); 2053 napi_disable(&dev->mt76.napi[2]); 2054 napi_disable(&dev->mt76.tx_napi); 2055 2056 mutex_lock(&dev->mt76.mutex); 2057 2058 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 2059 2060 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 2061 mt7915_dma_reset(dev); 2062 2063 mt7915_tx_token_put(dev); 2064 idr_init(&dev->mt76.token); 2065 2066 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 2067 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 2068 } 2069 2070 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 2071 clear_bit(MT76_RESET, &dev->mphy.state); 2072 if (phy2) 2073 clear_bit(MT76_RESET, &phy2->mt76->state); 2074 2075 local_bh_disable(); 2076 napi_enable(&dev->mt76.napi[0]); 2077 napi_schedule(&dev->mt76.napi[0]); 2078 2079 napi_enable(&dev->mt76.napi[1]); 2080 napi_schedule(&dev->mt76.napi[1]); 2081 2082 napi_enable(&dev->mt76.napi[2]); 2083 napi_schedule(&dev->mt76.napi[2]); 2084 local_bh_enable(); 2085 2086 tasklet_schedule(&dev->irq_tasklet); 2087 2088 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 2089 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 2090 2091 mt76_worker_enable(&dev->mt76.tx_worker); 2092 2093 napi_enable(&dev->mt76.tx_napi); 2094 napi_schedule(&dev->mt76.tx_napi); 2095 2096 ieee80211_wake_queues(mt76_hw(dev)); 2097 if (ext_phy) 2098 ieee80211_wake_queues(ext_phy->hw); 2099 2100 mutex_unlock(&dev->mt76.mutex); 2101 2102 mt7915_update_beacons(dev); 2103 2104 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 2105 MT7915_WATCHDOG_TIME); 2106 if (phy2) 2107 ieee80211_queue_delayed_work(ext_phy->hw, 2108 &phy2->mt76->mac_work, 2109 MT7915_WATCHDOG_TIME); 2110 } 2111 2112 void mt7915_mac_update_stats(struct mt7915_phy *phy) 2113 { 2114 struct mt7915_dev *dev = phy->dev; 2115 struct mib_stats *mib = &phy->mib; 2116 int i, aggr0, aggr1, cnt; 2117 u32 val; 2118 2119 cnt = mt76_rr(dev, MT_MIB_SDR3(phy->band_idx)); 2120 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 2121 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 2122 2123 cnt = mt76_rr(dev, MT_MIB_SDR4(phy->band_idx)); 2124 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 2125 2126 cnt = mt76_rr(dev, MT_MIB_SDR5(phy->band_idx)); 2127 mib->rx_mpdu_cnt += cnt; 2128 2129 cnt = mt76_rr(dev, MT_MIB_SDR6(phy->band_idx)); 2130 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 2131 2132 cnt = mt76_rr(dev, MT_MIB_SDR7(phy->band_idx)); 2133 mib->rx_vector_mismatch_cnt += FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 2134 2135 cnt = mt76_rr(dev, MT_MIB_SDR8(phy->band_idx)); 2136 mib->rx_delimiter_fail_cnt += FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 2137 2138 cnt = mt76_rr(dev, MT_MIB_SDR11(phy->band_idx)); 2139 mib->rx_len_mismatch_cnt += FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 2140 2141 cnt = mt76_rr(dev, MT_MIB_SDR12(phy->band_idx)); 2142 mib->tx_ampdu_cnt += cnt; 2143 2144 cnt = mt76_rr(dev, MT_MIB_SDR13(phy->band_idx)); 2145 mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 2146 2147 cnt = mt76_rr(dev, MT_MIB_SDR14(phy->band_idx)); 2148 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 2149 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 2150 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 2151 2152 cnt = mt76_rr(dev, MT_MIB_SDR15(phy->band_idx)); 2153 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 2154 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 2155 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 2156 2157 cnt = mt76_rr(dev, MT_MIB_SDR22(phy->band_idx)); 2158 mib->rx_ampdu_cnt += cnt; 2159 2160 cnt = mt76_rr(dev, MT_MIB_SDR23(phy->band_idx)); 2161 mib->rx_ampdu_bytes_cnt += cnt; 2162 2163 cnt = mt76_rr(dev, MT_MIB_SDR24(phy->band_idx)); 2164 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 2165 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 2166 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 2167 2168 cnt = mt76_rr(dev, MT_MIB_SDR25(phy->band_idx)); 2169 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 2170 2171 cnt = mt76_rr(dev, MT_MIB_SDR27(phy->band_idx)); 2172 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 2173 2174 cnt = mt76_rr(dev, MT_MIB_SDR28(phy->band_idx)); 2175 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 2176 2177 cnt = mt76_rr(dev, MT_MIB_SDR29(phy->band_idx)); 2178 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 2179 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 2180 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 2181 2182 cnt = mt76_rr(dev, MT_MIB_SDRVEC(phy->band_idx)); 2183 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 2184 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 2185 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 2186 2187 cnt = mt76_rr(dev, MT_MIB_SDR31(phy->band_idx)); 2188 mib->rx_ba_cnt += cnt; 2189 2190 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(phy->band_idx)); 2191 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 2192 2193 cnt = mt76_rr(dev, MT_MIB_DR8(phy->band_idx)); 2194 mib->tx_mu_mpdu_cnt += cnt; 2195 2196 cnt = mt76_rr(dev, MT_MIB_DR9(phy->band_idx)); 2197 mib->tx_mu_acked_mpdu_cnt += cnt; 2198 2199 cnt = mt76_rr(dev, MT_MIB_DR11(phy->band_idx)); 2200 mib->tx_su_acked_mpdu_cnt += cnt; 2201 2202 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(phy->band_idx)); 2203 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 2204 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 2205 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 2206 2207 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2208 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2209 mib->tx_amsdu[i] += cnt; 2210 mib->tx_amsdu_cnt += cnt; 2211 } 2212 2213 aggr0 = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 2214 if (is_mt7915(&dev->mt76)) { 2215 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 2216 val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 4))); 2217 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 2218 mib->ack_fail_cnt += 2219 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 2220 2221 val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 4))); 2222 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2223 mib->rts_retries_cnt += 2224 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 2225 2226 val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i)); 2227 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 2228 dev->mt76.aggr_stats[aggr0++] += val >> 16; 2229 2230 val = mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i)); 2231 dev->mt76.aggr_stats[aggr1++] += val & 0xffff; 2232 dev->mt76.aggr_stats[aggr1++] += val >> 16; 2233 } 2234 2235 cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx)); 2236 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 2237 2238 cnt = mt76_rr(dev, MT_MIB_SDR33(phy->band_idx)); 2239 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 2240 2241 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(phy->band_idx)); 2242 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 2243 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 2244 2245 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(phy->band_idx)); 2246 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 2247 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 2248 2249 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(phy->band_idx)); 2250 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 2251 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 2252 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 2253 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 2254 } else { 2255 for (i = 0; i < 2; i++) { 2256 /* rts count */ 2257 val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 2))); 2258 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 2259 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 2260 2261 /* rts retry count */ 2262 val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 2))); 2263 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 2264 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 2265 2266 /* ba miss count */ 2267 val = mt76_rr(dev, MT_MIB_MB_SDR2(phy->band_idx, (i << 2))); 2268 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 2269 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 2270 2271 /* ack fail count */ 2272 val = mt76_rr(dev, MT_MIB_MB_BFTF(phy->band_idx, (i << 2))); 2273 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 2274 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 2275 } 2276 2277 for (i = 0; i < 8; i++) { 2278 val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i)); 2279 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 2280 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 2281 } 2282 2283 cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx)); 2284 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 2285 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 2286 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 2287 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 2288 2289 cnt = mt76_rr(dev, MT_MIB_BFCR7(phy->band_idx)); 2290 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 2291 2292 cnt = mt76_rr(dev, MT_MIB_BFCR2(phy->band_idx)); 2293 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 2294 2295 cnt = mt76_rr(dev, MT_MIB_BFCR0(phy->band_idx)); 2296 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 2297 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 2298 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 2299 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 2300 2301 cnt = mt76_rr(dev, MT_MIB_BFCR1(phy->band_idx)); 2302 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 2303 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 2304 } 2305 } 2306 2307 void mt7915_mac_sta_rc_work(struct work_struct *work) 2308 { 2309 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 2310 struct ieee80211_sta *sta; 2311 struct ieee80211_vif *vif; 2312 struct mt7915_sta *msta; 2313 u32 changed; 2314 LIST_HEAD(list); 2315 2316 spin_lock_bh(&dev->sta_poll_lock); 2317 list_splice_init(&dev->sta_rc_list, &list); 2318 2319 while (!list_empty(&list)) { 2320 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2321 list_del_init(&msta->rc_list); 2322 changed = msta->changed; 2323 msta->changed = 0; 2324 spin_unlock_bh(&dev->sta_poll_lock); 2325 2326 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2327 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2328 2329 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2330 IEEE80211_RC_NSS_CHANGED | 2331 IEEE80211_RC_BW_CHANGED)) 2332 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2333 2334 if (changed & IEEE80211_RC_SMPS_CHANGED) 2335 mt7915_mcu_add_smps(dev, vif, sta); 2336 2337 spin_lock_bh(&dev->sta_poll_lock); 2338 } 2339 2340 spin_unlock_bh(&dev->sta_poll_lock); 2341 } 2342 2343 void mt7915_mac_work(struct work_struct *work) 2344 { 2345 struct mt7915_phy *phy; 2346 struct mt76_phy *mphy; 2347 2348 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2349 mac_work.work); 2350 phy = mphy->priv; 2351 2352 mutex_lock(&mphy->dev->mutex); 2353 2354 mt76_update_survey(mphy); 2355 if (++mphy->mac_work_count == 5) { 2356 mphy->mac_work_count = 0; 2357 2358 mt7915_mac_update_stats(phy); 2359 } 2360 2361 mutex_unlock(&mphy->dev->mutex); 2362 2363 mt76_tx_status_check(mphy->dev, false); 2364 2365 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2366 MT7915_WATCHDOG_TIME); 2367 } 2368 2369 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2370 { 2371 struct mt7915_dev *dev = phy->dev; 2372 2373 if (phy->rdd_state & BIT(0)) 2374 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2375 MT_RX_SEL0, 0); 2376 if (phy->rdd_state & BIT(1)) 2377 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2378 MT_RX_SEL0, 0); 2379 } 2380 2381 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2382 { 2383 int err, region; 2384 2385 switch (dev->mt76.region) { 2386 case NL80211_DFS_ETSI: 2387 region = 0; 2388 break; 2389 case NL80211_DFS_JP: 2390 region = 2; 2391 break; 2392 case NL80211_DFS_FCC: 2393 default: 2394 region = 1; 2395 break; 2396 } 2397 2398 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2399 MT_RX_SEL0, region); 2400 if (err < 0) 2401 return err; 2402 2403 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2404 MT_RX_SEL0, 1); 2405 } 2406 2407 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2408 { 2409 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2410 struct mt7915_dev *dev = phy->dev; 2411 int err; 2412 2413 /* start CAC */ 2414 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, phy->band_idx, 2415 MT_RX_SEL0, 0); 2416 if (err < 0) 2417 return err; 2418 2419 err = mt7915_dfs_start_rdd(dev, phy->band_idx); 2420 if (err < 0) 2421 return err; 2422 2423 phy->rdd_state |= BIT(phy->band_idx); 2424 2425 if (!is_mt7915(&dev->mt76)) 2426 return 0; 2427 2428 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2429 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2430 err = mt7915_dfs_start_rdd(dev, 1); 2431 if (err < 0) 2432 return err; 2433 2434 phy->rdd_state |= BIT(1); 2435 } 2436 2437 return 0; 2438 } 2439 2440 static int 2441 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2442 { 2443 const struct mt7915_dfs_radar_spec *radar_specs; 2444 struct mt7915_dev *dev = phy->dev; 2445 int err, i; 2446 2447 switch (dev->mt76.region) { 2448 case NL80211_DFS_FCC: 2449 radar_specs = &fcc_radar_specs; 2450 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2451 if (err < 0) 2452 return err; 2453 break; 2454 case NL80211_DFS_ETSI: 2455 radar_specs = &etsi_radar_specs; 2456 break; 2457 case NL80211_DFS_JP: 2458 radar_specs = &jp_radar_specs; 2459 break; 2460 default: 2461 return -EINVAL; 2462 } 2463 2464 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2465 err = mt7915_mcu_set_radar_th(dev, i, 2466 &radar_specs->radar_pattern[i]); 2467 if (err < 0) 2468 return err; 2469 } 2470 2471 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2472 } 2473 2474 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2475 { 2476 struct mt7915_dev *dev = phy->dev; 2477 enum mt76_dfs_state dfs_state, prev_state; 2478 int err; 2479 2480 prev_state = phy->mt76->dfs_state; 2481 dfs_state = mt76_phy_dfs_state(phy->mt76); 2482 2483 if (prev_state == dfs_state) 2484 return 0; 2485 2486 if (prev_state == MT_DFS_STATE_UNKNOWN) 2487 mt7915_dfs_stop_radar_detector(phy); 2488 2489 if (dfs_state == MT_DFS_STATE_DISABLED) 2490 goto stop; 2491 2492 if (prev_state <= MT_DFS_STATE_DISABLED) { 2493 err = mt7915_dfs_init_radar_specs(phy); 2494 if (err < 0) 2495 return err; 2496 2497 err = mt7915_dfs_start_radar_detector(phy); 2498 if (err < 0) 2499 return err; 2500 2501 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2502 } 2503 2504 if (dfs_state == MT_DFS_STATE_CAC) 2505 return 0; 2506 2507 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2508 phy->band_idx, MT_RX_SEL0, 0); 2509 if (err < 0) { 2510 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2511 return err; 2512 } 2513 2514 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2515 return 0; 2516 2517 stop: 2518 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, 2519 phy->band_idx, MT_RX_SEL0, 0); 2520 if (err < 0) 2521 return err; 2522 2523 mt7915_dfs_stop_radar_detector(phy); 2524 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2525 2526 return 0; 2527 } 2528 2529 static int 2530 mt7915_mac_twt_duration_align(int duration) 2531 { 2532 return duration << 8; 2533 } 2534 2535 static u64 2536 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2537 struct mt7915_twt_flow *flow) 2538 { 2539 struct mt7915_twt_flow *iter, *iter_next; 2540 u32 duration = flow->duration << 8; 2541 u64 start_tsf; 2542 2543 iter = list_first_entry_or_null(&dev->twt_list, 2544 struct mt7915_twt_flow, list); 2545 if (!iter || !iter->sched || iter->start_tsf > duration) { 2546 /* add flow as first entry in the list */ 2547 list_add(&flow->list, &dev->twt_list); 2548 return 0; 2549 } 2550 2551 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2552 start_tsf = iter->start_tsf + 2553 mt7915_mac_twt_duration_align(iter->duration); 2554 if (list_is_last(&iter->list, &dev->twt_list)) 2555 break; 2556 2557 if (!iter_next->sched || 2558 iter_next->start_tsf > start_tsf + duration) { 2559 list_add(&flow->list, &iter->list); 2560 goto out; 2561 } 2562 } 2563 2564 /* add flow as last entry in the list */ 2565 list_add_tail(&flow->list, &dev->twt_list); 2566 out: 2567 return start_tsf; 2568 } 2569 2570 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2571 { 2572 struct ieee80211_twt_params *twt_agrt; 2573 u64 interval, duration; 2574 u16 mantissa; 2575 u8 exp; 2576 2577 /* only individual agreement supported */ 2578 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2579 return -EOPNOTSUPP; 2580 2581 /* only 256us unit supported */ 2582 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2583 return -EOPNOTSUPP; 2584 2585 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2586 2587 /* explicit agreement not supported */ 2588 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2589 return -EOPNOTSUPP; 2590 2591 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2592 le16_to_cpu(twt_agrt->req_type)); 2593 mantissa = le16_to_cpu(twt_agrt->mantissa); 2594 duration = twt_agrt->min_twt_dur << 8; 2595 2596 interval = (u64)mantissa << exp; 2597 if (interval < duration) 2598 return -EOPNOTSUPP; 2599 2600 return 0; 2601 } 2602 2603 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2604 struct ieee80211_sta *sta, 2605 struct ieee80211_twt_setup *twt) 2606 { 2607 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2608 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2609 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2610 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2611 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2612 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2613 struct mt7915_twt_flow *flow; 2614 int flowid, table_id; 2615 u8 exp; 2616 2617 if (mt7915_mac_check_twt_req(twt)) 2618 goto out; 2619 2620 mutex_lock(&dev->mt76.mutex); 2621 2622 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2623 goto unlock; 2624 2625 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2626 goto unlock; 2627 2628 flowid = ffs(~msta->twt.flowid_mask) - 1; 2629 le16p_replace_bits(&twt_agrt->req_type, flowid, 2630 IEEE80211_TWT_REQTYPE_FLOWID); 2631 2632 table_id = ffs(~dev->twt.table_mask) - 1; 2633 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2634 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2635 2636 flow = &msta->twt.flow[flowid]; 2637 memset(flow, 0, sizeof(*flow)); 2638 INIT_LIST_HEAD(&flow->list); 2639 flow->wcid = msta->wcid.idx; 2640 flow->table_id = table_id; 2641 flow->id = flowid; 2642 flow->duration = twt_agrt->min_twt_dur; 2643 flow->mantissa = twt_agrt->mantissa; 2644 flow->exp = exp; 2645 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2646 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2647 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2648 2649 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2650 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2651 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2652 u64 flow_tsf, curr_tsf; 2653 u32 rem; 2654 2655 flow->sched = true; 2656 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2657 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2658 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2659 flow_tsf = curr_tsf + interval - rem; 2660 twt_agrt->twt = cpu_to_le64(flow_tsf); 2661 } else { 2662 list_add_tail(&flow->list, &dev->twt_list); 2663 } 2664 flow->tsf = le64_to_cpu(twt_agrt->twt); 2665 2666 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2667 goto unlock; 2668 2669 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2670 dev->twt.table_mask |= BIT(table_id); 2671 msta->twt.flowid_mask |= BIT(flowid); 2672 dev->twt.n_agrt++; 2673 2674 unlock: 2675 mutex_unlock(&dev->mt76.mutex); 2676 out: 2677 le16p_replace_bits(&twt_agrt->req_type, setup_cmd, 2678 IEEE80211_TWT_REQTYPE_SETUP_CMD); 2679 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2680 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2681 } 2682 2683 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2684 struct mt7915_sta *msta, 2685 u8 flowid) 2686 { 2687 struct mt7915_twt_flow *flow; 2688 2689 lockdep_assert_held(&dev->mt76.mutex); 2690 2691 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2692 return; 2693 2694 if (!(msta->twt.flowid_mask & BIT(flowid))) 2695 return; 2696 2697 flow = &msta->twt.flow[flowid]; 2698 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2699 MCU_TWT_AGRT_DELETE)) 2700 return; 2701 2702 list_del_init(&flow->list); 2703 msta->twt.flowid_mask &= ~BIT(flowid); 2704 dev->twt.table_mask &= ~BIT(flow->table_id); 2705 dev->twt.n_agrt--; 2706 } 2707